Evan Cheng | afff941 | 2011-12-20 18:26:50 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM |
| 2 | ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB |
Chad Rosier | a07d3fc | 2011-11-11 06:20:39 +0000 | [diff] [blame] | 3 | |
| 4 | define i32 @t1(i1 %c) nounwind readnone { |
| 5 | entry: |
| 6 | ; ARM: t1 |
| 7 | ; ARM: movw r{{[1-9]}}, #10 |
| 8 | ; ARM: cmp r0, #0 |
| 9 | ; ARM: moveq r{{[1-9]}}, #20 |
| 10 | ; ARM: mov r0, r{{[1-9]}} |
| 11 | ; THUMB: t1 |
| 12 | ; THUMB: movs r{{[1-9]}}, #10 |
| 13 | ; THUMB: movt r{{[1-9]}}, #0 |
| 14 | ; THUMB: cmp r0, #0 |
| 15 | ; THUMB: it eq |
| 16 | ; THUMB: moveq r{{[1-9]}}, #20 |
| 17 | ; THUMB: mov r0, r{{[1-9]}} |
| 18 | %0 = select i1 %c, i32 10, i32 20 |
| 19 | ret i32 %0 |
| 20 | } |
| 21 | |
| 22 | define i32 @t2(i1 %c, i32 %a) nounwind readnone { |
| 23 | entry: |
| 24 | ; ARM: t2 |
| 25 | ; ARM: cmp r0, #0 |
| 26 | ; ARM: moveq r{{[1-9]}}, #20 |
| 27 | ; ARM: mov r0, r{{[1-9]}} |
| 28 | ; THUMB: t2 |
| 29 | ; THUMB: cmp r0, #0 |
| 30 | ; THUMB: it eq |
| 31 | ; THUMB: moveq r{{[1-9]}}, #20 |
| 32 | ; THUMB: mov r0, r{{[1-9]}} |
| 33 | %0 = select i1 %c, i32 %a, i32 20 |
| 34 | ret i32 %0 |
| 35 | } |
| 36 | |
| 37 | define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { |
| 38 | entry: |
| 39 | ; ARM: t3 |
| 40 | ; ARM: cmp r0, #0 |
| 41 | ; ARM: movne r{{[1-9]}}, r{{[1-9]}} |
| 42 | ; ARM: mov r0, r{{[1-9]}} |
| 43 | ; THUMB: t3 |
| 44 | ; THUMB: cmp r0, #0 |
| 45 | ; THUMB: it ne |
| 46 | ; THUMB: movne r{{[1-9]}}, r{{[1-9]}} |
| 47 | ; THUMB: mov r0, r{{[1-9]}} |
| 48 | %0 = select i1 %c, i32 %a, i32 %b |
| 49 | ret i32 %0 |
| 50 | } |
| 51 | |
| 52 | define i32 @t4(i1 %c) nounwind readnone { |
| 53 | entry: |
| 54 | ; ARM: t4 |
| 55 | ; ARM: mvn r{{[1-9]}}, #9 |
| 56 | ; ARM: cmp r0, #0 |
| 57 | ; ARM: mvneq r{{[1-9]}}, #0 |
| 58 | ; ARM: mov r0, r{{[1-9]}} |
| 59 | ; THUMB: t4 |
| 60 | ; THUMB: movw r{{[1-9]}}, #65526 |
| 61 | ; THUMB: movt r{{[1-9]}}, #65535 |
| 62 | ; THUMB: cmp r0, #0 |
| 63 | ; THUMB: it eq |
| 64 | ; THUMB: mvneq r{{[1-9]}}, #0 |
| 65 | ; THUMB: mov r0, r{{[1-9]}} |
| 66 | %0 = select i1 %c, i32 -10, i32 -1 |
| 67 | ret i32 %0 |
| 68 | } |
| 69 | |
| 70 | define i32 @t5(i1 %c, i32 %a) nounwind readnone { |
| 71 | entry: |
| 72 | ; ARM: t5 |
| 73 | ; ARM: cmp r0, #0 |
| 74 | ; ARM: mvneq r{{[1-9]}}, #1 |
| 75 | ; ARM: mov r0, r{{[1-9]}} |
| 76 | ; THUMB: t5 |
| 77 | ; THUMB: cmp r0, #0 |
| 78 | ; THUMB: it eq |
| 79 | ; THUMB: mvneq r{{[1-9]}}, #1 |
| 80 | ; THUMB: mov r0, r{{[1-9]}} |
| 81 | %0 = select i1 %c, i32 %a, i32 -2 |
| 82 | ret i32 %0 |
| 83 | } |
| 84 | |
| 85 | ; Check one large negative immediates. |
| 86 | define i32 @t6(i1 %c, i32 %a) nounwind readnone { |
| 87 | entry: |
| 88 | ; ARM: t6 |
| 89 | ; ARM: cmp r0, #0 |
| 90 | ; ARM: mvneq r{{[1-9]}}, #978944 |
| 91 | ; ARM: mov r0, r{{[1-9]}} |
| 92 | ; THUMB: t6 |
| 93 | ; THUMB: cmp r0, #0 |
| 94 | ; THUMB: it eq |
| 95 | ; THUMB: mvneq r{{[1-9]}}, #978944 |
| 96 | ; THUMB: mov r0, r{{[1-9]}} |
| 97 | %0 = select i1 %c, i32 %a, i32 -978945 |
| 98 | ret i32 %0 |
| 99 | } |