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gerrit-public.fairphone.software / platform / external / llvm / c23b933d5f8be9b51a1d22e717c0311f65f87dcd / . / test / Transforms / LoopUnswitch / 2011-11-18-TwoSwitches.ll
blob: 270899642ffa0616a372f8c190e45dd8c42a87aa [file] [log] [blame]
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]1; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s
2; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info %s | FileCheck %s
3
4; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted
5; STATS: 3 loop-unswitch - Number of switches unswitched
6
7; CHECK: %1 = icmp eq i32 %c, 1
8; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge
9
10; CHECK: ..split_crit_edge: ; preds = %0
11; CHECK-NEXT: br label %.split
12
13; CHECK: .split.us: ; preds = %0
14; CHECK-NEXT: %2 = icmp eq i32 %d, 1
15; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge
16
17; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us
18; CHECK-NEXT: br label %.split.us.split
19
20; CHECK: .split.us.split.us: ; preds = %.split.us
21; CHECK-NEXT: br label %loop_begin.us.us
22
23; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us
24; CHECK-NEXT: %var_val.us.us = load i32* %var
25; CHECK-NEXT: switch i32 1, label %second_switch.us.us [
26; CHECK-NEXT: i32 1, label %inc.us.us
27
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]28; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us
29; CHECK-NEXT: switch i32 1, label %default.us.us [
30; CHECK-NEXT: i32 1, label %inc.us.us
31
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]32; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us
33; CHECK-NEXT: call void @incf() noreturn nounwind
34; CHECK-NEXT: br label %loop_begin.backedge.us.us
35
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]36; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge
37; CHECK-NEXT: br label %loop_begin.us
38
39; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split
40; CHECK-NEXT: %var_val.us = load i32* %var
41; CHECK-NEXT: switch i32 1, label %second_switch.us [
42; CHECK-NEXT: i32 1, label %inc.us
43
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]44; CHECK: second_switch.us: ; preds = %loop_begin.us
45; CHECK-NEXT: switch i32 %d, label %default.us [
46; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge
47; CHECK-NEXT: ]
48
49; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us
50; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us
51
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]52; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us
53; CHECK-NEXT: call void @incf() noreturn nounwind
54; CHECK-NEXT: br label %loop_begin.backedge.us
55
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]56; CHECK: .split: ; preds = %..split_crit_edge
57; CHECK-NEXT: %3 = icmp eq i32 %d, 1
58; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge
59
60; CHECK: .split..split.split_crit_edge: ; preds = %.split
61; CHECK-NEXT: br label %.split.split
62
63; CHECK: .split.split.us: ; preds = %.split
64; CHECK-NEXT: br label %loop_begin.us1
65
66; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us
67; CHECK-NEXT: %var_val.us2 = load i32* %var
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]68; CHECK-NEXT: switch i32 %c, label %second_switch.us3 [
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]69; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us
70; CHECK-NEXT: ]
71
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]72; CHECK: second_switch.us3: ; preds = %loop_begin.us1
73; CHECK-NEXT: switch i32 1, label %default.us5 [
74; CHECK-NEXT: i32 1, label %inc.us4
75; CHECK-NEXT: ]
76
77; CHECK: inc.us4: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us3
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]78; CHECK-NEXT: call void @incf() noreturn nounwind
79; CHECK-NEXT: br label %loop_begin.backedge.us6
80
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]81; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]82; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us4
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]83
84; CHECK: .split.split: ; preds = %.split..split.split_crit_edge
85; CHECK-NEXT: br label %loop_begin
86
87; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split
88; CHECK-NEXT: %var_val = load i32* %var
89; CHECK-NEXT: switch i32 %c, label %second_switch [
90; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge
91; CHECK-NEXT: ]
92
93; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin
94; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc
95
96; CHECK: second_switch: ; preds = %loop_begin
97; CHECK-NEXT: switch i32 %d, label %default [
98; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge
99; CHECK-NEXT: ]
100
101; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch
102; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc
103
104
105define i32 @test(i32* %var) {
106 %mem = alloca i32
107 store i32 2, i32* %mem
108 %c = load i32* %mem
109 %d = load i32* %mem
110
111 br label %loop_begin
112
113loop_begin:
114
115 %var_val = load i32* %var
116
117 switch i32 %c, label %second_switch [
118 i32 1, label %inc
119 ]
120
121second_switch:
122 switch i32 %d, label %default [
123 i32 1, label %inc
124 ]
125
126inc:
127 call void @incf() noreturn nounwind
128 br label %loop_begin
129
Andrew Trickc9b1e252012-06-26 04:11:38 +0000[diff] [blame]130default:
Chad Rosierf1eba252011-12-22 21:06:36 +0000[diff] [blame]131 br label %loop_begin
132
133loop_exit:
134 ret i32 0
135}
136
137declare void @incf() noreturn
138declare void @decf() noreturn