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gerrit-public.fairphone.software / platform / external / llvm / c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 7cead8c13b71f378601c29feeea1ba1fa24920e3 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]320#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]321
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]324}
325
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]328}
329
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330EDInstInfo *ARMDisassembler::getEDInfo() const {
331 return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335 return instInfoARM;
336}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]339 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]340 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]341 raw_ostream &os,
342 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]343 CommentStream = &cs;
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint8_t bytes[4];
346
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]353 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]354 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
358 (bytes[2] << 16) |
359 (bytes[1] << 8) |
360 (bytes[0] << 0);
361
362 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]366 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 }
368
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // VFP and NEON instructions, similarly, are shared between ARM
370 // and Thumb modes.
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
378 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]380 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]381 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 Size = 4;
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 }
410
411 MI.clear();
412
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]413 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst. The immediate Value has had any PC
423/// adjustment made by the caller. If the instruction is a branch instruction
424/// then isBranch is true, else false. If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction. If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst. If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created. This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438 if (!getOpInfo)
439 return false;
440
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445 if (isBranch) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
448 if (SymbolLookUp) {
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453 &ReferenceName);
454 if (Name) {
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
458 }
459 else {
460 SymbolicOp.Value = Value;
461 }
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464 }
465 else {
466 return false;
467 }
468 }
469 else {
470 return false;
471 }
472 }
473
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481 } else {
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483 }
484 }
485
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501 const MCExpr *Expr;
502 if (Sub) {
503 const MCExpr *LHS;
504 if (Add)
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506 else
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508 if (Off != 0)
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510 else
511 Expr = LHS;
512 } else if (Add) {
513 if (Off != 0)
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515 else
516 Expr = Add;
517 } else {
518 if (Off != 0)
519 Expr = Off;
520 else
521 Expr = MCConstantExpr::Create(0, *Ctx);
522 }
523
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
530 else
531 assert("bad SymbolicOp.VariantKind");
532
533 return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction. The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry. The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol. Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549 if (SymbolLookUp) {
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558 }
559}
560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]561// Thumb1 instructions don't have explicit S bits. Rather, they
562// implicitly set CPSR. Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand. We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574 return;
575 }
576 }
577
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context. We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]587 MCDisassembler::DecodeStatus S = Success;
588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
592 case ARM::tBcc:
593 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594 case ARM::tCBZ:
595 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]596 case ARM::tCPS:
597 case ARM::t2CPS3p:
598 case ARM::t2CPS2p:
599 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]600 case ARM::tMOVSr:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]601 // Some instructions (mostly conditional branches) are not
602 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]603 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]604 S = SoftFail;
605 else
606 return Success;
607 break;
608 case ARM::tB:
609 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]610 case ARM::t2TBB:
611 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]612 // Some instructions (mostly unconditional branches) can
613 // only appears at the end of, or outside of, an IT.
614 if (ITBlock.size() > 1)
615 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]616 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]617 default:
618 break;
619 }
620
621 // If we're in an IT block, base the predicate on that. Otherwise,
622 // assume a predicate of AL.
623 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]624 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]626 if (CC == 0xF)
627 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 ITBlock.pop_back();
629 } else
630 CC = ARMCC::AL;
631
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
639 ++I;
640 if (CC == ARMCC::AL)
641 MI.insert(I, MCOperand::CreateReg(0));
642 else
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]644 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]645 }
646 }
647
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]648 I = MI.insert(I, MCOperand::CreateImm(CC));
649 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]651 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]652 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]654
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]655 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]656}
657
658// Thumb VFP instructions are a special case. Because we share their
659// encodings between ARM and Thumb modes, and they are predicable in ARM
660// mode, the auto-generated decoder will give them an (incorrect)
661// predicate operand. We need to rewrite these operands based on the IT
662// context as a post-pass.
663void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
664 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]665 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]666 CC = ITBlock.back();
667 ITBlock.pop_back();
668 } else
669 CC = ARMCC::AL;
670
671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
672 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
674 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]675 if (OpInfo[i].isPredicate() ) {
676 I->setImm(CC);
677 ++I;
678 if (CC == ARMCC::AL)
679 I->setReg(0);
680 else
681 I->setReg(ARM::CPSR);
682 return;
683 }
684 }
685}
686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]687DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]688 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]689 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]690 raw_ostream &os,
691 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]692 CommentStream = &cs;
693
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]694 uint8_t bytes[4];
695
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]696 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
697 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
698
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]699 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]700 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
701 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]702 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]703 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704
705 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]706 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]707 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]709 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]710 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]711 }
712
713 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]714 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]715 if (result) {
716 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]717 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]719 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]720 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 }
722
723 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]724 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]725 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]726 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]727
728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
729 // the Thumb predicate.
730 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
731 result = MCDisassembler::SoftFail;
732
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]733 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]734
735 // If we find an IT instruction, we need to parse its condition
736 // code and mask operands so that we can apply them correctly
737 // to the subsequent instructions.
738 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]739
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]740 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]742 unsigned Mask = MI.getOperand(1).getImm();
743 unsigned CondBit0 = Mask >> 4 & 1;
744 unsigned NumTZ = CountTrailingZeros_32(Mask);
745 assert(NumTZ <= 3 && "Invalid IT mask!");
746 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
747 bool T = ((Mask >> Pos) & 1) == CondBit0;
748 if (T)
749 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]751 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]753
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]754 ITBlock.push_back(firstcond);
755 }
756
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]757 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758 }
759
760 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]761 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
762 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]763 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]764 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]765
766 uint32_t insn32 = (bytes[3] << 8) |
767 (bytes[2] << 0) |
768 (bytes[1] << 24) |
769 (bytes[0] << 16);
770 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]771 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773 Size = 4;
774 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]775 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]777 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 }
779
780 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]781 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]784 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]785 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 }
787
788 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]789 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 Size = 4;
792 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]793 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 }
795
796 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]797 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]798 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]799 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]800 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]801 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]802 }
803
804 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
805 MI.clear();
806 uint32_t NEONLdStInsn = insn32;
807 NEONLdStInsn &= 0xF0FFFFFF;
808 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]809 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]810 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]811 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]812 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]813 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 }
815 }
816
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]817 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]818 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]819 uint32_t NEONDataInsn = insn32;
820 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
821 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
822 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]823 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]824 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]825 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]826 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]827 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 }
829 }
830
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]831 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833}
834
835
836extern "C" void LLVMInitializeARMDisassembler() {
837 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
838 createARMDisassembler);
839 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
840 createThumbDisassembler);
841}
842
843static const unsigned GPRDecoderTable[] = {
844 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
845 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
846 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
847 ARM::R12, ARM::SP, ARM::LR, ARM::PC
848};
849
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]850static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]851 uint64_t Address, const void *Decoder) {
852 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854
855 unsigned Register = GPRDecoderTable[RegNo];
856 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]857 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]858}
859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]860static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]861DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
862 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]863 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
865}
866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]867static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]868 uint64_t Address, const void *Decoder) {
869 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]870 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]871 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
872}
873
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]874static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]875 uint64_t Address, const void *Decoder) {
876 unsigned Register = 0;
877 switch (RegNo) {
878 case 0:
879 Register = ARM::R0;
880 break;
881 case 1:
882 Register = ARM::R1;
883 break;
884 case 2:
885 Register = ARM::R2;
886 break;
887 case 3:
888 Register = ARM::R3;
889 break;
890 case 9:
891 Register = ARM::R9;
892 break;
893 case 12:
894 Register = ARM::R12;
895 break;
896 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898 }
899
900 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]901 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902}
903
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]904static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]905 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]906 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]907 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
908}
909
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]910static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]911 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
912 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
913 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
914 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
915 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
916 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
917 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
918 ARM::S28, ARM::S29, ARM::S30, ARM::S31
919};
920
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]921static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922 uint64_t Address, const void *Decoder) {
923 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925
926 unsigned Register = SPRDecoderTable[RegNo];
927 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]928 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929}
930
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]931static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
933 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
934 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
935 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
936 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
937 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
938 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
939 ARM::D28, ARM::D29, ARM::D30, ARM::D31
940};
941
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]942static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943 uint64_t Address, const void *Decoder) {
944 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]945 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946
947 unsigned Register = DPRDecoderTable[RegNo];
948 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]949 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950}
951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953 uint64_t Address, const void *Decoder) {
954 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]955 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
957}
958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]959static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]960DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]962 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]963 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
965}
966
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]967static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
969 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
970 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
971 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
972};
973
974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976 uint64_t Address, const void *Decoder) {
977 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 RegNo >>= 1;
980
981 unsigned Register = QPRDecoderTable[RegNo];
982 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]983 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984}
985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]986static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]988 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]989 // AL predicate is not allowed on Thumb1 branches.
990 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]991 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 Inst.addOperand(MCOperand::CreateImm(Val));
993 if (Val == ARMCC::AL) {
994 Inst.addOperand(MCOperand::CreateReg(0));
995 } else
996 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]997 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998}
999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1000static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001 uint64_t Address, const void *Decoder) {
1002 if (Val)
1003 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1004 else
1005 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1006 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1007}
1008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1009static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1010 uint64_t Address, const void *Decoder) {
1011 uint32_t imm = Val & 0xFF;
1012 uint32_t rot = (Val & 0xF00) >> 7;
1013 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
1014 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1015 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016}
1017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1018static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1020 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1021
1022 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1023 unsigned type = fieldFromInstruction32(Val, 5, 2);
1024 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1025
1026 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1028 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1029
1030 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1031 switch (type) {
1032 case 0:
1033 Shift = ARM_AM::lsl;
1034 break;
1035 case 1:
1036 Shift = ARM_AM::lsr;
1037 break;
1038 case 2:
1039 Shift = ARM_AM::asr;
1040 break;
1041 case 3:
1042 Shift = ARM_AM::ror;
1043 break;
1044 }
1045
1046 if (Shift == ARM_AM::ror && imm == 0)
1047 Shift = ARM_AM::rrx;
1048
1049 unsigned Op = Shift | (imm << 3);
1050 Inst.addOperand(MCOperand::CreateImm(Op));
1051
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1052 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1053}
1054
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1055static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1057 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1058
1059 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1060 unsigned type = fieldFromInstruction32(Val, 5, 2);
1061 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1062
1063 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1065 return MCDisassembler::Fail;
1066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1067 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1068
1069 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1070 switch (type) {
1071 case 0:
1072 Shift = ARM_AM::lsl;
1073 break;
1074 case 1:
1075 Shift = ARM_AM::lsr;
1076 break;
1077 case 2:
1078 Shift = ARM_AM::asr;
1079 break;
1080 case 3:
1081 Shift = ARM_AM::ror;
1082 break;
1083 }
1084
1085 Inst.addOperand(MCOperand::CreateImm(Shift));
1086
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1087 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1088}
1089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1090static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1093
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1094 bool writebackLoad = false;
1095 unsigned writebackReg = 0;
1096 switch (Inst.getOpcode()) {
1097 default:
1098 break;
1099 case ARM::LDMIA_UPD:
1100 case ARM::LDMDB_UPD:
1101 case ARM::LDMIB_UPD:
1102 case ARM::LDMDA_UPD:
1103 case ARM::t2LDMIA_UPD:
1104 case ARM::t2LDMDB_UPD:
1105 writebackLoad = true;
1106 writebackReg = Inst.getOperand(0).getReg();
1107 break;
1108 }
1109
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1110 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1111 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1113 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1114 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1115 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1116 // Writeback not allowed if Rn is in the target list.
1117 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1118 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1119 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1120 }
1121
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1122 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123}
1124
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1127 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1128
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1129 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1130 unsigned regs = Val & 0xFF;
1131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1133 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1134 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1135 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1136 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1137 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1138
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1139 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1140}
1141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1142static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1143 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1144 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1145
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1146 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1147 unsigned regs = (Val & 0xFF) / 2;
1148
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1149 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1150 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1151 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1152 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1153 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1154 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1156 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1157}
1158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1159static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1160 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1161 // This operand encodes a mask of contiguous zeros between a specified MSB
1162 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1163 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1164 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1165 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1167 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1168
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1169 DecodeStatus S = MCDisassembler::Success;
1170 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1171
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1172 uint32_t msb_mask = 0xFFFFFFFF;
1173 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1174 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1175
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1176 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1177 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1178}
1179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1180static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1181 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1182 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1183
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1184 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1185 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1186 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1187 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1189 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1190
1191 switch (Inst.getOpcode()) {
1192 case ARM::LDC_OFFSET:
1193 case ARM::LDC_PRE:
1194 case ARM::LDC_POST:
1195 case ARM::LDC_OPTION:
1196 case ARM::LDCL_OFFSET:
1197 case ARM::LDCL_PRE:
1198 case ARM::LDCL_POST:
1199 case ARM::LDCL_OPTION:
1200 case ARM::STC_OFFSET:
1201 case ARM::STC_PRE:
1202 case ARM::STC_POST:
1203 case ARM::STC_OPTION:
1204 case ARM::STCL_OFFSET:
1205 case ARM::STCL_PRE:
1206 case ARM::STCL_POST:
1207 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1208 case ARM::t2LDC_OFFSET:
1209 case ARM::t2LDC_PRE:
1210 case ARM::t2LDC_POST:
1211 case ARM::t2LDC_OPTION:
1212 case ARM::t2LDCL_OFFSET:
1213 case ARM::t2LDCL_PRE:
1214 case ARM::t2LDCL_POST:
1215 case ARM::t2LDCL_OPTION:
1216 case ARM::t2STC_OFFSET:
1217 case ARM::t2STC_PRE:
1218 case ARM::t2STC_POST:
1219 case ARM::t2STC_OPTION:
1220 case ARM::t2STCL_OFFSET:
1221 case ARM::t2STCL_PRE:
1222 case ARM::t2STCL_POST:
1223 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1225 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1226 break;
1227 default:
1228 break;
1229 }
1230
1231 Inst.addOperand(MCOperand::CreateImm(coproc));
1232 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235
1236 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1237 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1238
1239 bool writeback = (P == 0) || (W == 1);
1240 unsigned idx_mode = 0;
1241 if (P && writeback)
1242 idx_mode = ARMII::IndexModePre;
1243 else if (!P && writeback)
1244 idx_mode = ARMII::IndexModePost;
1245
1246 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame^]1247 case ARM::t2LDC2_OFFSET:
1248 case ARM::t2LDC2L_OFFSET:
1249 case ARM::t2LDC2_PRE:
1250 case ARM::t2LDC2L_PRE:
1251 case ARM::t2LDC2_POST:
1252 case ARM::t2LDC2L_POST:
1253 case ARM::t2STC2_OFFSET:
1254 case ARM::t2STC2L_OFFSET:
1255 case ARM::t2STC2_PRE:
1256 case ARM::t2STC2L_PRE:
1257 case ARM::t2STC2_POST:
1258 case ARM::t2STC2L_POST:
1259 case ARM::LDC2_OFFSET:
1260 case ARM::LDC2L_OFFSET:
1261 case ARM::LDC2_PRE:
1262 case ARM::LDC2L_PRE:
1263 case ARM::LDC2_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1264 case ARM::LDC2L_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame^]1265 case ARM::STC2_OFFSET:
1266 case ARM::STC2L_OFFSET:
1267 case ARM::STC2_PRE:
1268 case ARM::STC2L_PRE:
1269 case ARM::STC2_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1270 case ARM::STC2L_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame^]1271 case ARM::t2LDC_OFFSET:
1272 case ARM::t2LDCL_OFFSET:
1273 case ARM::t2LDC_PRE:
1274 case ARM::t2LDCL_PRE:
1275 case ARM::t2LDC_POST:
1276 case ARM::t2LDCL_POST:
1277 case ARM::t2STC_OFFSET:
1278 case ARM::t2STCL_OFFSET:
1279 case ARM::t2STC_PRE:
1280 case ARM::t2STCL_PRE:
1281 case ARM::t2STC_POST:
1282 case ARM::t2STCL_POST:
1283 case ARM::LDC_OFFSET:
1284 case ARM::LDCL_OFFSET:
1285 case ARM::LDC_PRE:
1286 case ARM::LDCL_PRE:
1287 case ARM::LDC_POST:
1288 case ARM::LDCL_POST:
1289 case ARM::STC_OFFSET:
1290 case ARM::STCL_OFFSET:
1291 case ARM::STC_PRE:
1292 case ARM::STCL_PRE:
1293 case ARM::STC_POST:
1294 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame^]1296 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1297 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame^]1298 // The 'option' variant doesn't encode 'U' in the immediate since
1299 // the immediate is unsigned [0,255].
1300 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1301 break;
1302 }
1303
1304 switch (Inst.getOpcode()) {
1305 case ARM::LDC_OFFSET:
1306 case ARM::LDC_PRE:
1307 case ARM::LDC_POST:
1308 case ARM::LDC_OPTION:
1309 case ARM::LDCL_OFFSET:
1310 case ARM::LDCL_PRE:
1311 case ARM::LDCL_POST:
1312 case ARM::LDCL_OPTION:
1313 case ARM::STC_OFFSET:
1314 case ARM::STC_PRE:
1315 case ARM::STC_POST:
1316 case ARM::STC_OPTION:
1317 case ARM::STCL_OFFSET:
1318 case ARM::STCL_PRE:
1319 case ARM::STCL_POST:
1320 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1322 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1323 break;
1324 default:
1325 break;
1326 }
1327
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1328 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1329}
1330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1331static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1332DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1333 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1334 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1335
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1336 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1337 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1338 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1339 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1340 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1341 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1342 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1343 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1344
1345 // On stores, the writeback operand precedes Rt.
1346 switch (Inst.getOpcode()) {
1347 case ARM::STR_POST_IMM:
1348 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1349 case ARM::STRB_POST_IMM:
1350 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1351 case ARM::STRT_POST_REG:
1352 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1353 case ARM::STRBT_POST_REG:
1354 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1356 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1357 break;
1358 default:
1359 break;
1360 }
1361
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1363 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1364
1365 // On loads, the writeback operand comes after Rt.
1366 switch (Inst.getOpcode()) {
1367 case ARM::LDR_POST_IMM:
1368 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1369 case ARM::LDRB_POST_IMM:
1370 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1371 case ARM::LDRBT_POST_REG:
1372 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1373 case ARM::LDRT_POST_REG:
1374 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1376 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1377 break;
1378 default:
1379 break;
1380 }
1381
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1383 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1384
1385 ARM_AM::AddrOpc Op = ARM_AM::add;
1386 if (!fieldFromInstruction32(Insn, 23, 1))
1387 Op = ARM_AM::sub;
1388
1389 bool writeback = (P == 0) || (W == 1);
1390 unsigned idx_mode = 0;
1391 if (P && writeback)
1392 idx_mode = ARMII::IndexModePre;
1393 else if (!P && writeback)
1394 idx_mode = ARMII::IndexModePost;
1395
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1396 if (writeback && (Rn == 15 || Rn == Rt))
1397 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1398
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1399 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1403 switch( fieldFromInstruction32(Insn, 5, 2)) {
1404 case 0:
1405 Opc = ARM_AM::lsl;
1406 break;
1407 case 1:
1408 Opc = ARM_AM::lsr;
1409 break;
1410 case 2:
1411 Opc = ARM_AM::asr;
1412 break;
1413 case 3:
1414 Opc = ARM_AM::ror;
1415 break;
1416 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1417 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1418 }
1419 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1420 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1421
1422 Inst.addOperand(MCOperand::CreateImm(imm));
1423 } else {
1424 Inst.addOperand(MCOperand::CreateReg(0));
1425 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1426 Inst.addOperand(MCOperand::CreateImm(tmp));
1427 }
1428
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1430 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1431
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1432 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1433}
1434
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1437 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1438
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1439 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1440 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1441 unsigned type = fieldFromInstruction32(Val, 5, 2);
1442 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1443 unsigned U = fieldFromInstruction32(Val, 12, 1);
1444
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1445 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1446 switch (type) {
1447 case 0:
1448 ShOp = ARM_AM::lsl;
1449 break;
1450 case 1:
1451 ShOp = ARM_AM::lsr;
1452 break;
1453 case 2:
1454 ShOp = ARM_AM::asr;
1455 break;
1456 case 3:
1457 ShOp = ARM_AM::ror;
1458 break;
1459 }
1460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1462 return MCDisassembler::Fail;
1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1464 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1465 unsigned shift;
1466 if (U)
1467 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1468 else
1469 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1470 Inst.addOperand(MCOperand::CreateImm(shift));
1471
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1472 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1473}
1474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1475static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1476DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1477 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1478 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1479
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1480 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1481 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1482 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1483 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1484 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1485 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1486 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1487 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1488 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1489
1490 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1491
1492 // For {LD,ST}RD, Rt must be even, else undefined.
1493 switch (Inst.getOpcode()) {
1494 case ARM::STRD:
1495 case ARM::STRD_PRE:
1496 case ARM::STRD_POST:
1497 case ARM::LDRD:
1498 case ARM::LDRD_PRE:
1499 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1500 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1501 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1502 default:
1503 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1504 }
1505
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1506 if (writeback) { // Writeback
1507 if (P)
1508 U |= ARMII::IndexModePre << 9;
1509 else
1510 U |= ARMII::IndexModePost << 9;
1511
1512 // On stores, the writeback operand precedes Rt.
1513 switch (Inst.getOpcode()) {
1514 case ARM::STRD:
1515 case ARM::STRD_PRE:
1516 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1517 case ARM::STRH:
1518 case ARM::STRH_PRE:
1519 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1521 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1522 break;
1523 default:
1524 break;
1525 }
1526 }
1527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1529 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530 switch (Inst.getOpcode()) {
1531 case ARM::STRD:
1532 case ARM::STRD_PRE:
1533 case ARM::STRD_POST:
1534 case ARM::LDRD:
1535 case ARM::LDRD_PRE:
1536 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1538 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1539 break;
1540 default:
1541 break;
1542 }
1543
1544 if (writeback) {
1545 // On loads, the writeback operand comes after Rt.
1546 switch (Inst.getOpcode()) {
1547 case ARM::LDRD:
1548 case ARM::LDRD_PRE:
1549 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1550 case ARM::LDRH:
1551 case ARM::LDRH_PRE:
1552 case ARM::LDRH_POST:
1553 case ARM::LDRSH:
1554 case ARM::LDRSH_PRE:
1555 case ARM::LDRSH_POST:
1556 case ARM::LDRSB:
1557 case ARM::LDRSB_PRE:
1558 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1559 case ARM::LDRHTr:
1560 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1562 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1563 break;
1564 default:
1565 break;
1566 }
1567 }
1568
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1570 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1571
1572 if (type) {
1573 Inst.addOperand(MCOperand::CreateReg(0));
1574 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1575 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1577 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1578 Inst.addOperand(MCOperand::CreateImm(U));
1579 }
1580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1582 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585}
1586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1588 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1589 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1590
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1591 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1592 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1593
1594 switch (mode) {
1595 case 0:
1596 mode = ARM_AM::da;
1597 break;
1598 case 1:
1599 mode = ARM_AM::ia;
1600 break;
1601 case 2:
1602 mode = ARM_AM::db;
1603 break;
1604 case 3:
1605 mode = ARM_AM::ib;
1606 break;
1607 }
1608
1609 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1611 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1613 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1614}
1615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1616static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1617 unsigned Insn,
1618 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1619 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1620
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1621 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1622 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1623 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1624
1625 if (pred == 0xF) {
1626 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1627 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1628 Inst.setOpcode(ARM::RFEDA);
1629 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1630 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1631 Inst.setOpcode(ARM::RFEDA_UPD);
1632 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1633 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634 Inst.setOpcode(ARM::RFEDB);
1635 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1636 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 Inst.setOpcode(ARM::RFEDB_UPD);
1638 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1639 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 Inst.setOpcode(ARM::RFEIA);
1641 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1642 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1643 Inst.setOpcode(ARM::RFEIA_UPD);
1644 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1645 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646 Inst.setOpcode(ARM::RFEIB);
1647 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1648 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1649 Inst.setOpcode(ARM::RFEIB_UPD);
1650 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1651 case ARM::STMDA:
1652 Inst.setOpcode(ARM::SRSDA);
1653 break;
1654 case ARM::STMDA_UPD:
1655 Inst.setOpcode(ARM::SRSDA_UPD);
1656 break;
1657 case ARM::STMDB:
1658 Inst.setOpcode(ARM::SRSDB);
1659 break;
1660 case ARM::STMDB_UPD:
1661 Inst.setOpcode(ARM::SRSDB_UPD);
1662 break;
1663 case ARM::STMIA:
1664 Inst.setOpcode(ARM::SRSIA);
1665 break;
1666 case ARM::STMIA_UPD:
1667 Inst.setOpcode(ARM::SRSIA_UPD);
1668 break;
1669 case ARM::STMIB:
1670 Inst.setOpcode(ARM::SRSIB);
1671 break;
1672 case ARM::STMIB_UPD:
1673 Inst.setOpcode(ARM::SRSIB_UPD);
1674 break;
1675 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1676 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1677 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1678
1679 // For stores (which become SRS's, the only operand is the mode.
1680 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1681 Inst.addOperand(
1682 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1683 return S;
1684 }
1685
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1686 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1687 }
1688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1690 return MCDisassembler::Fail;
1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1692 return MCDisassembler::Fail; // Tied
1693 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1694 return MCDisassembler::Fail;
1695 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1696 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1697
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1698 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1699}
1700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1702 uint64_t Address, const void *Decoder) {
1703 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1704 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1705 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1706 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1708 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1709
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1710 // imod == '01' --> UNPREDICTABLE
1711 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1712 // return failure here. The '01' imod value is unprintable, so there's
1713 // nothing useful we could do even if we returned UNPREDICTABLE.
1714
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1715 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1716
1717 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718 Inst.setOpcode(ARM::CPS3p);
1719 Inst.addOperand(MCOperand::CreateImm(imod));
1720 Inst.addOperand(MCOperand::CreateImm(iflags));
1721 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1722 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723 Inst.setOpcode(ARM::CPS2p);
1724 Inst.addOperand(MCOperand::CreateImm(imod));
1725 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1726 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1727 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1728 Inst.setOpcode(ARM::CPS1p);
1729 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1730 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1731 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1732 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1733 Inst.setOpcode(ARM::CPS1p);
1734 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1735 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1736 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1737
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1738 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1739}
1740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1741static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1742 uint64_t Address, const void *Decoder) {
1743 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1744 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1745 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1746 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1747
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1748 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1749
1750 // imod == '01' --> UNPREDICTABLE
1751 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1752 // return failure here. The '01' imod value is unprintable, so there's
1753 // nothing useful we could do even if we returned UNPREDICTABLE.
1754
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1755 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1756
1757 if (imod && M) {
1758 Inst.setOpcode(ARM::t2CPS3p);
1759 Inst.addOperand(MCOperand::CreateImm(imod));
1760 Inst.addOperand(MCOperand::CreateImm(iflags));
1761 Inst.addOperand(MCOperand::CreateImm(mode));
1762 } else if (imod && !M) {
1763 Inst.setOpcode(ARM::t2CPS2p);
1764 Inst.addOperand(MCOperand::CreateImm(imod));
1765 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1766 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1767 } else if (!imod && M) {
1768 Inst.setOpcode(ARM::t2CPS1p);
1769 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1770 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1771 } else {
1772 // imod == '00' && M == '0' --> UNPREDICTABLE
1773 Inst.setOpcode(ARM::t2CPS1p);
1774 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1775 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1776 }
1777
1778 return S;
1779}
1780
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1781static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1782 uint64_t Address, const void *Decoder) {
1783 DecodeStatus S = MCDisassembler::Success;
1784
1785 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1786 unsigned imm = 0;
1787
1788 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1789 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1790 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1791 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1792
1793 if (Inst.getOpcode() == ARM::t2MOVTi16)
1794 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1795 return MCDisassembler::Fail;
1796 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1797 return MCDisassembler::Fail;
1798
1799 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1800 Inst.addOperand(MCOperand::CreateImm(imm));
1801
1802 return S;
1803}
1804
1805static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1806 uint64_t Address, const void *Decoder) {
1807 DecodeStatus S = MCDisassembler::Success;
1808
1809 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1810 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1811 unsigned imm = 0;
1812
1813 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1814 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1815
1816 if (Inst.getOpcode() == ARM::MOVTi16)
1817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1818 return MCDisassembler::Fail;
1819 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1820 return MCDisassembler::Fail;
1821
1822 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1823 Inst.addOperand(MCOperand::CreateImm(imm));
1824
1825 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1826 return MCDisassembler::Fail;
1827
1828 return S;
1829}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1830
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1831static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1833 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1834
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1836 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1837 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1838 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1839 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1840
1841 if (pred == 0xF)
1842 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1843
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1851 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1853 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1854 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1855
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1856 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1857}
1858
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1859static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1860 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1861 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1862
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1863 unsigned add = fieldFromInstruction32(Val, 12, 1);
1864 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1865 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1868 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869
1870 if (!add) imm *= -1;
1871 if (imm == 0 && !add) imm = INT32_MIN;
1872 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1873 if (Rn == 15)
1874 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1875
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1876 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1877}
1878
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1880 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1882
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1883 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1884 unsigned U = fieldFromInstruction32(Val, 8, 1);
1885 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889
1890 if (U)
1891 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1892 else
1893 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1894
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1895 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1896}
1897
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1898static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899 uint64_t Address, const void *Decoder) {
1900 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1901}
1902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1903static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1904DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1905 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1906 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1907
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1908 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1909 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1910
1911 if (pred == 0xF) {
1912 Inst.setOpcode(ARM::BLXi);
1913 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1915 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1916 }
1917
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1918 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1919 4, Inst, Decoder))
1920 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1921 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1922 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1924 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925}
1926
1927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1928static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929 uint64_t Address, const void *Decoder) {
1930 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1931 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1932}
1933
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1934static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1935 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1936 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1937
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1938 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1939 unsigned align = fieldFromInstruction32(Val, 4, 2);
1940
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1942 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1943 if (!align)
1944 Inst.addOperand(MCOperand::CreateImm(0));
1945 else
1946 Inst.addOperand(MCOperand::CreateImm(4 << align));
1947
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1948 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949}
1950
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1951static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1952 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1953 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1954
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1955 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1956 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1957 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1958 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1959 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1960 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1961
1962 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1963 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1964 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1965
1966 // Second output register
1967 switch (Inst.getOpcode()) {
1968 case ARM::VLD1q8:
1969 case ARM::VLD1q16:
1970 case ARM::VLD1q32:
1971 case ARM::VLD1q64:
1972 case ARM::VLD1q8_UPD:
1973 case ARM::VLD1q16_UPD:
1974 case ARM::VLD1q32_UPD:
1975 case ARM::VLD1q64_UPD:
1976 case ARM::VLD1d8T:
1977 case ARM::VLD1d16T:
1978 case ARM::VLD1d32T:
1979 case ARM::VLD1d64T:
1980 case ARM::VLD1d8T_UPD:
1981 case ARM::VLD1d16T_UPD:
1982 case ARM::VLD1d32T_UPD:
1983 case ARM::VLD1d64T_UPD:
1984 case ARM::VLD1d8Q:
1985 case ARM::VLD1d16Q:
1986 case ARM::VLD1d32Q:
1987 case ARM::VLD1d64Q:
1988 case ARM::VLD1d8Q_UPD:
1989 case ARM::VLD1d16Q_UPD:
1990 case ARM::VLD1d32Q_UPD:
1991 case ARM::VLD1d64Q_UPD:
1992 case ARM::VLD2d8:
1993 case ARM::VLD2d16:
1994 case ARM::VLD2d32:
1995 case ARM::VLD2d8_UPD:
1996 case ARM::VLD2d16_UPD:
1997 case ARM::VLD2d32_UPD:
1998 case ARM::VLD2q8:
1999 case ARM::VLD2q16:
2000 case ARM::VLD2q32:
2001 case ARM::VLD2q8_UPD:
2002 case ARM::VLD2q16_UPD:
2003 case ARM::VLD2q32_UPD:
2004 case ARM::VLD3d8:
2005 case ARM::VLD3d16:
2006 case ARM::VLD3d32:
2007 case ARM::VLD3d8_UPD:
2008 case ARM::VLD3d16_UPD:
2009 case ARM::VLD3d32_UPD:
2010 case ARM::VLD4d8:
2011 case ARM::VLD4d16:
2012 case ARM::VLD4d32:
2013 case ARM::VLD4d8_UPD:
2014 case ARM::VLD4d16_UPD:
2015 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2016 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2017 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2018 break;
2019 case ARM::VLD2b8:
2020 case ARM::VLD2b16:
2021 case ARM::VLD2b32:
2022 case ARM::VLD2b8_UPD:
2023 case ARM::VLD2b16_UPD:
2024 case ARM::VLD2b32_UPD:
2025 case ARM::VLD3q8:
2026 case ARM::VLD3q16:
2027 case ARM::VLD3q32:
2028 case ARM::VLD3q8_UPD:
2029 case ARM::VLD3q16_UPD:
2030 case ARM::VLD3q32_UPD:
2031 case ARM::VLD4q8:
2032 case ARM::VLD4q16:
2033 case ARM::VLD4q32:
2034 case ARM::VLD4q8_UPD:
2035 case ARM::VLD4q16_UPD:
2036 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2037 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2038 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2039 default:
2040 break;
2041 }
2042
2043 // Third output register
2044 switch(Inst.getOpcode()) {
2045 case ARM::VLD1d8T:
2046 case ARM::VLD1d16T:
2047 case ARM::VLD1d32T:
2048 case ARM::VLD1d64T:
2049 case ARM::VLD1d8T_UPD:
2050 case ARM::VLD1d16T_UPD:
2051 case ARM::VLD1d32T_UPD:
2052 case ARM::VLD1d64T_UPD:
2053 case ARM::VLD1d8Q:
2054 case ARM::VLD1d16Q:
2055 case ARM::VLD1d32Q:
2056 case ARM::VLD1d64Q:
2057 case ARM::VLD1d8Q_UPD:
2058 case ARM::VLD1d16Q_UPD:
2059 case ARM::VLD1d32Q_UPD:
2060 case ARM::VLD1d64Q_UPD:
2061 case ARM::VLD2q8:
2062 case ARM::VLD2q16:
2063 case ARM::VLD2q32:
2064 case ARM::VLD2q8_UPD:
2065 case ARM::VLD2q16_UPD:
2066 case ARM::VLD2q32_UPD:
2067 case ARM::VLD3d8:
2068 case ARM::VLD3d16:
2069 case ARM::VLD3d32:
2070 case ARM::VLD3d8_UPD:
2071 case ARM::VLD3d16_UPD:
2072 case ARM::VLD3d32_UPD:
2073 case ARM::VLD4d8:
2074 case ARM::VLD4d16:
2075 case ARM::VLD4d32:
2076 case ARM::VLD4d8_UPD:
2077 case ARM::VLD4d16_UPD:
2078 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2079 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2080 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2081 break;
2082 case ARM::VLD3q8:
2083 case ARM::VLD3q16:
2084 case ARM::VLD3q32:
2085 case ARM::VLD3q8_UPD:
2086 case ARM::VLD3q16_UPD:
2087 case ARM::VLD3q32_UPD:
2088 case ARM::VLD4q8:
2089 case ARM::VLD4q16:
2090 case ARM::VLD4q32:
2091 case ARM::VLD4q8_UPD:
2092 case ARM::VLD4q16_UPD:
2093 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2094 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2095 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2096 break;
2097 default:
2098 break;
2099 }
2100
2101 // Fourth output register
2102 switch (Inst.getOpcode()) {
2103 case ARM::VLD1d8Q:
2104 case ARM::VLD1d16Q:
2105 case ARM::VLD1d32Q:
2106 case ARM::VLD1d64Q:
2107 case ARM::VLD1d8Q_UPD:
2108 case ARM::VLD1d16Q_UPD:
2109 case ARM::VLD1d32Q_UPD:
2110 case ARM::VLD1d64Q_UPD:
2111 case ARM::VLD2q8:
2112 case ARM::VLD2q16:
2113 case ARM::VLD2q32:
2114 case ARM::VLD2q8_UPD:
2115 case ARM::VLD2q16_UPD:
2116 case ARM::VLD2q32_UPD:
2117 case ARM::VLD4d8:
2118 case ARM::VLD4d16:
2119 case ARM::VLD4d32:
2120 case ARM::VLD4d8_UPD:
2121 case ARM::VLD4d16_UPD:
2122 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2123 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2124 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2125 break;
2126 case ARM::VLD4q8:
2127 case ARM::VLD4q16:
2128 case ARM::VLD4q32:
2129 case ARM::VLD4q8_UPD:
2130 case ARM::VLD4q16_UPD:
2131 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2133 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134 break;
2135 default:
2136 break;
2137 }
2138
2139 // Writeback operand
2140 switch (Inst.getOpcode()) {
2141 case ARM::VLD1d8_UPD:
2142 case ARM::VLD1d16_UPD:
2143 case ARM::VLD1d32_UPD:
2144 case ARM::VLD1d64_UPD:
2145 case ARM::VLD1q8_UPD:
2146 case ARM::VLD1q16_UPD:
2147 case ARM::VLD1q32_UPD:
2148 case ARM::VLD1q64_UPD:
2149 case ARM::VLD1d8T_UPD:
2150 case ARM::VLD1d16T_UPD:
2151 case ARM::VLD1d32T_UPD:
2152 case ARM::VLD1d64T_UPD:
2153 case ARM::VLD1d8Q_UPD:
2154 case ARM::VLD1d16Q_UPD:
2155 case ARM::VLD1d32Q_UPD:
2156 case ARM::VLD1d64Q_UPD:
2157 case ARM::VLD2d8_UPD:
2158 case ARM::VLD2d16_UPD:
2159 case ARM::VLD2d32_UPD:
2160 case ARM::VLD2q8_UPD:
2161 case ARM::VLD2q16_UPD:
2162 case ARM::VLD2q32_UPD:
2163 case ARM::VLD2b8_UPD:
2164 case ARM::VLD2b16_UPD:
2165 case ARM::VLD2b32_UPD:
2166 case ARM::VLD3d8_UPD:
2167 case ARM::VLD3d16_UPD:
2168 case ARM::VLD3d32_UPD:
2169 case ARM::VLD3q8_UPD:
2170 case ARM::VLD3q16_UPD:
2171 case ARM::VLD3q32_UPD:
2172 case ARM::VLD4d8_UPD:
2173 case ARM::VLD4d16_UPD:
2174 case ARM::VLD4d32_UPD:
2175 case ARM::VLD4q8_UPD:
2176 case ARM::VLD4q16_UPD:
2177 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2178 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2179 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2180 break;
2181 default:
2182 break;
2183 }
2184
2185 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2186 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2187 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2188
2189 // AddrMode6 Offset (register)
2190 if (Rm == 0xD)
2191 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2192 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2194 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2195 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2196
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2197 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2198}
2199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2200static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2201 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2202 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2203
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2204 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2205 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2206 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2207 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2208 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2209 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2210
2211 // Writeback Operand
2212 switch (Inst.getOpcode()) {
2213 case ARM::VST1d8_UPD:
2214 case ARM::VST1d16_UPD:
2215 case ARM::VST1d32_UPD:
2216 case ARM::VST1d64_UPD:
2217 case ARM::VST1q8_UPD:
2218 case ARM::VST1q16_UPD:
2219 case ARM::VST1q32_UPD:
2220 case ARM::VST1q64_UPD:
2221 case ARM::VST1d8T_UPD:
2222 case ARM::VST1d16T_UPD:
2223 case ARM::VST1d32T_UPD:
2224 case ARM::VST1d64T_UPD:
2225 case ARM::VST1d8Q_UPD:
2226 case ARM::VST1d16Q_UPD:
2227 case ARM::VST1d32Q_UPD:
2228 case ARM::VST1d64Q_UPD:
2229 case ARM::VST2d8_UPD:
2230 case ARM::VST2d16_UPD:
2231 case ARM::VST2d32_UPD:
2232 case ARM::VST2q8_UPD:
2233 case ARM::VST2q16_UPD:
2234 case ARM::VST2q32_UPD:
2235 case ARM::VST2b8_UPD:
2236 case ARM::VST2b16_UPD:
2237 case ARM::VST2b32_UPD:
2238 case ARM::VST3d8_UPD:
2239 case ARM::VST3d16_UPD:
2240 case ARM::VST3d32_UPD:
2241 case ARM::VST3q8_UPD:
2242 case ARM::VST3q16_UPD:
2243 case ARM::VST3q32_UPD:
2244 case ARM::VST4d8_UPD:
2245 case ARM::VST4d16_UPD:
2246 case ARM::VST4d32_UPD:
2247 case ARM::VST4q8_UPD:
2248 case ARM::VST4q16_UPD:
2249 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2250 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2251 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2252 break;
2253 default:
2254 break;
2255 }
2256
2257 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2258 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2259 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2260
2261 // AddrMode6 Offset (register)
2262 if (Rm == 0xD)
2263 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2264 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2266 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2267 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2268
2269 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2271 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2272
2273 // Second input register
2274 switch (Inst.getOpcode()) {
2275 case ARM::VST1q8:
2276 case ARM::VST1q16:
2277 case ARM::VST1q32:
2278 case ARM::VST1q64:
2279 case ARM::VST1q8_UPD:
2280 case ARM::VST1q16_UPD:
2281 case ARM::VST1q32_UPD:
2282 case ARM::VST1q64_UPD:
2283 case ARM::VST1d8T:
2284 case ARM::VST1d16T:
2285 case ARM::VST1d32T:
2286 case ARM::VST1d64T:
2287 case ARM::VST1d8T_UPD:
2288 case ARM::VST1d16T_UPD:
2289 case ARM::VST1d32T_UPD:
2290 case ARM::VST1d64T_UPD:
2291 case ARM::VST1d8Q:
2292 case ARM::VST1d16Q:
2293 case ARM::VST1d32Q:
2294 case ARM::VST1d64Q:
2295 case ARM::VST1d8Q_UPD:
2296 case ARM::VST1d16Q_UPD:
2297 case ARM::VST1d32Q_UPD:
2298 case ARM::VST1d64Q_UPD:
2299 case ARM::VST2d8:
2300 case ARM::VST2d16:
2301 case ARM::VST2d32:
2302 case ARM::VST2d8_UPD:
2303 case ARM::VST2d16_UPD:
2304 case ARM::VST2d32_UPD:
2305 case ARM::VST2q8:
2306 case ARM::VST2q16:
2307 case ARM::VST2q32:
2308 case ARM::VST2q8_UPD:
2309 case ARM::VST2q16_UPD:
2310 case ARM::VST2q32_UPD:
2311 case ARM::VST3d8:
2312 case ARM::VST3d16:
2313 case ARM::VST3d32:
2314 case ARM::VST3d8_UPD:
2315 case ARM::VST3d16_UPD:
2316 case ARM::VST3d32_UPD:
2317 case ARM::VST4d8:
2318 case ARM::VST4d16:
2319 case ARM::VST4d32:
2320 case ARM::VST4d8_UPD:
2321 case ARM::VST4d16_UPD:
2322 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2323 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2324 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2325 break;
2326 case ARM::VST2b8:
2327 case ARM::VST2b16:
2328 case ARM::VST2b32:
2329 case ARM::VST2b8_UPD:
2330 case ARM::VST2b16_UPD:
2331 case ARM::VST2b32_UPD:
2332 case ARM::VST3q8:
2333 case ARM::VST3q16:
2334 case ARM::VST3q32:
2335 case ARM::VST3q8_UPD:
2336 case ARM::VST3q16_UPD:
2337 case ARM::VST3q32_UPD:
2338 case ARM::VST4q8:
2339 case ARM::VST4q16:
2340 case ARM::VST4q32:
2341 case ARM::VST4q8_UPD:
2342 case ARM::VST4q16_UPD:
2343 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2344 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2345 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346 break;
2347 default:
2348 break;
2349 }
2350
2351 // Third input register
2352 switch (Inst.getOpcode()) {
2353 case ARM::VST1d8T:
2354 case ARM::VST1d16T:
2355 case ARM::VST1d32T:
2356 case ARM::VST1d64T:
2357 case ARM::VST1d8T_UPD:
2358 case ARM::VST1d16T_UPD:
2359 case ARM::VST1d32T_UPD:
2360 case ARM::VST1d64T_UPD:
2361 case ARM::VST1d8Q:
2362 case ARM::VST1d16Q:
2363 case ARM::VST1d32Q:
2364 case ARM::VST1d64Q:
2365 case ARM::VST1d8Q_UPD:
2366 case ARM::VST1d16Q_UPD:
2367 case ARM::VST1d32Q_UPD:
2368 case ARM::VST1d64Q_UPD:
2369 case ARM::VST2q8:
2370 case ARM::VST2q16:
2371 case ARM::VST2q32:
2372 case ARM::VST2q8_UPD:
2373 case ARM::VST2q16_UPD:
2374 case ARM::VST2q32_UPD:
2375 case ARM::VST3d8:
2376 case ARM::VST3d16:
2377 case ARM::VST3d32:
2378 case ARM::VST3d8_UPD:
2379 case ARM::VST3d16_UPD:
2380 case ARM::VST3d32_UPD:
2381 case ARM::VST4d8:
2382 case ARM::VST4d16:
2383 case ARM::VST4d32:
2384 case ARM::VST4d8_UPD:
2385 case ARM::VST4d16_UPD:
2386 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2388 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2389 break;
2390 case ARM::VST3q8:
2391 case ARM::VST3q16:
2392 case ARM::VST3q32:
2393 case ARM::VST3q8_UPD:
2394 case ARM::VST3q16_UPD:
2395 case ARM::VST3q32_UPD:
2396 case ARM::VST4q8:
2397 case ARM::VST4q16:
2398 case ARM::VST4q32:
2399 case ARM::VST4q8_UPD:
2400 case ARM::VST4q16_UPD:
2401 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2402 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2403 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2404 break;
2405 default:
2406 break;
2407 }
2408
2409 // Fourth input register
2410 switch (Inst.getOpcode()) {
2411 case ARM::VST1d8Q:
2412 case ARM::VST1d16Q:
2413 case ARM::VST1d32Q:
2414 case ARM::VST1d64Q:
2415 case ARM::VST1d8Q_UPD:
2416 case ARM::VST1d16Q_UPD:
2417 case ARM::VST1d32Q_UPD:
2418 case ARM::VST1d64Q_UPD:
2419 case ARM::VST2q8:
2420 case ARM::VST2q16:
2421 case ARM::VST2q32:
2422 case ARM::VST2q8_UPD:
2423 case ARM::VST2q16_UPD:
2424 case ARM::VST2q32_UPD:
2425 case ARM::VST4d8:
2426 case ARM::VST4d16:
2427 case ARM::VST4d32:
2428 case ARM::VST4d8_UPD:
2429 case ARM::VST4d16_UPD:
2430 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2431 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2432 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2433 break;
2434 case ARM::VST4q8:
2435 case ARM::VST4q16:
2436 case ARM::VST4q32:
2437 case ARM::VST4q8_UPD:
2438 case ARM::VST4q16_UPD:
2439 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2440 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2441 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442 break;
2443 default:
2444 break;
2445 }
2446
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2447 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2448}
2449
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2450static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2451 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2452 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2453
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2454 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2455 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2456 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2457 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2458 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2459 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2460 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2461
2462 align *= (1 << size);
2463
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2464 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2465 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2466 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2467 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2468 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2469 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2470 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2472 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2473 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2476 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477 Inst.addOperand(MCOperand::CreateImm(align));
2478
2479 if (Rm == 0xD)
2480 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2481 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2483 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2484 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2486 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2487}
2488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2489static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2491 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2492
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2494 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2495 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2496 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2497 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2498 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2499 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2500 align *= 2*size;
2501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2503 return MCDisassembler::Fail;
2504 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2505 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2506 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2508 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2509 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2510
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2512 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513 Inst.addOperand(MCOperand::CreateImm(align));
2514
2515 if (Rm == 0xD)
2516 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2517 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2519 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2520 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2522 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2523}
2524
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2525static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2526 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2527 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2528
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2530 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2532 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2533 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2534
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2536 return MCDisassembler::Fail;
2537 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2538 return MCDisassembler::Fail;
2539 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2540 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2541 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2543 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2544 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2547 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548 Inst.addOperand(MCOperand::CreateImm(0));
2549
2550 if (Rm == 0xD)
2551 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2552 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2554 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2555 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2557 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558}
2559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2560static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2562 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2563
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2564 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2565 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2566 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2567 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2568 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2569 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2570 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2571
2572 if (size == 0x3) {
2573 size = 4;
2574 align = 16;
2575 } else {
2576 if (size == 2) {
2577 size = 1 << size;
2578 align *= 8;
2579 } else {
2580 size = 1 << size;
2581 align *= 4*size;
2582 }
2583 }
2584
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2586 return MCDisassembler::Fail;
2587 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2588 return MCDisassembler::Fail;
2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2590 return MCDisassembler::Fail;
2591 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2592 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2593 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2595 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2596 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2597
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2599 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2600 Inst.addOperand(MCOperand::CreateImm(align));
2601
2602 if (Rm == 0xD)
2603 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2604 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2606 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2607 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2609 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2610}
2611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2612static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2613DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2614 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2615 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2616
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2617 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2618 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2619 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2620 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2621 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2622 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2623 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2624 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2625
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2626 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2627 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2628 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2629 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2631 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2632 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2633
2634 Inst.addOperand(MCOperand::CreateImm(imm));
2635
2636 switch (Inst.getOpcode()) {
2637 case ARM::VORRiv4i16:
2638 case ARM::VORRiv2i32:
2639 case ARM::VBICiv4i16:
2640 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2642 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643 break;
2644 case ARM::VORRiv8i16:
2645 case ARM::VORRiv4i32:
2646 case ARM::VBICiv8i16:
2647 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2648 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2649 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650 break;
2651 default:
2652 break;
2653 }
2654
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2655 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2656}
2657
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2658static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2659 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2660 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2661
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2662 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2663 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2664 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2665 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2666 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2667
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2668 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2669 return MCDisassembler::Fail;
2670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2671 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672 Inst.addOperand(MCOperand::CreateImm(8 << size));
2673
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2674 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2675}
2676
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2677static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678 uint64_t Address, const void *Decoder) {
2679 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2680 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681}
2682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2683static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 uint64_t Address, const void *Decoder) {
2685 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2686 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687}
2688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2689static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690 uint64_t Address, const void *Decoder) {
2691 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2692 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693}
2694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2695static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696 uint64_t Address, const void *Decoder) {
2697 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2698 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2699}
2700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2701static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2703 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2704
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2706 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2707 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2708 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2709 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2710 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2711 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2712 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2715 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2716 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2718 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2719 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2721 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2722 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2723 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2724 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2725
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2726 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2727 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2728
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2729 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2730}
2731
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2733 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2734 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2735
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2736 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2737 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2739 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2740 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2741
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2742 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2743 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2744 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2745 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2746 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2747 case ARM::tADDrSPi:
2748 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2749 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2750 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751
2752 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2753 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754}
2755
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2756static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757 uint64_t Address, const void *Decoder) {
2758 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2759 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760}
2761
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2762static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763 uint64_t Address, const void *Decoder) {
2764 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2765 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2766}
2767
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2768static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769 uint64_t Address, const void *Decoder) {
2770 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2771 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2772}
2773
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2774static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2775 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2776 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2777
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2778 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2779 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2780
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2781 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2784 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2786 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2787}
2788
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2789static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2791 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2792
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2793 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2794 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2795
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2796 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2797 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798 Inst.addOperand(MCOperand::CreateImm(imm));
2799
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2800 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2801}
2802
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2803static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2805 unsigned imm = Val << 2;
2806
2807 Inst.addOperand(MCOperand::CreateImm(imm));
2808 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2810 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2811}
2812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814 uint64_t Address, const void *Decoder) {
2815 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2816 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2818 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2819}
2820
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2821static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2822 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2824
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2826 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2827 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2830 return MCDisassembler::Fail;
2831 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2832 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2833 Inst.addOperand(MCOperand::CreateImm(imm));
2834
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2835 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2836}
2837
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2838static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2839 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2840 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2841
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2842 switch (Inst.getOpcode()) {
2843 case ARM::t2PLDs:
2844 case ARM::t2PLDWs:
2845 case ARM::t2PLIs:
2846 break;
2847 default: {
2848 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2849 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2850 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2851 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2852 }
2853
2854 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2855 if (Rn == 0xF) {
2856 switch (Inst.getOpcode()) {
2857 case ARM::t2LDRBs:
2858 Inst.setOpcode(ARM::t2LDRBpci);
2859 break;
2860 case ARM::t2LDRHs:
2861 Inst.setOpcode(ARM::t2LDRHpci);
2862 break;
2863 case ARM::t2LDRSHs:
2864 Inst.setOpcode(ARM::t2LDRSHpci);
2865 break;
2866 case ARM::t2LDRSBs:
2867 Inst.setOpcode(ARM::t2LDRSBpci);
2868 break;
2869 case ARM::t2PLDs:
2870 Inst.setOpcode(ARM::t2PLDi12);
2871 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2872 break;
2873 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2874 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2875 }
2876
2877 int imm = fieldFromInstruction32(Insn, 0, 12);
2878 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2879 Inst.addOperand(MCOperand::CreateImm(imm));
2880
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2881 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2882 }
2883
2884 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2885 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2886 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2887 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2890 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2891}
2892
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2893static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2894 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2895 int imm = Val & 0xFF;
2896 if (!(Val & 0x100)) imm *= -1;
2897 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2898
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2899 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900}
2901
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2902static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2905
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2906 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2907 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2908
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2910 return MCDisassembler::Fail;
2911 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2912 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2914 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2915}
2916
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2917static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2918 uint64_t Address, const void *Decoder) {
2919 DecodeStatus S = MCDisassembler::Success;
2920
2921 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2922 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2923
2924 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2925 return MCDisassembler::Fail;
2926
2927 Inst.addOperand(MCOperand::CreateImm(imm));
2928
2929 return S;
2930}
2931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2932static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2933 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2935 if (Val == 0)
2936 imm = INT32_MIN;
2937 else if (!(Val & 0x100))
2938 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939 Inst.addOperand(MCOperand::CreateImm(imm));
2940
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2941 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942}
2943
2944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2945static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2948
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2949 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2950 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2951
2952 // Some instructions always use an additive offset.
2953 switch (Inst.getOpcode()) {
2954 case ARM::t2LDRT:
2955 case ARM::t2LDRBT:
2956 case ARM::t2LDRHT:
2957 case ARM::t2LDRSBT:
2958 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2959 case ARM::t2STRT:
2960 case ARM::t2STRBT:
2961 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2962 imm |= 0x100;
2963 break;
2964 default:
2965 break;
2966 }
2967
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2969 return MCDisassembler::Fail;
2970 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2971 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2972
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2973 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974}
2975
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2976static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2977 uint64_t Address, const void *Decoder) {
2978 DecodeStatus S = MCDisassembler::Success;
2979
2980 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2981 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2982 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2983 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2984 addr |= Rn << 9;
2985 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2986
2987 if (!load) {
2988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2989 return MCDisassembler::Fail;
2990 }
2991
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2993 return MCDisassembler::Fail;
2994
2995 if (load) {
2996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2997 return MCDisassembler::Fail;
2998 }
2999
3000 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3001 return MCDisassembler::Fail;
3002
3003 return S;
3004}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3005
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3007 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3008 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3009
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3011 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3012
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3014 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3015 Inst.addOperand(MCOperand::CreateImm(imm));
3016
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3017 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018}
3019
3020
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3021static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3022 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3023 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3024
3025 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3026 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3027 Inst.addOperand(MCOperand::CreateImm(imm));
3028
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3029 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3030}
3031
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3032static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3033 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3034 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3035
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3036 if (Inst.getOpcode() == ARM::tADDrSP) {
3037 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3038 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3039
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3041 return MCDisassembler::Fail;
3042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3043 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3044 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3045 } else if (Inst.getOpcode() == ARM::tADDspr) {
3046 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3047
3048 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3049 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3051 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3052 }
3053
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3054 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3055}
3056
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3057static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3058 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3059 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3060 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3061
3062 Inst.addOperand(MCOperand::CreateImm(imod));
3063 Inst.addOperand(MCOperand::CreateImm(flags));
3064
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3065 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066}
3067
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3068static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3069 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3070 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3071 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3072 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3073
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3075 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3076 Inst.addOperand(MCOperand::CreateImm(add));
3077
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3078 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079}
3080
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3081static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3082 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3083 if (!tryAddingSymbolicOperand(Address,
3084 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3085 true, 4, Inst, Decoder))
3086 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3087 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3088}
3089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3090static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091 uint64_t Address, const void *Decoder) {
3092 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3093 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3094
3095 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3096 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3097}
3098
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3099static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3100DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3101 uint64_t Address, const void *Decoder) {
3102 DecodeStatus S = MCDisassembler::Success;
3103
3104 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3105 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3106
3107 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3109 return MCDisassembler::Fail;
3110 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3111 return MCDisassembler::Fail;
3112 return S;
3113}
3114
3115static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3116DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3119
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3120 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3121 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3122 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3123 switch (opc) {
3124 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3125 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3126 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3127 Inst.setOpcode(ARM::t2DSB);
3128 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3129 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 Inst.setOpcode(ARM::t2DMB);
3131 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3132 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3133 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3134 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3135 }
3136
3137 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3138 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3139 }
3140
3141 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3142 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3143 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3144 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3145 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3146
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3147 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3148 return MCDisassembler::Fail;
3149 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3150 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3151
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3152 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3153}
3154
3155// Decode a shifted immediate operand. These basically consist
3156// of an 8-bit value, and a 4-bit directive that specifies either
3157// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3158static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3159 uint64_t Address, const void *Decoder) {
3160 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3161 if (ctrl == 0) {
3162 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3163 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3164 switch (byte) {
3165 case 0:
3166 Inst.addOperand(MCOperand::CreateImm(imm));
3167 break;
3168 case 1:
3169 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3170 break;
3171 case 2:
3172 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3173 break;
3174 case 3:
3175 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3176 (imm << 8) | imm));
3177 break;
3178 }
3179 } else {
3180 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3181 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3182 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3183 Inst.addOperand(MCOperand::CreateImm(imm));
3184 }
3185
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3186 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3187}
3188
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3189static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3190DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3191 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3192 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3193 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3194}
3195
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3196static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3197 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3198 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3199 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3200}
3201
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3202static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3203 uint64_t Address, const void *Decoder) {
3204 switch (Val) {
3205 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3206 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3207 case 0xF: // SY
3208 case 0xE: // ST
3209 case 0xB: // ISH
3210 case 0xA: // ISHST
3211 case 0x7: // NSH
3212 case 0x6: // NSHST
3213 case 0x3: // OSH
3214 case 0x2: // OSHST
3215 break;
3216 }
3217
3218 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3219 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3220}
3221
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3222static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3223 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3224 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3225 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3226 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3227}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3228
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3229static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3230 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3231 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3232
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3233 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3234 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3235 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3236
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3237 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3238
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3240 return MCDisassembler::Fail;
3241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3242 return MCDisassembler::Fail;
3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3244 return MCDisassembler::Fail;
3245 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3246 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3247
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3248 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3249}
3250
3251
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3252static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3253 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3254 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3255
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3256 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3257 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3258 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3259 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3260
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3261 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3262 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3263
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3264 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3265 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3266
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3268 return MCDisassembler::Fail;
3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3270 return MCDisassembler::Fail;
3271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3272 return MCDisassembler::Fail;
3273 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3274 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3275
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3276 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3277}
3278
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3279static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3280 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3281 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3282
3283 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3284 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3285 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3286 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3287 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3288 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3289
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3290 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3291
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3293 return MCDisassembler::Fail;
3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3295 return MCDisassembler::Fail;
3296 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3297 return MCDisassembler::Fail;
3298 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3299 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3300
3301 return S;
3302}
3303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3304static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3305 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3306 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3307
3308 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3309 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3310 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3311 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3312 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3313 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3314 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3315
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3316 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3317 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3318
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3320 return MCDisassembler::Fail;
3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3322 return MCDisassembler::Fail;
3323 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3324 return MCDisassembler::Fail;
3325 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3326 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3327
3328 return S;
3329}
3330
3331
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3332static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3333 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3334 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3335
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3336 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3337 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3338 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3339 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3340 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3341 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3342
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3343 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3344
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3346 return MCDisassembler::Fail;
3347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3348 return MCDisassembler::Fail;
3349 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3350 return MCDisassembler::Fail;
3351 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3352 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3353
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3354 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3355}
3356
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3357static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3358 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3359 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3360
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3362 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3363 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3364 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3365 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3366 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3367
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3368 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3371 return MCDisassembler::Fail;
3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3373 return MCDisassembler::Fail;
3374 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3375 return MCDisassembler::Fail;
3376 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3377 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3378
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3379 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3380}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3381
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3382static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3383 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3384 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3385
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3386 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3387 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3388 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3389 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3390 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3391
3392 unsigned align = 0;
3393 unsigned index = 0;
3394 switch (size) {
3395 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3396 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3397 case 0:
3398 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3400 index = fieldFromInstruction32(Insn, 5, 3);
3401 break;
3402 case 1:
3403 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3404 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3405 index = fieldFromInstruction32(Insn, 6, 2);
3406 if (fieldFromInstruction32(Insn, 4, 1))
3407 align = 2;
3408 break;
3409 case 2:
3410 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3411 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3412 index = fieldFromInstruction32(Insn, 7, 1);
3413 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3414 align = 4;
3415 }
3416
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3417 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3418 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3419 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3421 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3422 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3424 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3425 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3426 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3427 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3429 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3430 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3431 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3432 }
3433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3435 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3436 Inst.addOperand(MCOperand::CreateImm(index));
3437
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3438 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3439}
3440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3441static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3442 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3443 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3444
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3445 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3446 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3447 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3448 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3449 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3450
3451 unsigned align = 0;
3452 unsigned index = 0;
3453 switch (size) {
3454 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3455 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3456 case 0:
3457 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3458 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3459 index = fieldFromInstruction32(Insn, 5, 3);
3460 break;
3461 case 1:
3462 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3463 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3464 index = fieldFromInstruction32(Insn, 6, 2);
3465 if (fieldFromInstruction32(Insn, 4, 1))
3466 align = 2;
3467 break;
3468 case 2:
3469 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3470 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3471 index = fieldFromInstruction32(Insn, 7, 1);
3472 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3473 align = 4;
3474 }
3475
3476 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3478 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3479 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3481 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3482 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3483 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3484 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3486 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3487 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3488 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3489 }
3490
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3492 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3493 Inst.addOperand(MCOperand::CreateImm(index));
3494
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3495 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3496}
3497
3498
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3499static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3500 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3501 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3502
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3503 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3504 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3505 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3506 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3507 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3508
3509 unsigned align = 0;
3510 unsigned index = 0;
3511 unsigned inc = 1;
3512 switch (size) {
3513 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3514 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3515 case 0:
3516 index = fieldFromInstruction32(Insn, 5, 3);
3517 if (fieldFromInstruction32(Insn, 4, 1))
3518 align = 2;
3519 break;
3520 case 1:
3521 index = fieldFromInstruction32(Insn, 6, 2);
3522 if (fieldFromInstruction32(Insn, 4, 1))
3523 align = 4;
3524 if (fieldFromInstruction32(Insn, 5, 1))
3525 inc = 2;
3526 break;
3527 case 2:
3528 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3529 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3530 index = fieldFromInstruction32(Insn, 7, 1);
3531 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3532 align = 8;
3533 if (fieldFromInstruction32(Insn, 6, 1))
3534 inc = 2;
3535 break;
3536 }
3537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3539 return MCDisassembler::Fail;
3540 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3541 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3542 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3544 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3545 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3547 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3548 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3549 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3550 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3552 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3553 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3554 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3555 }
3556
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3557 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3558 return MCDisassembler::Fail;
3559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3560 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3561 Inst.addOperand(MCOperand::CreateImm(index));
3562
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3563 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3564}
3565
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3566static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3567 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3568 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3569
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3570 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3571 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3572 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3573 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3574 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3575
3576 unsigned align = 0;
3577 unsigned index = 0;
3578 unsigned inc = 1;
3579 switch (size) {
3580 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3581 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3582 case 0:
3583 index = fieldFromInstruction32(Insn, 5, 3);
3584 if (fieldFromInstruction32(Insn, 4, 1))
3585 align = 2;
3586 break;
3587 case 1:
3588 index = fieldFromInstruction32(Insn, 6, 2);
3589 if (fieldFromInstruction32(Insn, 4, 1))
3590 align = 4;
3591 if (fieldFromInstruction32(Insn, 5, 1))
3592 inc = 2;
3593 break;
3594 case 2:
3595 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3596 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3597 index = fieldFromInstruction32(Insn, 7, 1);
3598 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3599 align = 8;
3600 if (fieldFromInstruction32(Insn, 6, 1))
3601 inc = 2;
3602 break;
3603 }
3604
3605 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3607 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3608 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3610 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3611 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3612 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3613 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3615 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3616 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3617 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3618 }
3619
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3620 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3621 return MCDisassembler::Fail;
3622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3623 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3624 Inst.addOperand(MCOperand::CreateImm(index));
3625
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3626 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3627}
3628
3629
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3630static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3631 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3632 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3633
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3634 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3635 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3636 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3637 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3638 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3639
3640 unsigned align = 0;
3641 unsigned index = 0;
3642 unsigned inc = 1;
3643 switch (size) {
3644 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3645 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3646 case 0:
3647 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3648 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3649 index = fieldFromInstruction32(Insn, 5, 3);
3650 break;
3651 case 1:
3652 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3653 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3654 index = fieldFromInstruction32(Insn, 6, 2);
3655 if (fieldFromInstruction32(Insn, 5, 1))
3656 inc = 2;
3657 break;
3658 case 2:
3659 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3660 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3661 index = fieldFromInstruction32(Insn, 7, 1);
3662 if (fieldFromInstruction32(Insn, 6, 1))
3663 inc = 2;
3664 break;
3665 }
3666
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3670 return MCDisassembler::Fail;
3671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3672 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3673
3674 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3676 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3677 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3679 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3680 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3681 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3682 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3684 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3685 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3686 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3687 }
3688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3690 return MCDisassembler::Fail;
3691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3692 return MCDisassembler::Fail;
3693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3694 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3695 Inst.addOperand(MCOperand::CreateImm(index));
3696
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3697 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698}
3699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3700static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3701 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3702 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3703
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3704 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3705 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3706 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3707 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3708 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3709
3710 unsigned align = 0;
3711 unsigned index = 0;
3712 unsigned inc = 1;
3713 switch (size) {
3714 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3715 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3716 case 0:
3717 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3719 index = fieldFromInstruction32(Insn, 5, 3);
3720 break;
3721 case 1:
3722 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3723 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3724 index = fieldFromInstruction32(Insn, 6, 2);
3725 if (fieldFromInstruction32(Insn, 5, 1))
3726 inc = 2;
3727 break;
3728 case 2:
3729 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3730 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3731 index = fieldFromInstruction32(Insn, 7, 1);
3732 if (fieldFromInstruction32(Insn, 6, 1))
3733 inc = 2;
3734 break;
3735 }
3736
3737 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3739 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3740 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3743 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3744 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3745 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3747 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3748 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3749 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3750 }
3751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3753 return MCDisassembler::Fail;
3754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3755 return MCDisassembler::Fail;
3756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3757 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3758 Inst.addOperand(MCOperand::CreateImm(index));
3759
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3760 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3761}
3762
3763
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3764static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3765 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3766 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3767
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3768 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3769 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3770 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3771 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3772 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3773
3774 unsigned align = 0;
3775 unsigned index = 0;
3776 unsigned inc = 1;
3777 switch (size) {
3778 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3779 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3780 case 0:
3781 if (fieldFromInstruction32(Insn, 4, 1))
3782 align = 4;
3783 index = fieldFromInstruction32(Insn, 5, 3);
3784 break;
3785 case 1:
3786 if (fieldFromInstruction32(Insn, 4, 1))
3787 align = 8;
3788 index = fieldFromInstruction32(Insn, 6, 2);
3789 if (fieldFromInstruction32(Insn, 5, 1))
3790 inc = 2;
3791 break;
3792 case 2:
3793 if (fieldFromInstruction32(Insn, 4, 2))
3794 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3795 index = fieldFromInstruction32(Insn, 7, 1);
3796 if (fieldFromInstruction32(Insn, 6, 1))
3797 inc = 2;
3798 break;
3799 }
3800
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3802 return MCDisassembler::Fail;
3803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3804 return MCDisassembler::Fail;
3805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3806 return MCDisassembler::Fail;
3807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3808 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3809
3810 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3812 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3813 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3815 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3816 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3817 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3818 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3820 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3821 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3822 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3823 }
3824
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3826 return MCDisassembler::Fail;
3827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3828 return MCDisassembler::Fail;
3829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3830 return MCDisassembler::Fail;
3831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3832 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 Inst.addOperand(MCOperand::CreateImm(index));
3834
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3835 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3836}
3837
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3838static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3839 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3840 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3841
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3842 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3843 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3844 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3845 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3846 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3847
3848 unsigned align = 0;
3849 unsigned index = 0;
3850 unsigned inc = 1;
3851 switch (size) {
3852 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3853 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3854 case 0:
3855 if (fieldFromInstruction32(Insn, 4, 1))
3856 align = 4;
3857 index = fieldFromInstruction32(Insn, 5, 3);
3858 break;
3859 case 1:
3860 if (fieldFromInstruction32(Insn, 4, 1))
3861 align = 8;
3862 index = fieldFromInstruction32(Insn, 6, 2);
3863 if (fieldFromInstruction32(Insn, 5, 1))
3864 inc = 2;
3865 break;
3866 case 2:
3867 if (fieldFromInstruction32(Insn, 4, 2))
3868 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3869 index = fieldFromInstruction32(Insn, 7, 1);
3870 if (fieldFromInstruction32(Insn, 6, 1))
3871 inc = 2;
3872 break;
3873 }
3874
3875 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3877 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3878 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3880 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3881 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3882 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3883 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3885 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3886 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3887 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3888 }
3889
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3893 return MCDisassembler::Fail;
3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3895 return MCDisassembler::Fail;
3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3897 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3898 Inst.addOperand(MCOperand::CreateImm(index));
3899
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3900 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3901}
3902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3903static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3904 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3905 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3906 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3907 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3908 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3909 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3910 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3911
3912 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3913 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3914
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3915 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3918 return MCDisassembler::Fail;
3919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3920 return MCDisassembler::Fail;
3921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3922 return MCDisassembler::Fail;
3923 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3924 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3925
3926 return S;
3927}
3928
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3929static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3930 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3931 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3932 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3933 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3934 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3935 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3936 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3937
3938 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3939 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3940
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3942 return MCDisassembler::Fail;
3943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3944 return MCDisassembler::Fail;
3945 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3946 return MCDisassembler::Fail;
3947 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3948 return MCDisassembler::Fail;
3949 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3950 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3951
3952 return S;
3953}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3955static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3956 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3957 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3958 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3959 // The InstPrinter needs to have the low bit of the predicate in
3960 // the mask operand to be able to print it properly.
3961 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3962
3963 if (pred == 0xF) {
3964 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3965 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3966 }
3967
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3968 if ((mask & 0xF) == 0) {
3969 // Preserve the high bit of the mask, which is the low bit of
3970 // the predicate.
3971 mask &= 0x10;
3972 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3973 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3974 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3975
3976 Inst.addOperand(MCOperand::CreateImm(pred));
3977 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3978 return S;
3979}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3980
3981static DecodeStatus
3982DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3983 uint64_t Address, const void *Decoder) {
3984 DecodeStatus S = MCDisassembler::Success;
3985
3986 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3987 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3988 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3989 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3990 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3991 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3992 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3993 bool writeback = (W == 1) | (P == 0);
3994
3995 addr |= (U << 8) | (Rn << 9);
3996
3997 if (writeback && (Rn == Rt || Rn == Rt2))
3998 Check(S, MCDisassembler::SoftFail);
3999 if (Rt == Rt2)
4000 Check(S, MCDisassembler::SoftFail);
4001
4002 // Rt
4003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4004 return MCDisassembler::Fail;
4005 // Rt2
4006 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4007 return MCDisassembler::Fail;
4008 // Writeback operand
4009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4010 return MCDisassembler::Fail;
4011 // addr
4012 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4013 return MCDisassembler::Fail;
4014
4015 return S;
4016}
4017
4018static DecodeStatus
4019DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4020 uint64_t Address, const void *Decoder) {
4021 DecodeStatus S = MCDisassembler::Success;
4022
4023 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4024 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4025 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4026 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4027 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4028 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4029 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4030 bool writeback = (W == 1) | (P == 0);
4031
4032 addr |= (U << 8) | (Rn << 9);
4033
4034 if (writeback && (Rn == Rt || Rn == Rt2))
4035 Check(S, MCDisassembler::SoftFail);
4036
4037 // Writeback operand
4038 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4039 return MCDisassembler::Fail;
4040 // Rt
4041 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4042 return MCDisassembler::Fail;
4043 // Rt2
4044 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4045 return MCDisassembler::Fail;
4046 // addr
4047 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4048 return MCDisassembler::Fail;
4049
4050 return S;
4051}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4052
4053static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4054 uint64_t Address, const void *Decoder) {
4055 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4056 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4057 if (sign1 != sign2) return MCDisassembler::Fail;
4058
4059 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4060 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4061 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4062 Val |= sign1 << 12;
4063 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4064
4065 return MCDisassembler::Success;
4066}
4067
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4068static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4069 uint64_t Address,
4070 const void *Decoder) {
4071 DecodeStatus S = MCDisassembler::Success;
4072
4073 // Shift of "asr #32" is not allowed in Thumb2 mode.
4074 if (Val == 0x20) S = MCDisassembler::SoftFail;
4075 Inst.addOperand(MCOperand::CreateImm(Val));
4076 return S;
4077}
4078