Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame^]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame^]	15	#include "MCTargetDesc/ARMMCExpr.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	16	#include "llvm/MC/EDInstInfo.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame^]	17	#include "llvm/MC/MCContext.h"
				18	#include "llvm/MC/MCExpr.h"
				19	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/MC/MCInst.h"
Benjamin Kramer	eea66f6	2011-11-11 12:39:41 +0000	[diff] [blame]	21	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	75e3b7f	2012-04-03 15:48:14 +0000	[diff] [blame]	22	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/Debug.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	24	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	25	#include "llvm/Support/LEB128.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame^]	26	#include "llvm/Support/MemoryObject.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	27	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	28	#include "llvm/Support/raw_ostream.h"
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	29	#include <vector>
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	30
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	31	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	32
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	33	typedef MCDisassembler::DecodeStatus DecodeStatus;
				34
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	35	namespace {
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	36	// Handles the condition code status of instructions in IT blocks
				37	class ITStatus
				38	{
				39	public:
				40	// Returns the condition code for instruction in IT block
				41	unsigned getITCC() {
				42	unsigned CC = ARMCC::AL;
				43	if (instrInITBlock())
				44	CC = ITStates.back();
				45	return CC;
				46	}
				47
				48	// Advances the IT block state to the next T or E
				49	void advanceITState() {
				50	ITStates.pop_back();
				51	}
				52
				53	// Returns true if the current instruction is in an IT block
				54	bool instrInITBlock() {
				55	return !ITStates.empty();
				56	}
				57
				58	// Returns true if current instruction is the last instruction in an IT block
				59	bool instrLastInITBlock() {
				60	return ITStates.size() == 1;
				61	}
				62
				63	// Called when decoding an IT instruction. Sets the IT state for the following
				64	// instructions that for the IT block. Firstcond and Mask correspond to the
				65	// fields in the IT instruction encoding.
				66	void setITState(char Firstcond, char Mask) {
				67	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	68	unsigned CondBit0 = Firstcond & 1;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned NumTZ = CountTrailingZeros_32(Mask);
				70	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				71	assert(NumTZ <= 3 && "Invalid IT mask!");
				72	// push condition codes onto the stack the correct order for the pops
				73	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				74	bool T = ((Mask >> Pos) & 1) == CondBit0;
				75	if (T)
				76	ITStates.push_back(CCBits);
				77	else
				78	ITStates.push_back(CCBits ^ 1);
				79	}
				80	ITStates.push_back(CCBits);
				81	}
				82
				83	private:
				84	std::vector<unsigned char> ITStates;
				85	};
				86	}
				87
				88	namespace {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	89	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				90	class ARMDisassembler : public MCDisassembler {
				91	public:
				92	/// Constructor - Initializes the disassembler.
				93	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	94	ARMDisassembler(const MCSubtargetInfo &STI) :
				95	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	96	}
				97
				98	~ARMDisassembler() {
				99	}
				100
				101	/// getInstruction - See MCDisassembler.
				102	DecodeStatus getInstruction(MCInst &instr,
				103	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	104	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	105	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	106	raw_ostream &vStream,
				107	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	108
				109	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	110	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	111	private:
				112	};
				113
				114	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				115	class ThumbDisassembler : public MCDisassembler {
				116	public:
				117	/// Constructor - Initializes the disassembler.
				118	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	119	ThumbDisassembler(const MCSubtargetInfo &STI) :
				120	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	121	}
				122
				123	~ThumbDisassembler() {
				124	}
				125
				126	/// getInstruction - See MCDisassembler.
				127	DecodeStatus getInstruction(MCInst &instr,
				128	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	129	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	130	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	131	raw_ostream &vStream,
				132	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	133
				134	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	135	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	136	private:
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	137	mutable ITStatus ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	138	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	139	void UpdateThumbVFPPredicate(MCInst&) const;
				140	};
				141	}
				142
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	143	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	144	switch (In) {
				145	case MCDisassembler::Success:
				146	// Out stays the same.
				147	return true;
				148	case MCDisassembler::SoftFail:
				149	Out = In;
				150	return true;
				151	case MCDisassembler::Fail:
				152	Out = In;
				153	return false;
				154	}
David Blaikie	4d6ccb5	2012-01-20 21:51:11 +0000	[diff] [blame]	155	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	156	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	157
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	158
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	159	// Forward declare these because the autogenerated code will reference them.
				160	// Definitions are further down.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo, uint64_t Address,
				165	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	177	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	179	unsigned RegNo,
				180	uint64_t Address,
				181	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	185	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	187	unsigned RegNo, uint64_t Address,
				188	const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	189
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	202
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	208	unsigned Insn,
				209	uint64_t Address,
				210	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	217	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
				219
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	221	unsigned Insn,
				222	uint64_t Adddress,
				223	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	240	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				241	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	244	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	245	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	246	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	247	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	248	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	250	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	284	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
				318
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	319
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	326	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	327	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	352	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	353	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
				382
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	385	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				386	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	387	#include "ARMGenDisassemblerTables.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	388	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	389
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	390	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				391	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	392	}
				393
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	394	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				395	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	396	}
				397
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	398	const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	399	return instInfoARM;
				400	}
				401
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	402	const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	403	return instInfoARM;
				404	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	405
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	406	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	407	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	408	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	409	raw_ostream &os,
				410	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	411	CommentStream = &cs;
				412
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	413	uint8_t bytes[4];
				414
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	415	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				416	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				417
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	418	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	419	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				420	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	421	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	422	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423
				424	// Encoded as a small-endian 32-bit word in the stream.
				425	uint32_t insn = (bytes[3] << 24) \|
				426	(bytes[2] << 16) \|
				427	(bytes[1] << 8) \|
				428	(bytes[0] << 0);
				429
				430	// Calling the auto-generated decoder function.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	431	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				432	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	433	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	434	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	435	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	436	}
				437
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	438	// VFP and NEON instructions, similarly, are shared between ARM
				439	// and Thumb modes.
				440	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	441	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	442	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	443	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	444	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	445	}
				446
				447	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	448	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				449	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	450	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	451	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	452	// Add a fake predicate operand, because we share these instruction
				453	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	454	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				455	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	456	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	457	}
				458
				459	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	460	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				461	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	462	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	463	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	464	// Add a fake predicate operand, because we share these instruction
				465	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	466	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				467	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	468	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	469	}
				470
				471	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	472	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				473	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	474	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	475	Size = 4;
				476	// Add a fake predicate operand, because we share these instruction
				477	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	478	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				479	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	480	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	481	}
				482
				483	MI.clear();
				484
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	485	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	486	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	487	}
				488
				489	namespace llvm {
Benjamin Kramer	1a2f988	2011-10-22 16:50:00 +0000	[diff] [blame]	490	extern const MCInstrDesc ARMInsts[];
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	491	}
				492
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	493	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				494	/// immediate Value in the MCInst. The immediate Value has had any PC
				495	/// adjustment made by the caller. If the instruction is a branch instruction
				496	/// then isBranch is true, else false. If the getOpInfo() function was set as
				497	/// part of the setupForSymbolicDisassembly() call then that function is called
				498	/// to get any symbolic information at the Address for this instruction. If
				499	/// that returns non-zero then the symbolic information it returns is used to
				500	/// create an MCExpr and that is added as an operand to the MCInst. If
				501	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				502	/// Value is done and if a symbol is found an MCExpr is created with that, else
				503	/// an MCExpr with Value is created. This function returns true if it adds an
				504	/// operand to the MCInst and false otherwise.
				505	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				506	bool isBranch, uint64_t InstSize,
				507	MCInst &MI, const void *Decoder) {
				508	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				509	LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	510	struct LLVMOpInfo1 SymbolicOp;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	511	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	512	SymbolicOp.Value = Value;
				513	void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	514
				515	if (!getOpInfo \|\|
				516	!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
				517	// Clear SymbolicOp.Value from above and also all other fields.
				518	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
				519	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				520	if (!SymbolLookUp)
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	521	return false;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	522	uint64_t ReferenceType;
				523	if (isBranch)
				524	ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
				525	else
				526	ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
				527	const char *ReferenceName;
Kevin Enderby	88d1266	2012-10-18 21:49:18 +0000	[diff] [blame]	528	uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
				529	const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
				530	Address, &ReferenceName);
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	531	if (Name) {
				532	SymbolicOp.AddSymbol.Name = Name;
				533	SymbolicOp.AddSymbol.Present = true;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	534	}
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	535	// For branches always create an MCExpr so it gets printed as hex address.
				536	else if (isBranch) {
				537	SymbolicOp.Value = Value;
				538	}
				539	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
				540	(*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
				541	if (!Name && !isBranch)
				542	return false;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	543	}
				544
				545	MCContext *Ctx = Dis->getMCContext();
				546	const MCExpr *Add = NULL;
				547	if (SymbolicOp.AddSymbol.Present) {
				548	if (SymbolicOp.AddSymbol.Name) {
				549	StringRef Name(SymbolicOp.AddSymbol.Name);
				550	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				551	Add = MCSymbolRefExpr::Create(Sym, *Ctx);
				552	} else {
				553	Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
				554	}
				555	}
				556
				557	const MCExpr *Sub = NULL;
				558	if (SymbolicOp.SubtractSymbol.Present) {
				559	if (SymbolicOp.SubtractSymbol.Name) {
				560	StringRef Name(SymbolicOp.SubtractSymbol.Name);
				561	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				562	Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
				563	} else {
				564	Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
				565	}
				566	}
				567
				568	const MCExpr *Off = NULL;
				569	if (SymbolicOp.Value != 0)
				570	Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
				571
				572	const MCExpr *Expr;
				573	if (Sub) {
				574	const MCExpr *LHS;
				575	if (Add)
				576	LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
				577	else
				578	LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
				579	if (Off != 0)
				580	Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
				581	else
				582	Expr = LHS;
				583	} else if (Add) {
				584	if (Off != 0)
				585	Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
				586	else
				587	Expr = Add;
				588	} else {
				589	if (Off != 0)
				590	Expr = Off;
				591	else
				592	Expr = MCConstantExpr::Create(0, *Ctx);
				593	}
				594
				595	if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
				596	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
				597	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
				598	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
				599	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
				600	MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	601	else
Craig Topper	bc21981	2012-02-07 02:50:20 +0000	[diff] [blame]	602	llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	603
				604	return true;
				605	}
				606
				607	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				608	/// referenced by a load instruction with the base register that is the Pc.
				609	/// These can often be values in a literal pool near the Address of the
				610	/// instruction. The Address of the instruction and its immediate Value are
				611	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	c8e41c5	2012-07-23 08:51:15 +0000	[diff] [blame]	612	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	613	/// the referenced address is that of a symbol. Or it will return a pointer to
				614	/// a literal 'C' string if the referenced address of the literal pool's entry
				615	/// is an address into a section with 'C' string literals.
				616	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	617	const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	618	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				619	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				620	if (SymbolLookUp) {
				621	void *DisInfo = Dis->getDisInfoBlock();
				622	uint64_t ReferenceType;
				623	ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
				624	const char *ReferenceName;
				625	(void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
				626	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr \|\|
				627	ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
				628	(*Dis->CommentStream) << "literal pool for: " << ReferenceName;
				629	}
				630	}
				631
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	632	// Thumb1 instructions don't have explicit S bits. Rather, they
				633	// implicitly set CPSR. Since it's not represented in the encoding, the
				634	// auto-generated decoder won't inject the CPSR operand. We need to fix
				635	// that as a post-pass.
				636	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				637	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	638	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	639	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	640	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				641	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	642	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	643	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	644	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				645	return;
				646	}
				647	}
				648
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	649	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	650	}
				651
				652	// Most Thumb instructions don't have explicit predicates in the
				653	// encoding, but rather get their predicates from IT context. We need
				654	// to fix up the predicate operands using this context information as a
				655	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	656	MCDisassembler::DecodeStatus
				657	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	658	MCDisassembler::DecodeStatus S = Success;
				659
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	660	// A few instructions actually have predicates encoded in them. Don't
				661	// try to overwrite it if we're seeing one of those.
				662	switch (MI.getOpcode()) {
				663	case ARM::tBcc:
				664	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	665	case ARM::tCBZ:
				666	case ARM::tCBNZ:
Owen Anderson	9f666b5	2011-09-19 23:47:10 +0000	[diff] [blame]	667	case ARM::tCPS:
				668	case ARM::t2CPS3p:
				669	case ARM::t2CPS2p:
				670	case ARM::t2CPS1p:
Owen Anderson	d9346fb	2011-09-19 23:57:20 +0000	[diff] [blame]	671	case ARM::tMOVSr:
Owen Anderson	c18e940	2011-10-13 17:58:39 +0000	[diff] [blame]	672	case ARM::tSETEND:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	673	// Some instructions (mostly conditional branches) are not
				674	// allowed in IT blocks.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	675	if (ITBlock.instrInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	676	S = SoftFail;
				677	else
				678	return Success;
				679	break;
				680	case ARM::tB:
				681	case ARM::t2B:
Owen Anderson	04c7877	2011-09-19 22:34:23 +0000	[diff] [blame]	682	case ARM::t2TBB:
				683	case ARM::t2TBH:
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	684	// Some instructions (mostly unconditional branches) can
				685	// only appears at the end of, or outside of, an IT.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	686	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	687	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	688	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	689	default:
				690	break;
				691	}
				692
				693	// If we're in an IT block, base the predicate on that. Otherwise,
				694	// assume a predicate of AL.
				695	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	696	CC = ITBlock.getITCC();
				697	if (CC == 0xF)
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	698	CC = ARMCC::AL;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	699	if (ITBlock.instrInITBlock())
				700	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	701
				702	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	703	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	704	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	705	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				706	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	707	if (OpInfo[i].isPredicate()) {
				708	I = MI.insert(I, MCOperand::CreateImm(CC));
				709	++I;
				710	if (CC == ARMCC::AL)
				711	MI.insert(I, MCOperand::CreateReg(0));
				712	else
				713	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	714	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	715	}
				716	}
				717
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	718	I = MI.insert(I, MCOperand::CreateImm(CC));
				719	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	720	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	721	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	722	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	723	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	724
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	725	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	726	}
				727
				728	// Thumb VFP instructions are a special case. Because we share their
				729	// encodings between ARM and Thumb modes, and they are predicable in ARM
				730	// mode, the auto-generated decoder will give them an (incorrect)
				731	// predicate operand. We need to rewrite these operands based on the IT
				732	// context as a post-pass.
				733	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				734	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	735	CC = ITBlock.getITCC();
				736	if (ITBlock.instrInITBlock())
				737	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	738
				739	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				740	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	741	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				742	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	743	if (OpInfo[i].isPredicate() ) {
				744	I->setImm(CC);
				745	++I;
				746	if (CC == ARMCC::AL)
				747	I->setReg(0);
				748	else
				749	I->setReg(ARM::CPSR);
				750	return;
				751	}
				752	}
				753	}
				754
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	755	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	756	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	757	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	758	raw_ostream &os,
				759	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	760	CommentStream = &cs;
				761
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	762	uint8_t bytes[4];
				763
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	764	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				765	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				766
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	767	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	768	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				769	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	770	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	771	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	772
				773	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	774	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				775	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	776	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	777	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	778	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	779	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	780	}
				781
				782	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	783	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				784	Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	785	if (result) {
				786	Size = 2;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	787	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	788	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	789	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	790	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	791	}
				792
				793	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	794	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				795	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	796	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	797	Size = 2;
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	798
				799	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				800	// the Thumb predicate.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	801	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	802	result = MCDisassembler::SoftFail;
				803
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	804	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	805
				806	// If we find an IT instruction, we need to parse its condition
				807	// code and mask operands so that we can apply them correctly
				808	// to the subsequent instructions.
				809	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	810
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	811	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	812	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	813	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	814	}
				815
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	816	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	817	}
				818
				819	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	820	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				821	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	822	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	823	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	824
				825	uint32_t insn32 = (bytes[3] << 8) \|
				826	(bytes[2] << 0) \|
				827	(bytes[1] << 24) \|
				828	(bytes[0] << 16);
				829	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	830	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				831	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	832	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	833	Size = 4;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	834	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	835	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	836	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	837	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	838	}
				839
				840	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	841	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				842	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	843	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	844	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	845	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	846	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	847	}
				848
				849	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	850	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	851	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	852	Size = 4;
				853	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	854	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	855	}
				856
				857	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	858	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				859	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	860	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	861	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	862	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	863	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	864	}
				865
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	866	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	867	MI.clear();
				868	uint32_t NEONLdStInsn = insn32;
				869	NEONLdStInsn &= 0xF0FFFFFF;
				870	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	871	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				872	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	873	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	874	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	875	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	876	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	877	}
				878	}
				879
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	880	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	881	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	882	uint32_t NEONDataInsn = insn32;
				883	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				884	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				885	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	886	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				887	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	888	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	889	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	890	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	891	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	892	}
				893	}
				894
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	895	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	896	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	897	}
				898
				899
				900	extern "C" void LLVMInitializeARMDisassembler() {
				901	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				902	createARMDisassembler);
				903	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				904	createThumbDisassembler);
				905	}
				906
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	907	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	908	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				909	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				910	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				911	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				912	};
				913
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	914	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	915	uint64_t Address, const void *Decoder) {
				916	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	917	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	918
				919	unsigned Register = GPRDecoderTable[RegNo];
				920	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	921	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	922	}
				923
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	924	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	925	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	926	uint64_t Address, const void *Decoder) {
Silviu Baranga	5c062ad	2012-03-20 15:54:56 +0000	[diff] [blame]	927	DecodeStatus S = MCDisassembler::Success;
				928
				929	if (RegNo == 15)
				930	S = MCDisassembler::SoftFail;
				931
				932	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				933
				934	return S;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	935	}
				936
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	937	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	938	uint64_t Address, const void *Decoder) {
				939	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	940	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	941	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				942	}
				943
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	944	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	945	uint64_t Address, const void *Decoder) {
				946	unsigned Register = 0;
				947	switch (RegNo) {
				948	case 0:
				949	Register = ARM::R0;
				950	break;
				951	case 1:
				952	Register = ARM::R1;
				953	break;
				954	case 2:
				955	Register = ARM::R2;
				956	break;
				957	case 3:
				958	Register = ARM::R3;
				959	break;
				960	case 9:
				961	Register = ARM::R9;
				962	break;
				963	case 12:
				964	Register = ARM::R12;
				965	break;
				966	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	967	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	968	}
				969
				970	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	971	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	972	}
				973
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	974	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	975	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	976	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	977	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				978	}
				979
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	980	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	981	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				982	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				983	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				984	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				985	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				986	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				987	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				988	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				989	};
				990
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	991	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	992	uint64_t Address, const void *Decoder) {
				993	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	994	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	995
				996	unsigned Register = SPRDecoderTable[RegNo];
				997	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	998	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	999	}
				1000
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1001	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1002	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1003	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1004	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1005	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1006	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1007	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1008	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1009	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1010	};
				1011
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1012	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1013	uint64_t Address, const void *Decoder) {
				1014	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1015	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1016
				1017	unsigned Register = DPRDecoderTable[RegNo];
				1018	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1019	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1020	}
				1021
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1022	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1023	uint64_t Address, const void *Decoder) {
				1024	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1025	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1026	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1027	}
				1028
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1029	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1030	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1031	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1032	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1033	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1034	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1035	}
				1036
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1037	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1038	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1039	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1040	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1041	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1042	};
				1043
				1044
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1045	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1046	uint64_t Address, const void *Decoder) {
				1047	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1048	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1049	RegNo >>= 1;
				1050
				1051	unsigned Register = QPRDecoderTable[RegNo];
				1052	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1053	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1054	}
				1055
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1056	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1057	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1058	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1059	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1060	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1061	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1062	ARM::Q15
				1063	};
				1064
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1065	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1066	uint64_t Address, const void *Decoder) {
				1067	if (RegNo > 30)
				1068	return MCDisassembler::Fail;
				1069
				1070	unsigned Register = DPairDecoderTable[RegNo];
				1071	Inst.addOperand(MCOperand::CreateReg(Register));
				1072	return MCDisassembler::Success;
				1073	}
				1074
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1075	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1076	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1077	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1078	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1079	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1080	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1081	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1082	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1083	ARM::D28_D30, ARM::D29_D31
				1084	};
				1085
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1086	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1087	unsigned RegNo,
				1088	uint64_t Address,
				1089	const void *Decoder) {
				1090	if (RegNo > 29)
				1091	return MCDisassembler::Fail;
				1092
				1093	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1094	Inst.addOperand(MCOperand::CreateReg(Register));
				1095	return MCDisassembler::Success;
				1096	}
				1097
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1098	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1099	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1100	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	1101	// AL predicate is not allowed on Thumb1 branches.
				1102	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1103	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1104	Inst.addOperand(MCOperand::CreateImm(Val));
				1105	if (Val == ARMCC::AL) {
				1106	Inst.addOperand(MCOperand::CreateReg(0));
				1107	} else
				1108	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1109	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1110	}
				1111
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1112	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1113	uint64_t Address, const void *Decoder) {
				1114	if (Val)
				1115	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1116	else
				1117	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1118	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1119	}
				1120
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1121	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	uint64_t Address, const void *Decoder) {
				1123	uint32_t imm = Val & 0xFF;
				1124	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	ecb830e	2011-10-13 23:36:06 +0000	[diff] [blame]	1125	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1126	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1127	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	}
				1129
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1130	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1131	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1132	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1133
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1134	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1135	unsigned type = fieldFromInstruction(Val, 5, 2);
				1136	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1137
				1138	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1139	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1140	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1141
				1142	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1143	switch (type) {
				1144	case 0:
				1145	Shift = ARM_AM::lsl;
				1146	break;
				1147	case 1:
				1148	Shift = ARM_AM::lsr;
				1149	break;
				1150	case 2:
				1151	Shift = ARM_AM::asr;
				1152	break;
				1153	case 3:
				1154	Shift = ARM_AM::ror;
				1155	break;
				1156	}
				1157
				1158	if (Shift == ARM_AM::ror && imm == 0)
				1159	Shift = ARM_AM::rrx;
				1160
				1161	unsigned Op = Shift \| (imm << 3);
				1162	Inst.addOperand(MCOperand::CreateImm(Op));
				1163
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1164	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1165	}
				1166
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1167	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1168	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1169	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1170
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1171	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1172	unsigned type = fieldFromInstruction(Val, 5, 2);
				1173	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1174
				1175	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1176	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1177	return MCDisassembler::Fail;
				1178	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1179	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
				1181	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1182	switch (type) {
				1183	case 0:
				1184	Shift = ARM_AM::lsl;
				1185	break;
				1186	case 1:
				1187	Shift = ARM_AM::lsr;
				1188	break;
				1189	case 2:
				1190	Shift = ARM_AM::asr;
				1191	break;
				1192	case 3:
				1193	Shift = ARM_AM::ror;
				1194	break;
				1195	}
				1196
				1197	Inst.addOperand(MCOperand::CreateImm(Shift));
				1198
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1199	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1200	}
				1201
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1202	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1203	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1204	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1205
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1206	bool writebackLoad = false;
				1207	unsigned writebackReg = 0;
				1208	switch (Inst.getOpcode()) {
				1209	default:
				1210	break;
				1211	case ARM::LDMIA_UPD:
				1212	case ARM::LDMDB_UPD:
				1213	case ARM::LDMIB_UPD:
				1214	case ARM::LDMDA_UPD:
				1215	case ARM::t2LDMIA_UPD:
				1216	case ARM::t2LDMDB_UPD:
				1217	writebackLoad = true;
				1218	writebackReg = Inst.getOperand(0).getReg();
				1219	break;
				1220	}
				1221
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	1222	// Empty register lists are not allowed.
Owen Anderson	244006d	2011-11-02 17:46:18 +0000	[diff] [blame]	1223	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1224	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1225	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1226	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1227	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1228	// Writeback not allowed if Rn is in the target list.
				1229	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1230	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1231	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1232	}
				1233
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1234	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1235	}
				1236
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1237	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1238	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1239	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1240
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1241	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1242	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1243
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1244	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1245	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1246	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1247	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1248	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1249	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1250
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1251	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1252	}
				1253
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1254	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1255	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1256	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1257
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1258	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1259	unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Baranga	b422d0b	2012-05-03 16:38:40 +0000	[diff] [blame]	1260
				1261	regs = regs >> 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1262
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1263	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1264	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1265	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1266	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1267	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1268	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1269
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1270	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1271	}
				1272
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1273	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1274	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1275	// This operand encodes a mask of contiguous zeros between a specified MSB
				1276	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1277	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1278	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1279	// create the final mask.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1280	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1281	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1282
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1283	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	1c83093	2012-11-29 23:47:11 +0000	[diff] [blame]	1284	if (lsb > msb) {
				1285	Check(S, MCDisassembler::SoftFail);
				1286	// The check above will cause the warning for the "potentially undefined
				1287	// instruction encoding" but we can't build a bad MCOperand value here
				1288	// with a lsb > msb or else printing the MCInst will cause a crash.
				1289	lsb = msb;
				1290	}
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1291
Owen Anderson	8b22778	2011-09-16 23:04:48 +0000	[diff] [blame]	1292	uint32_t msb_mask = 0xFFFFFFFF;
				1293	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1294	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1295
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1296	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1297	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1298	}
				1299
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1300	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1301	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1302	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1303
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1304	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1305	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1306	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1307	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1308	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1309	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1310
				1311	switch (Inst.getOpcode()) {
				1312	case ARM::LDC_OFFSET:
				1313	case ARM::LDC_PRE:
				1314	case ARM::LDC_POST:
				1315	case ARM::LDC_OPTION:
				1316	case ARM::LDCL_OFFSET:
				1317	case ARM::LDCL_PRE:
				1318	case ARM::LDCL_POST:
				1319	case ARM::LDCL_OPTION:
				1320	case ARM::STC_OFFSET:
				1321	case ARM::STC_PRE:
				1322	case ARM::STC_POST:
				1323	case ARM::STC_OPTION:
				1324	case ARM::STCL_OFFSET:
				1325	case ARM::STCL_PRE:
				1326	case ARM::STCL_POST:
				1327	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1328	case ARM::t2LDC_OFFSET:
				1329	case ARM::t2LDC_PRE:
				1330	case ARM::t2LDC_POST:
				1331	case ARM::t2LDC_OPTION:
				1332	case ARM::t2LDCL_OFFSET:
				1333	case ARM::t2LDCL_PRE:
				1334	case ARM::t2LDCL_POST:
				1335	case ARM::t2LDCL_OPTION:
				1336	case ARM::t2STC_OFFSET:
				1337	case ARM::t2STC_PRE:
				1338	case ARM::t2STC_POST:
				1339	case ARM::t2STC_OPTION:
				1340	case ARM::t2STCL_OFFSET:
				1341	case ARM::t2STCL_PRE:
				1342	case ARM::t2STCL_POST:
				1343	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1344	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1345	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1346	break;
				1347	default:
				1348	break;
				1349	}
				1350
				1351	Inst.addOperand(MCOperand::CreateImm(coproc));
				1352	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1353	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1354	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1355
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1356	switch (Inst.getOpcode()) {
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1357	case ARM::t2LDC2_OFFSET:
				1358	case ARM::t2LDC2L_OFFSET:
				1359	case ARM::t2LDC2_PRE:
				1360	case ARM::t2LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1361	case ARM::t2STC2_OFFSET:
				1362	case ARM::t2STC2L_OFFSET:
				1363	case ARM::t2STC2_PRE:
				1364	case ARM::t2STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1365	case ARM::LDC2_OFFSET:
				1366	case ARM::LDC2L_OFFSET:
				1367	case ARM::LDC2_PRE:
				1368	case ARM::LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1369	case ARM::STC2_OFFSET:
				1370	case ARM::STC2L_OFFSET:
				1371	case ARM::STC2_PRE:
				1372	case ARM::STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1373	case ARM::t2LDC_OFFSET:
				1374	case ARM::t2LDCL_OFFSET:
				1375	case ARM::t2LDC_PRE:
				1376	case ARM::t2LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1377	case ARM::t2STC_OFFSET:
				1378	case ARM::t2STCL_OFFSET:
				1379	case ARM::t2STC_PRE:
				1380	case ARM::t2STCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1381	case ARM::LDC_OFFSET:
				1382	case ARM::LDCL_OFFSET:
				1383	case ARM::LDC_PRE:
				1384	case ARM::LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1385	case ARM::STC_OFFSET:
				1386	case ARM::STCL_OFFSET:
				1387	case ARM::STC_PRE:
				1388	case ARM::STCL_PRE:
Jim Grosbach	81b2928	2011-10-12 21:59:02 +0000	[diff] [blame]	1389	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1390	Inst.addOperand(MCOperand::CreateImm(imm));
				1391	break;
				1392	case ARM::t2LDC2_POST:
				1393	case ARM::t2LDC2L_POST:
				1394	case ARM::t2STC2_POST:
				1395	case ARM::t2STC2L_POST:
				1396	case ARM::LDC2_POST:
				1397	case ARM::LDC2L_POST:
				1398	case ARM::STC2_POST:
				1399	case ARM::STC2L_POST:
				1400	case ARM::t2LDC_POST:
				1401	case ARM::t2LDCL_POST:
				1402	case ARM::t2STC_POST:
				1403	case ARM::t2STCL_POST:
				1404	case ARM::LDC_POST:
				1405	case ARM::LDCL_POST:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1406	case ARM::STC_POST:
				1407	case ARM::STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1408	imm \|= U << 8;
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1409	// fall through.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1410	default:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1411	// The 'option' variant doesn't encode 'U' in the immediate since
				1412	// the immediate is unsigned [0,255].
				1413	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1414	break;
				1415	}
				1416
				1417	switch (Inst.getOpcode()) {
				1418	case ARM::LDC_OFFSET:
				1419	case ARM::LDC_PRE:
				1420	case ARM::LDC_POST:
				1421	case ARM::LDC_OPTION:
				1422	case ARM::LDCL_OFFSET:
				1423	case ARM::LDCL_PRE:
				1424	case ARM::LDCL_POST:
				1425	case ARM::LDCL_OPTION:
				1426	case ARM::STC_OFFSET:
				1427	case ARM::STC_PRE:
				1428	case ARM::STC_POST:
				1429	case ARM::STC_OPTION:
				1430	case ARM::STCL_OFFSET:
				1431	case ARM::STCL_PRE:
				1432	case ARM::STCL_POST:
				1433	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1434	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1435	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1436	break;
				1437	default:
				1438	break;
				1439	}
				1440
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1441	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1442	}
				1443
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1444	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1445	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1446	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1447	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1448
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1449	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1450	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1451	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1452	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1453	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1454	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1455	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1456	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1457
				1458	// On stores, the writeback operand precedes Rt.
				1459	switch (Inst.getOpcode()) {
				1460	case ARM::STR_POST_IMM:
				1461	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1462	case ARM::STRB_POST_IMM:
				1463	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1464	case ARM::STRT_POST_REG:
				1465	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1466	case ARM::STRBT_POST_REG:
				1467	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1468	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1469	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1470	break;
				1471	default:
				1472	break;
				1473	}
				1474
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1475	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1476	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1477
				1478	// On loads, the writeback operand comes after Rt.
				1479	switch (Inst.getOpcode()) {
				1480	case ARM::LDR_POST_IMM:
				1481	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1482	case ARM::LDRB_POST_IMM:
				1483	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1484	case ARM::LDRBT_POST_REG:
				1485	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1486	case ARM::LDRT_POST_REG:
				1487	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1489	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1490	break;
				1491	default:
				1492	break;
				1493	}
				1494
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1495	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1496	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1497
				1498	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1499	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1500	Op = ARM_AM::sub;
				1501
				1502	bool writeback = (P == 0) \|\| (W == 1);
				1503	unsigned idx_mode = 0;
				1504	if (P && writeback)
				1505	idx_mode = ARMII::IndexModePre;
				1506	else if (!P && writeback)
				1507	idx_mode = ARMII::IndexModePost;
				1508
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1509	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1510	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1511
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1512	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1513	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1514	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1515	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1516	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1517	case 0:
				1518	Opc = ARM_AM::lsl;
				1519	break;
				1520	case 1:
				1521	Opc = ARM_AM::lsr;
				1522	break;
				1523	case 2:
				1524	Opc = ARM_AM::asr;
				1525	break;
				1526	case 3:
				1527	Opc = ARM_AM::ror;
				1528	break;
				1529	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1530	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1531	}
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1532	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame]	1533	if (Opc == ARM_AM::ror && amt == 0)
				1534	Opc = ARM_AM::rrx;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1535	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1536
				1537	Inst.addOperand(MCOperand::CreateImm(imm));
				1538	} else {
				1539	Inst.addOperand(MCOperand::CreateReg(0));
				1540	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1541	Inst.addOperand(MCOperand::CreateImm(tmp));
				1542	}
				1543
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1544	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1545	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1546
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1547	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1548	}
				1549
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1550	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1551	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1552	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1553
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1554	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1555	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1556	unsigned type = fieldFromInstruction(Val, 5, 2);
				1557	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1558	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1559
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1560	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1561	switch (type) {
				1562	case 0:
				1563	ShOp = ARM_AM::lsl;
				1564	break;
				1565	case 1:
				1566	ShOp = ARM_AM::lsr;
				1567	break;
				1568	case 2:
				1569	ShOp = ARM_AM::asr;
				1570	break;
				1571	case 3:
				1572	ShOp = ARM_AM::ror;
				1573	break;
				1574	}
				1575
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame]	1576	if (ShOp == ARM_AM::ror && imm == 0)
				1577	ShOp = ARM_AM::rrx;
				1578
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1579	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1580	return MCDisassembler::Fail;
				1581	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1582	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1583	unsigned shift;
				1584	if (U)
				1585	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1586	else
				1587	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1588	Inst.addOperand(MCOperand::CreateImm(shift));
				1589
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1590	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1591	}
				1592
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1593	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1594	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1595	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1596	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1597
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1598	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1599	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1600	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1601	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1602	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1603	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1604	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1605	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1606	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1607	unsigned Rt2 = Rt + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1608
				1609	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1610
				1611	// For {LD,ST}RD, Rt must be even, else undefined.
				1612	switch (Inst.getOpcode()) {
				1613	case ARM::STRD:
				1614	case ARM::STRD_PRE:
				1615	case ARM::STRD_POST:
				1616	case ARM::LDRD:
				1617	case ARM::LDRD_PRE:
				1618	case ARM::LDRD_POST:
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1619	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1620	break;
				1621	default:
				1622	break;
				1623	}
				1624	switch (Inst.getOpcode()) {
				1625	case ARM::STRD:
				1626	case ARM::STRD_PRE:
				1627	case ARM::STRD_POST:
				1628	if (P == 0 && W == 1)
				1629	S = MCDisassembler::SoftFail;
				1630
				1631	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1632	S = MCDisassembler::SoftFail;
				1633	if (type && Rm == 15)
				1634	S = MCDisassembler::SoftFail;
				1635	if (Rt2 == 15)
				1636	S = MCDisassembler::SoftFail;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1637	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1638	S = MCDisassembler::SoftFail;
				1639	break;
				1640	case ARM::STRH:
				1641	case ARM::STRH_PRE:
				1642	case ARM::STRH_POST:
				1643	if (Rt == 15)
				1644	S = MCDisassembler::SoftFail;
				1645	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1646	S = MCDisassembler::SoftFail;
				1647	if (!type && Rm == 15)
				1648	S = MCDisassembler::SoftFail;
				1649	break;
				1650	case ARM::LDRD:
				1651	case ARM::LDRD_PRE:
				1652	case ARM::LDRD_POST:
				1653	if (type && Rn == 15){
				1654	if (Rt2 == 15)
				1655	S = MCDisassembler::SoftFail;
				1656	break;
				1657	}
				1658	if (P == 0 && W == 1)
				1659	S = MCDisassembler::SoftFail;
				1660	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1661	S = MCDisassembler::SoftFail;
				1662	if (!type && writeback && Rn == 15)
				1663	S = MCDisassembler::SoftFail;
				1664	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1665	S = MCDisassembler::SoftFail;
				1666	break;
				1667	case ARM::LDRH:
				1668	case ARM::LDRH_PRE:
				1669	case ARM::LDRH_POST:
				1670	if (type && Rn == 15){
				1671	if (Rt == 15)
				1672	S = MCDisassembler::SoftFail;
				1673	break;
				1674	}
				1675	if (Rt == 15)
				1676	S = MCDisassembler::SoftFail;
				1677	if (!type && Rm == 15)
				1678	S = MCDisassembler::SoftFail;
				1679	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1680	S = MCDisassembler::SoftFail;
				1681	break;
				1682	case ARM::LDRSH:
				1683	case ARM::LDRSH_PRE:
				1684	case ARM::LDRSH_POST:
				1685	case ARM::LDRSB:
				1686	case ARM::LDRSB_PRE:
				1687	case ARM::LDRSB_POST:
				1688	if (type && Rn == 15){
				1689	if (Rt == 15)
				1690	S = MCDisassembler::SoftFail;
				1691	break;
				1692	}
				1693	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1694	S = MCDisassembler::SoftFail;
				1695	if (!type && (Rt == 15 \|\| Rm == 15))
				1696	S = MCDisassembler::SoftFail;
				1697	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1698	S = MCDisassembler::SoftFail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1699	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1700	default:
				1701	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1702	}
				1703
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1704	if (writeback) { // Writeback
				1705	if (P)
				1706	U \|= ARMII::IndexModePre << 9;
				1707	else
				1708	U \|= ARMII::IndexModePost << 9;
				1709
				1710	// On stores, the writeback operand precedes Rt.
				1711	switch (Inst.getOpcode()) {
				1712	case ARM::STRD:
				1713	case ARM::STRD_PRE:
				1714	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1715	case ARM::STRH:
				1716	case ARM::STRH_PRE:
				1717	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1718	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1719	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1720	break;
				1721	default:
				1722	break;
				1723	}
				1724	}
				1725
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1726	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1727	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1728	switch (Inst.getOpcode()) {
				1729	case ARM::STRD:
				1730	case ARM::STRD_PRE:
				1731	case ARM::STRD_POST:
				1732	case ARM::LDRD:
				1733	case ARM::LDRD_PRE:
				1734	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1735	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1736	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1737	break;
				1738	default:
				1739	break;
				1740	}
				1741
				1742	if (writeback) {
				1743	// On loads, the writeback operand comes after Rt.
				1744	switch (Inst.getOpcode()) {
				1745	case ARM::LDRD:
				1746	case ARM::LDRD_PRE:
				1747	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1748	case ARM::LDRH:
				1749	case ARM::LDRH_PRE:
				1750	case ARM::LDRH_POST:
				1751	case ARM::LDRSH:
				1752	case ARM::LDRSH_PRE:
				1753	case ARM::LDRSH_POST:
				1754	case ARM::LDRSB:
				1755	case ARM::LDRSB_PRE:
				1756	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1757	case ARM::LDRHTr:
				1758	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1759	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1760	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1761	break;
				1762	default:
				1763	break;
				1764	}
				1765	}
				1766
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1767	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1768	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1769
				1770	if (type) {
				1771	Inst.addOperand(MCOperand::CreateReg(0));
				1772	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1773	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1774	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1775	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1776	Inst.addOperand(MCOperand::CreateImm(U));
				1777	}
				1778
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1779	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1780	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1781
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1782	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1783	}
				1784
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1785	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1786	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1787	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1788
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1789	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1790	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1791
				1792	switch (mode) {
				1793	case 0:
				1794	mode = ARM_AM::da;
				1795	break;
				1796	case 1:
				1797	mode = ARM_AM::ia;
				1798	break;
				1799	case 2:
				1800	mode = ARM_AM::db;
				1801	break;
				1802	case 3:
				1803	mode = ARM_AM::ib;
				1804	break;
				1805	}
				1806
				1807	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1808	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1809	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1810
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1811	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1812	}
				1813
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1814	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1815	unsigned Insn,
				1816	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1817	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1818
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1819	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1820	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1821	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1822
				1823	if (pred == 0xF) {
				1824	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1825	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1826	Inst.setOpcode(ARM::RFEDA);
				1827	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1828	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1829	Inst.setOpcode(ARM::RFEDA_UPD);
				1830	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1831	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1832	Inst.setOpcode(ARM::RFEDB);
				1833	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1834	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1835	Inst.setOpcode(ARM::RFEDB_UPD);
				1836	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1837	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1838	Inst.setOpcode(ARM::RFEIA);
				1839	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1840	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1841	Inst.setOpcode(ARM::RFEIA_UPD);
				1842	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1843	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1844	Inst.setOpcode(ARM::RFEIB);
				1845	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1846	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1847	Inst.setOpcode(ARM::RFEIB_UPD);
				1848	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1849	case ARM::STMDA:
				1850	Inst.setOpcode(ARM::SRSDA);
				1851	break;
				1852	case ARM::STMDA_UPD:
				1853	Inst.setOpcode(ARM::SRSDA_UPD);
				1854	break;
				1855	case ARM::STMDB:
				1856	Inst.setOpcode(ARM::SRSDB);
				1857	break;
				1858	case ARM::STMDB_UPD:
				1859	Inst.setOpcode(ARM::SRSDB_UPD);
				1860	break;
				1861	case ARM::STMIA:
				1862	Inst.setOpcode(ARM::SRSIA);
				1863	break;
				1864	case ARM::STMIA_UPD:
				1865	Inst.setOpcode(ARM::SRSIA_UPD);
				1866	break;
				1867	case ARM::STMIB:
				1868	Inst.setOpcode(ARM::SRSIB);
				1869	break;
				1870	case ARM::STMIB_UPD:
				1871	Inst.setOpcode(ARM::SRSIB_UPD);
				1872	break;
				1873	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1874	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1875	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1876
				1877	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1878	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1879	Inst.addOperand(
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1880	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1881	return S;
				1882	}
				1883
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1884	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1885	}
				1886
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1887	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1888	return MCDisassembler::Fail;
				1889	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1890	return MCDisassembler::Fail; // Tied
				1891	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1892	return MCDisassembler::Fail;
				1893	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1894	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1895
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1896	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1897	}
				1898
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1899	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1900	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1901	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1902	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1903	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1904	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1905
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1906	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1907
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1908	// imod == '01' --> UNPREDICTABLE
				1909	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1910	// return failure here. The '01' imod value is unprintable, so there's
				1911	// nothing useful we could do even if we returned UNPREDICTABLE.
				1912
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1913	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1914
				1915	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1916	Inst.setOpcode(ARM::CPS3p);
				1917	Inst.addOperand(MCOperand::CreateImm(imod));
				1918	Inst.addOperand(MCOperand::CreateImm(iflags));
				1919	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1920	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1921	Inst.setOpcode(ARM::CPS2p);
				1922	Inst.addOperand(MCOperand::CreateImm(imod));
				1923	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1924	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1925	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1926	Inst.setOpcode(ARM::CPS1p);
				1927	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1928	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1929	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1930	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1931	Inst.setOpcode(ARM::CPS1p);
				1932	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1933	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1934	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1935
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1936	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1937	}
				1938
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1939	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1940	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1941	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1942	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1943	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1944	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1945
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1946	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1947
				1948	// imod == '01' --> UNPREDICTABLE
				1949	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1950	// return failure here. The '01' imod value is unprintable, so there's
				1951	// nothing useful we could do even if we returned UNPREDICTABLE.
				1952
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1953	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1954
				1955	if (imod && M) {
				1956	Inst.setOpcode(ARM::t2CPS3p);
				1957	Inst.addOperand(MCOperand::CreateImm(imod));
				1958	Inst.addOperand(MCOperand::CreateImm(iflags));
				1959	Inst.addOperand(MCOperand::CreateImm(mode));
				1960	} else if (imod && !M) {
				1961	Inst.setOpcode(ARM::t2CPS2p);
				1962	Inst.addOperand(MCOperand::CreateImm(imod));
				1963	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1964	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1965	} else if (!imod && M) {
				1966	Inst.setOpcode(ARM::t2CPS1p);
				1967	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1968	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1969	} else {
				1970	// imod == '00' && M == '0' --> UNPREDICTABLE
				1971	Inst.setOpcode(ARM::t2CPS1p);
				1972	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1973	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1974	}
				1975
				1976	return S;
				1977	}
				1978
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1979	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1980	uint64_t Address, const void *Decoder) {
				1981	DecodeStatus S = MCDisassembler::Success;
				1982
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1983	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1984	unsigned imm = 0;
				1985
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1986	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				1987	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				1988	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				1989	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1990
				1991	if (Inst.getOpcode() == ARM::t2MOVTi16)
				1992	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1993	return MCDisassembler::Fail;
				1994	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1995	return MCDisassembler::Fail;
				1996
				1997	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				1998	Inst.addOperand(MCOperand::CreateImm(imm));
				1999
				2000	return S;
				2001	}
				2002
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2003	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2004	uint64_t Address, const void *Decoder) {
				2005	DecodeStatus S = MCDisassembler::Success;
				2006
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2007	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2008	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2009	unsigned imm = 0;
				2010
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2011	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2012	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2013
				2014	if (Inst.getOpcode() == ARM::MOVTi16)
				2015	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2016	return MCDisassembler::Fail;
				2017	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2018	return MCDisassembler::Fail;
				2019
				2020	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2021	Inst.addOperand(MCOperand::CreateImm(imm));
				2022
				2023	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2024	return MCDisassembler::Fail;
				2025
				2026	return S;
				2027	}
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	2028
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2029	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2030	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2031	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2032
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2033	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2034	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2035	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2036	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2037	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2038
				2039	if (pred == 0xF)
				2040	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2041
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2042	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2043	return MCDisassembler::Fail;
				2044	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2045	return MCDisassembler::Fail;
				2046	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2047	return MCDisassembler::Fail;
				2048	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2049	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2050
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2051	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2052	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	2053
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2054	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2055	}
				2056
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2057	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2058	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2059	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2060
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2061	unsigned add = fieldFromInstruction(Val, 12, 1);
				2062	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2063	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2064
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2065	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2066	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2067
				2068	if (!add) imm *= -1;
				2069	if (imm == 0 && !add) imm = INT32_MIN;
				2070	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2071	if (Rn == 15)
				2072	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2073
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2074	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2075	}
				2076
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2077	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2078	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2079	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2080
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2081	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2082	unsigned U = fieldFromInstruction(Val, 8, 1);
				2083	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2084
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2085	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2086	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2087
				2088	if (U)
				2089	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2090	else
				2091	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2092
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2093	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2094	}
				2095
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2096	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2097	uint64_t Address, const void *Decoder) {
				2098	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2099	}
				2100
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2101	static DecodeStatus
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2102	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2103	uint64_t Address, const void *Decoder) {
Kevin Enderby	445ba85	2012-10-29 23:27:20 +0000	[diff] [blame]	2104	DecodeStatus Status = MCDisassembler::Success;
				2105
				2106	// Note the J1 and J2 values are from the encoded instruction. So here
				2107	// change them to I1 and I2 values via as documented:
				2108	// I1 = NOT(J1 EOR S);
				2109	// I2 = NOT(J2 EOR S);
				2110	// and build the imm32 with one trailing zero as documented:
				2111	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2112	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2113	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2114	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2115	unsigned I1 = !(J1 ^ S);
				2116	unsigned I2 = !(J2 ^ S);
				2117	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2118	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2119	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
				2120	int imm32 = SignExtend32<24>(tmp << 1);
				2121	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2122	true, 4, Inst, Decoder))
Kevin Enderby	445ba85	2012-10-29 23:27:20 +0000	[diff] [blame]	2123	Inst.addOperand(MCOperand::CreateImm(imm32));
				2124
				2125	return Status;
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2126	}
				2127
				2128	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2129	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2130	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2131	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2132
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2133	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2134	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2135
				2136	if (pred == 0xF) {
				2137	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2138	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2139	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2140	true, 4, Inst, Decoder))
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	2141	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2142	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2143	}
				2144
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2145	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2146	true, 4, Inst, Decoder))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2147	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2148	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2149	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2150
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2151	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2152	}
				2153
				2154
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2155	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2156	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2157	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2158
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2159	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2160	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2161
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2162	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2163	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2164	if (!align)
				2165	Inst.addOperand(MCOperand::CreateImm(0));
				2166	else
				2167	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2168
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2169	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2170	}
				2171
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2172	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2173	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2174	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2175
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2176	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2177	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2178	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2179	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2180	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2181	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2182
				2183	// First output register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2184	switch (Inst.getOpcode()) {
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2185	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2186	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2187	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2188	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2189	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2190	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2191	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2192	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2193	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2194	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2195	return MCDisassembler::Fail;
				2196	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2197	case ARM::VLD2b16:
				2198	case ARM::VLD2b32:
				2199	case ARM::VLD2b8:
				2200	case ARM::VLD2b16wb_fixed:
				2201	case ARM::VLD2b16wb_register:
				2202	case ARM::VLD2b32wb_fixed:
				2203	case ARM::VLD2b32wb_register:
				2204	case ARM::VLD2b8wb_fixed:
				2205	case ARM::VLD2b8wb_register:
				2206	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2207	return MCDisassembler::Fail;
				2208	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2209	default:
				2210	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2211	return MCDisassembler::Fail;
				2212	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2213
				2214	// Second output register
				2215	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2216	case ARM::VLD3d8:
				2217	case ARM::VLD3d16:
				2218	case ARM::VLD3d32:
				2219	case ARM::VLD3d8_UPD:
				2220	case ARM::VLD3d16_UPD:
				2221	case ARM::VLD3d32_UPD:
				2222	case ARM::VLD4d8:
				2223	case ARM::VLD4d16:
				2224	case ARM::VLD4d32:
				2225	case ARM::VLD4d8_UPD:
				2226	case ARM::VLD4d16_UPD:
				2227	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2228	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2229	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2230	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2231	case ARM::VLD3q8:
				2232	case ARM::VLD3q16:
				2233	case ARM::VLD3q32:
				2234	case ARM::VLD3q8_UPD:
				2235	case ARM::VLD3q16_UPD:
				2236	case ARM::VLD3q32_UPD:
				2237	case ARM::VLD4q8:
				2238	case ARM::VLD4q16:
				2239	case ARM::VLD4q32:
				2240	case ARM::VLD4q8_UPD:
				2241	case ARM::VLD4q16_UPD:
				2242	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2243	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2244	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2245	default:
				2246	break;
				2247	}
				2248
				2249	// Third output register
				2250	switch(Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2251	case ARM::VLD3d8:
				2252	case ARM::VLD3d16:
				2253	case ARM::VLD3d32:
				2254	case ARM::VLD3d8_UPD:
				2255	case ARM::VLD3d16_UPD:
				2256	case ARM::VLD3d32_UPD:
				2257	case ARM::VLD4d8:
				2258	case ARM::VLD4d16:
				2259	case ARM::VLD4d32:
				2260	case ARM::VLD4d8_UPD:
				2261	case ARM::VLD4d16_UPD:
				2262	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2263	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2264	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2265	break;
				2266	case ARM::VLD3q8:
				2267	case ARM::VLD3q16:
				2268	case ARM::VLD3q32:
				2269	case ARM::VLD3q8_UPD:
				2270	case ARM::VLD3q16_UPD:
				2271	case ARM::VLD3q32_UPD:
				2272	case ARM::VLD4q8:
				2273	case ARM::VLD4q16:
				2274	case ARM::VLD4q32:
				2275	case ARM::VLD4q8_UPD:
				2276	case ARM::VLD4q16_UPD:
				2277	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2278	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2279	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2280	break;
				2281	default:
				2282	break;
				2283	}
				2284
				2285	// Fourth output register
				2286	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2287	case ARM::VLD4d8:
				2288	case ARM::VLD4d16:
				2289	case ARM::VLD4d32:
				2290	case ARM::VLD4d8_UPD:
				2291	case ARM::VLD4d16_UPD:
				2292	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2293	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2294	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2295	break;
				2296	case ARM::VLD4q8:
				2297	case ARM::VLD4q16:
				2298	case ARM::VLD4q32:
				2299	case ARM::VLD4q8_UPD:
				2300	case ARM::VLD4q16_UPD:
				2301	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2302	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2303	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2304	break;
				2305	default:
				2306	break;
				2307	}
				2308
				2309	// Writeback operand
				2310	switch (Inst.getOpcode()) {
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2311	case ARM::VLD1d8wb_fixed:
				2312	case ARM::VLD1d16wb_fixed:
				2313	case ARM::VLD1d32wb_fixed:
				2314	case ARM::VLD1d64wb_fixed:
				2315	case ARM::VLD1d8wb_register:
				2316	case ARM::VLD1d16wb_register:
				2317	case ARM::VLD1d32wb_register:
				2318	case ARM::VLD1d64wb_register:
				2319	case ARM::VLD1q8wb_fixed:
				2320	case ARM::VLD1q16wb_fixed:
				2321	case ARM::VLD1q32wb_fixed:
				2322	case ARM::VLD1q64wb_fixed:
				2323	case ARM::VLD1q8wb_register:
				2324	case ARM::VLD1q16wb_register:
				2325	case ARM::VLD1q32wb_register:
				2326	case ARM::VLD1q64wb_register:
Jim Grosbach	5921675	2011-10-24 23:26:05 +0000	[diff] [blame]	2327	case ARM::VLD1d8Twb_fixed:
				2328	case ARM::VLD1d8Twb_register:
				2329	case ARM::VLD1d16Twb_fixed:
				2330	case ARM::VLD1d16Twb_register:
				2331	case ARM::VLD1d32Twb_fixed:
				2332	case ARM::VLD1d32Twb_register:
				2333	case ARM::VLD1d64Twb_fixed:
				2334	case ARM::VLD1d64Twb_register:
Jim Grosbach	399cdca	2011-10-25 00:14:01 +0000	[diff] [blame]	2335	case ARM::VLD1d8Qwb_fixed:
				2336	case ARM::VLD1d8Qwb_register:
				2337	case ARM::VLD1d16Qwb_fixed:
				2338	case ARM::VLD1d16Qwb_register:
				2339	case ARM::VLD1d32Qwb_fixed:
				2340	case ARM::VLD1d32Qwb_register:
				2341	case ARM::VLD1d64Qwb_fixed:
				2342	case ARM::VLD1d64Qwb_register:
Jim Grosbach	a4e3c7f	2011-12-09 21:28:25 +0000	[diff] [blame]	2343	case ARM::VLD2d8wb_fixed:
				2344	case ARM::VLD2d16wb_fixed:
				2345	case ARM::VLD2d32wb_fixed:
				2346	case ARM::VLD2q8wb_fixed:
				2347	case ARM::VLD2q16wb_fixed:
				2348	case ARM::VLD2q32wb_fixed:
				2349	case ARM::VLD2d8wb_register:
				2350	case ARM::VLD2d16wb_register:
				2351	case ARM::VLD2d32wb_register:
				2352	case ARM::VLD2q8wb_register:
				2353	case ARM::VLD2q16wb_register:
				2354	case ARM::VLD2q32wb_register:
				2355	case ARM::VLD2b8wb_fixed:
				2356	case ARM::VLD2b16wb_fixed:
				2357	case ARM::VLD2b32wb_fixed:
				2358	case ARM::VLD2b8wb_register:
				2359	case ARM::VLD2b16wb_register:
				2360	case ARM::VLD2b32wb_register:
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2361	Inst.addOperand(MCOperand::CreateImm(0));
				2362	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2363	case ARM::VLD3d8_UPD:
				2364	case ARM::VLD3d16_UPD:
				2365	case ARM::VLD3d32_UPD:
				2366	case ARM::VLD3q8_UPD:
				2367	case ARM::VLD3q16_UPD:
				2368	case ARM::VLD3q32_UPD:
				2369	case ARM::VLD4d8_UPD:
				2370	case ARM::VLD4d16_UPD:
				2371	case ARM::VLD4d32_UPD:
				2372	case ARM::VLD4q8_UPD:
				2373	case ARM::VLD4q16_UPD:
				2374	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2375	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2376	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2377	break;
				2378	default:
				2379	break;
				2380	}
				2381
				2382	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2383	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2384	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2385
				2386	// AddrMode6 Offset (register)
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2387	switch (Inst.getOpcode()) {
				2388	default:
				2389	// The below have been updated to have explicit am6offset split
				2390	// between fixed and register offset. For those instructions not
				2391	// yet updated, we need to add an additional reg0 operand for the
				2392	// fixed variant.
				2393	//
				2394	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2395	if (Rm == 0xd) {
				2396	Inst.addOperand(MCOperand::CreateReg(0));
				2397	break;
				2398	}
				2399	// Fall through to handle the register offset variant.
				2400	case ARM::VLD1d8wb_fixed:
				2401	case ARM::VLD1d16wb_fixed:
				2402	case ARM::VLD1d32wb_fixed:
				2403	case ARM::VLD1d64wb_fixed:
Owen Anderson	04b12a4	2011-10-27 22:53:10 +0000	[diff] [blame]	2404	case ARM::VLD1d8Twb_fixed:
				2405	case ARM::VLD1d16Twb_fixed:
				2406	case ARM::VLD1d32Twb_fixed:
				2407	case ARM::VLD1d64Twb_fixed:
Owen Anderson	fb6ab2b	2011-10-31 17:17:32 +0000	[diff] [blame]	2408	case ARM::VLD1d8Qwb_fixed:
				2409	case ARM::VLD1d16Qwb_fixed:
				2410	case ARM::VLD1d32Qwb_fixed:
				2411	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2412	case ARM::VLD1d8wb_register:
				2413	case ARM::VLD1d16wb_register:
				2414	case ARM::VLD1d32wb_register:
				2415	case ARM::VLD1d64wb_register:
				2416	case ARM::VLD1q8wb_fixed:
				2417	case ARM::VLD1q16wb_fixed:
				2418	case ARM::VLD1q32wb_fixed:
				2419	case ARM::VLD1q64wb_fixed:
				2420	case ARM::VLD1q8wb_register:
				2421	case ARM::VLD1q16wb_register:
				2422	case ARM::VLD1q32wb_register:
				2423	case ARM::VLD1q64wb_register:
				2424	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2425	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2426	// increment and we need to add the register operand to the instruction.
				2427	if (Rm != 0xD && Rm != 0xF &&
				2428	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2429	return MCDisassembler::Fail;
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2430	break;
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2431	case ARM::VLD2d8wb_fixed:
				2432	case ARM::VLD2d16wb_fixed:
				2433	case ARM::VLD2d32wb_fixed:
				2434	case ARM::VLD2b8wb_fixed:
				2435	case ARM::VLD2b16wb_fixed:
				2436	case ARM::VLD2b32wb_fixed:
				2437	case ARM::VLD2q8wb_fixed:
				2438	case ARM::VLD2q16wb_fixed:
				2439	case ARM::VLD2q32wb_fixed:
				2440	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2441	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2442
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2443	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2444	}
				2445
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2446	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2447	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2448	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2449
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2450	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2451	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2452	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2453	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2454	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2455	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2456
				2457	// Writeback Operand
				2458	switch (Inst.getOpcode()) {
Jim Grosbach	4334e03	2011-10-31 21:50:31 +0000	[diff] [blame]	2459	case ARM::VST1d8wb_fixed:
				2460	case ARM::VST1d16wb_fixed:
				2461	case ARM::VST1d32wb_fixed:
				2462	case ARM::VST1d64wb_fixed:
				2463	case ARM::VST1d8wb_register:
				2464	case ARM::VST1d16wb_register:
				2465	case ARM::VST1d32wb_register:
				2466	case ARM::VST1d64wb_register:
				2467	case ARM::VST1q8wb_fixed:
				2468	case ARM::VST1q16wb_fixed:
				2469	case ARM::VST1q32wb_fixed:
				2470	case ARM::VST1q64wb_fixed:
				2471	case ARM::VST1q8wb_register:
				2472	case ARM::VST1q16wb_register:
				2473	case ARM::VST1q32wb_register:
				2474	case ARM::VST1q64wb_register:
Jim Grosbach	d5ca201	2011-11-29 22:38:04 +0000	[diff] [blame]	2475	case ARM::VST1d8Twb_fixed:
				2476	case ARM::VST1d16Twb_fixed:
				2477	case ARM::VST1d32Twb_fixed:
				2478	case ARM::VST1d64Twb_fixed:
				2479	case ARM::VST1d8Twb_register:
				2480	case ARM::VST1d16Twb_register:
				2481	case ARM::VST1d32Twb_register:
				2482	case ARM::VST1d64Twb_register:
Jim Grosbach	4c7edb3	2011-11-29 22:58:48 +0000	[diff] [blame]	2483	case ARM::VST1d8Qwb_fixed:
				2484	case ARM::VST1d16Qwb_fixed:
				2485	case ARM::VST1d32Qwb_fixed:
				2486	case ARM::VST1d64Qwb_fixed:
				2487	case ARM::VST1d8Qwb_register:
				2488	case ARM::VST1d16Qwb_register:
				2489	case ARM::VST1d32Qwb_register:
				2490	case ARM::VST1d64Qwb_register:
Jim Grosbach	bb3a2e4	2011-12-14 21:32:11 +0000	[diff] [blame]	2491	case ARM::VST2d8wb_fixed:
				2492	case ARM::VST2d16wb_fixed:
				2493	case ARM::VST2d32wb_fixed:
				2494	case ARM::VST2d8wb_register:
				2495	case ARM::VST2d16wb_register:
				2496	case ARM::VST2d32wb_register:
				2497	case ARM::VST2q8wb_fixed:
				2498	case ARM::VST2q16wb_fixed:
				2499	case ARM::VST2q32wb_fixed:
				2500	case ARM::VST2q8wb_register:
				2501	case ARM::VST2q16wb_register:
				2502	case ARM::VST2q32wb_register:
				2503	case ARM::VST2b8wb_fixed:
				2504	case ARM::VST2b16wb_fixed:
				2505	case ARM::VST2b32wb_fixed:
				2506	case ARM::VST2b8wb_register:
				2507	case ARM::VST2b16wb_register:
				2508	case ARM::VST2b32wb_register:
Kevin Enderby	b318cc1	2012-04-11 22:40:17 +0000	[diff] [blame]	2509	if (Rm == 0xF)
				2510	return MCDisassembler::Fail;
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2511	Inst.addOperand(MCOperand::CreateImm(0));
				2512	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2513	case ARM::VST3d8_UPD:
				2514	case ARM::VST3d16_UPD:
				2515	case ARM::VST3d32_UPD:
				2516	case ARM::VST3q8_UPD:
				2517	case ARM::VST3q16_UPD:
				2518	case ARM::VST3q32_UPD:
				2519	case ARM::VST4d8_UPD:
				2520	case ARM::VST4d16_UPD:
				2521	case ARM::VST4d32_UPD:
				2522	case ARM::VST4q8_UPD:
				2523	case ARM::VST4q16_UPD:
				2524	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2525	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2526	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2527	break;
				2528	default:
				2529	break;
				2530	}
				2531
				2532	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2533	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2534	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2535
				2536	// AddrMode6 Offset (register)
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2537	switch (Inst.getOpcode()) {
				2538	default:
				2539	if (Rm == 0xD)
				2540	Inst.addOperand(MCOperand::CreateReg(0));
				2541	else if (Rm != 0xF) {
				2542	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2543	return MCDisassembler::Fail;
				2544	}
				2545	break;
				2546	case ARM::VST1d8wb_fixed:
				2547	case ARM::VST1d16wb_fixed:
				2548	case ARM::VST1d32wb_fixed:
				2549	case ARM::VST1d64wb_fixed:
				2550	case ARM::VST1q8wb_fixed:
				2551	case ARM::VST1q16wb_fixed:
				2552	case ARM::VST1q32wb_fixed:
				2553	case ARM::VST1q64wb_fixed:
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2554	case ARM::VST1d8Twb_fixed:
				2555	case ARM::VST1d16Twb_fixed:
				2556	case ARM::VST1d32Twb_fixed:
				2557	case ARM::VST1d64Twb_fixed:
				2558	case ARM::VST1d8Qwb_fixed:
				2559	case ARM::VST1d16Qwb_fixed:
				2560	case ARM::VST1d32Qwb_fixed:
				2561	case ARM::VST1d64Qwb_fixed:
				2562	case ARM::VST2d8wb_fixed:
				2563	case ARM::VST2d16wb_fixed:
				2564	case ARM::VST2d32wb_fixed:
				2565	case ARM::VST2q8wb_fixed:
				2566	case ARM::VST2q16wb_fixed:
				2567	case ARM::VST2q32wb_fixed:
				2568	case ARM::VST2b8wb_fixed:
				2569	case ARM::VST2b16wb_fixed:
				2570	case ARM::VST2b32wb_fixed:
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2571	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2572	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2573
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2574
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2575	// First input register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2576	switch (Inst.getOpcode()) {
				2577	case ARM::VST1q16:
				2578	case ARM::VST1q32:
				2579	case ARM::VST1q64:
				2580	case ARM::VST1q8:
				2581	case ARM::VST1q16wb_fixed:
				2582	case ARM::VST1q16wb_register:
				2583	case ARM::VST1q32wb_fixed:
				2584	case ARM::VST1q32wb_register:
				2585	case ARM::VST1q64wb_fixed:
				2586	case ARM::VST1q64wb_register:
				2587	case ARM::VST1q8wb_fixed:
				2588	case ARM::VST1q8wb_register:
				2589	case ARM::VST2d16:
				2590	case ARM::VST2d32:
				2591	case ARM::VST2d8:
				2592	case ARM::VST2d16wb_fixed:
				2593	case ARM::VST2d16wb_register:
				2594	case ARM::VST2d32wb_fixed:
				2595	case ARM::VST2d32wb_register:
				2596	case ARM::VST2d8wb_fixed:
				2597	case ARM::VST2d8wb_register:
				2598	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2599	return MCDisassembler::Fail;
				2600	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2601	case ARM::VST2b16:
				2602	case ARM::VST2b32:
				2603	case ARM::VST2b8:
				2604	case ARM::VST2b16wb_fixed:
				2605	case ARM::VST2b16wb_register:
				2606	case ARM::VST2b32wb_fixed:
				2607	case ARM::VST2b32wb_register:
				2608	case ARM::VST2b8wb_fixed:
				2609	case ARM::VST2b8wb_register:
				2610	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2611	return MCDisassembler::Fail;
				2612	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2613	default:
				2614	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2615	return MCDisassembler::Fail;
				2616	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2617
				2618	// Second input register
				2619	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2620	case ARM::VST3d8:
				2621	case ARM::VST3d16:
				2622	case ARM::VST3d32:
				2623	case ARM::VST3d8_UPD:
				2624	case ARM::VST3d16_UPD:
				2625	case ARM::VST3d32_UPD:
				2626	case ARM::VST4d8:
				2627	case ARM::VST4d16:
				2628	case ARM::VST4d32:
				2629	case ARM::VST4d8_UPD:
				2630	case ARM::VST4d16_UPD:
				2631	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2632	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2633	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2634	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2635	case ARM::VST3q8:
				2636	case ARM::VST3q16:
				2637	case ARM::VST3q32:
				2638	case ARM::VST3q8_UPD:
				2639	case ARM::VST3q16_UPD:
				2640	case ARM::VST3q32_UPD:
				2641	case ARM::VST4q8:
				2642	case ARM::VST4q16:
				2643	case ARM::VST4q32:
				2644	case ARM::VST4q8_UPD:
				2645	case ARM::VST4q16_UPD:
				2646	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2647	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2648	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2649	break;
				2650	default:
				2651	break;
				2652	}
				2653
				2654	// Third input register
				2655	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2656	case ARM::VST3d8:
				2657	case ARM::VST3d16:
				2658	case ARM::VST3d32:
				2659	case ARM::VST3d8_UPD:
				2660	case ARM::VST3d16_UPD:
				2661	case ARM::VST3d32_UPD:
				2662	case ARM::VST4d8:
				2663	case ARM::VST4d16:
				2664	case ARM::VST4d32:
				2665	case ARM::VST4d8_UPD:
				2666	case ARM::VST4d16_UPD:
				2667	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2668	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2669	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2670	break;
				2671	case ARM::VST3q8:
				2672	case ARM::VST3q16:
				2673	case ARM::VST3q32:
				2674	case ARM::VST3q8_UPD:
				2675	case ARM::VST3q16_UPD:
				2676	case ARM::VST3q32_UPD:
				2677	case ARM::VST4q8:
				2678	case ARM::VST4q16:
				2679	case ARM::VST4q32:
				2680	case ARM::VST4q8_UPD:
				2681	case ARM::VST4q16_UPD:
				2682	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2683	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2684	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2685	break;
				2686	default:
				2687	break;
				2688	}
				2689
				2690	// Fourth input register
				2691	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2692	case ARM::VST4d8:
				2693	case ARM::VST4d16:
				2694	case ARM::VST4d32:
				2695	case ARM::VST4d8_UPD:
				2696	case ARM::VST4d16_UPD:
				2697	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2698	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2699	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2700	break;
				2701	case ARM::VST4q8:
				2702	case ARM::VST4q16:
				2703	case ARM::VST4q32:
				2704	case ARM::VST4q8_UPD:
				2705	case ARM::VST4q16_UPD:
				2706	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2707	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2708	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2709	break;
				2710	default:
				2711	break;
				2712	}
				2713
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2714	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2715	}
				2716
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2717	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2718	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2719	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2720
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2721	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2722	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2723	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2724	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2725	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2726	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2727
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2728	if (size == 0 && align == 1)
				2729	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2730	align *= (1 << size);
				2731
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2732	switch (Inst.getOpcode()) {
				2733	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2734	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2735	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2736	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2737	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2738	return MCDisassembler::Fail;
				2739	break;
				2740	default:
				2741	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2742	return MCDisassembler::Fail;
				2743	break;
				2744	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2745	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2746	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2747	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2748	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2749
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2750	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2751	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2752	Inst.addOperand(MCOperand::CreateImm(align));
				2753
Jim Grosbach	096334e	2011-11-30 19:35:44 +0000	[diff] [blame]	2754	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2755	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2756	// increment and we need to add the register operand to the instruction.
				2757	if (Rm != 0xD && Rm != 0xF &&
				2758	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2759	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2760
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2761	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2762	}
				2763
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2764	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2765	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2766	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2767
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2768	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2769	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2770	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2771	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2772	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2773	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2774	align = 2size;
				2775
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2776	switch (Inst.getOpcode()) {
				2777	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2778	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2779	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2780	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2781	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2782	return MCDisassembler::Fail;
				2783	break;
Jim Grosbach	4d0983a	2012-03-06 23:10:38 +0000	[diff] [blame]	2784	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2785	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2786	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2787	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2788	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2789	return MCDisassembler::Fail;
				2790	break;
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2791	default:
				2792	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2793	return MCDisassembler::Fail;
				2794	break;
				2795	}
Kevin Enderby	158c8a4	2012-03-06 18:33:12 +0000	[diff] [blame]	2796
				2797	if (Rm != 0xF)
				2798	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2799
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2801	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2802	Inst.addOperand(MCOperand::CreateImm(align));
				2803
Kevin Enderby	c5a2a33	2012-04-17 00:49:27 +0000	[diff] [blame]	2804	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2806	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2807	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2808
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2809	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	}
				2811
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2812	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2813	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2814	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2815
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2816	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2817	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2818	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2819	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2820	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2821
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2822	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2823	return MCDisassembler::Fail;
				2824	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2825	return MCDisassembler::Fail;
				2826	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2827	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2828	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2829	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2830	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2831	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2832
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2833	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2834	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2835	Inst.addOperand(MCOperand::CreateImm(0));
				2836
				2837	if (Rm == 0xD)
				2838	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2839	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2840	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2841	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2842	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2843
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2844	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2845	}
				2846
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2847	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2848	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2849	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2850
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2851	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2852	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2853	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2854	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2855	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2856	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2857	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2858
				2859	if (size == 0x3) {
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2860	if (align == 0)
				2861	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2862	size = 4;
				2863	align = 16;
				2864	} else {
				2865	if (size == 2) {
				2866	size = 1 << size;
				2867	align *= 8;
				2868	} else {
				2869	size = 1 << size;
				2870	align = 4size;
				2871	}
				2872	}
				2873
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2874	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2875	return MCDisassembler::Fail;
				2876	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2877	return MCDisassembler::Fail;
				2878	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2879	return MCDisassembler::Fail;
				2880	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2881	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2882	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2883	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2884	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2885	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2886
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2887	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2888	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2889	Inst.addOperand(MCOperand::CreateImm(align));
				2890
				2891	if (Rm == 0xD)
				2892	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2893	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2894	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2895	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2896	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2897
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2898	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2899	}
				2900
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2901	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2902	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2903	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2904	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2905
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2906	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2907	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2908	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2909	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2910	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2911	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2912	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2913	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2914
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2915	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2916	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2917	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2918	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2919	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2920	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2921	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2922
				2923	Inst.addOperand(MCOperand::CreateImm(imm));
				2924
				2925	switch (Inst.getOpcode()) {
				2926	case ARM::VORRiv4i16:
				2927	case ARM::VORRiv2i32:
				2928	case ARM::VBICiv4i16:
				2929	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2930	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2931	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2932	break;
				2933	case ARM::VORRiv8i16:
				2934	case ARM::VORRiv4i32:
				2935	case ARM::VBICiv8i16:
				2936	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2937	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2938	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2939	break;
				2940	default:
				2941	break;
				2942	}
				2943
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2944	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2945	}
				2946
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2947	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2948	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2949	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2950
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2951	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2952	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2953	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2954	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2955	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2956
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2957	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2958	return MCDisassembler::Fail;
				2959	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2960	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2961	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2962
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2963	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2964	}
				2965
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2966	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2967	uint64_t Address, const void *Decoder) {
				2968	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2969	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2970	}
				2971
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2972	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2973	uint64_t Address, const void *Decoder) {
				2974	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2975	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2976	}
				2977
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2978	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2979	uint64_t Address, const void *Decoder) {
				2980	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2981	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2982	}
				2983
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2984	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2985	uint64_t Address, const void *Decoder) {
				2986	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2987	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2988	}
				2989
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2990	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2991	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2992	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2993
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2994	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2995	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2996	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2997	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				2998	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2999	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3000	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3001
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3002	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3003	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	3004	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3005	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3006	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	3007	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3008
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	3009	switch (Inst.getOpcode()) {
				3010	case ARM::VTBL2:
				3011	case ARM::VTBX2:
				3012	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3013	return MCDisassembler::Fail;
				3014	break;
				3015	default:
				3016	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3017	return MCDisassembler::Fail;
				3018	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3019
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3020	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3021	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3022
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3023	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3024	}
				3025
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3026	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3027	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3028	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3029
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3030	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3031	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3032
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3033	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3034	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3035
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3036	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	3037	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3038	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3039	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	3040	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3041	case ARM::tADDrSPi:
				3042	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3043	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3044	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3045
				3046	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3047	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3048	}
				3049
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3050	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3051	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3052	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3053	true, 2, Inst, Decoder))
				3054	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3055	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3056	}
				3057
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3058	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3059	uint64_t Address, const void *Decoder) {
Kevin Enderby	3610a15	2012-05-04 22:09:52 +0000	[diff] [blame]	3060	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3061	true, 4, Inst, Decoder))
				3062	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3063	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3064	}
				3065
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3066	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3067	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3068	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
				3069	true, 2, Inst, Decoder))
				3070	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3071	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3072	}
				3073
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3074	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3075	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3076	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3077
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3078	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3079	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3080
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3081	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3082	return MCDisassembler::Fail;
				3083	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3084	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3085
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3086	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3087	}
				3088
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3089	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3090	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3091	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3092
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3093	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3094	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3095
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3096	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3097	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	Inst.addOperand(MCOperand::CreateImm(imm));
				3099
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3100	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3101	}
				3102
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3103	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3104	uint64_t Address, const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3105	unsigned imm = Val << 2;
				3106
				3107	Inst.addOperand(MCOperand::CreateImm(imm));
				3108	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3109
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3110	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3111	}
				3112
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3113	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3114	uint64_t Address, const void *Decoder) {
				3115	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	3116	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3117
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3118	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3119	}
				3120
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3121	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3122	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3123	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3124
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3125	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3126	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3127	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3128
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3129	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3130	return MCDisassembler::Fail;
				3131	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3132	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	Inst.addOperand(MCOperand::CreateImm(imm));
				3134
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3135	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3136	}
				3137
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3138	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3139	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3140	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3141
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3142	switch (Inst.getOpcode()) {
				3143	case ARM::t2PLDs:
				3144	case ARM::t2PLDWs:
				3145	case ARM::t2PLIs:
				3146	break;
				3147	default: {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3148	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson	31d485e	2011-09-23 21:07:25 +0000	[diff] [blame]	3149	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3150	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3151	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3152	}
				3153
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3154	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3155	if (Rn == 0xF) {
				3156	switch (Inst.getOpcode()) {
				3157	case ARM::t2LDRBs:
				3158	Inst.setOpcode(ARM::t2LDRBpci);
				3159	break;
				3160	case ARM::t2LDRHs:
				3161	Inst.setOpcode(ARM::t2LDRHpci);
				3162	break;
				3163	case ARM::t2LDRSHs:
				3164	Inst.setOpcode(ARM::t2LDRSHpci);
				3165	break;
				3166	case ARM::t2LDRSBs:
				3167	Inst.setOpcode(ARM::t2LDRSBpci);
				3168	break;
				3169	case ARM::t2PLDs:
				3170	Inst.setOpcode(ARM::t2PLDi12);
				3171	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				3172	break;
				3173	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3174	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3175	}
				3176
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3177	int imm = fieldFromInstruction(Insn, 0, 12);
				3178	if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3179	Inst.addOperand(MCOperand::CreateImm(imm));
				3180
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3181	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3182	}
				3183
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3184	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3185	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3186	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3187	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3188	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3189
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3190	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3191	}
				3192
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3193	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3194	uint64_t Address, const void *Decoder) {
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3195	if (Val == 0)
				3196	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3197	else {
				3198	int imm = Val & 0xFF;
				3199
				3200	if (!(Val & 0x100)) imm *= -1;
Richard Smith	1144af3	2012-08-24 23:29:28 +0000	[diff] [blame]	3201	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3202	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3203
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3204	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3205	}
				3206
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3207	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3208	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3209	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3210
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3211	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3212	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3213
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3214	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3215	return MCDisassembler::Fail;
				3216	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3217	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3218
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3219	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3220	}
				3221
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3222	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3223	uint64_t Address, const void *Decoder) {
				3224	DecodeStatus S = MCDisassembler::Success;
				3225
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3226	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3227	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3228
				3229	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3230	return MCDisassembler::Fail;
				3231
				3232	Inst.addOperand(MCOperand::CreateImm(imm));
				3233
				3234	return S;
				3235	}
				3236
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3237	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3238	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3239	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame]	3240	if (Val == 0)
				3241	imm = INT32_MIN;
				3242	else if (!(Val & 0x100))
				3243	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3244	Inst.addOperand(MCOperand::CreateImm(imm));
				3245
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3246	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3247	}
				3248
				3249
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3250	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3251	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3252	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3253
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3254	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3255	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3256
				3257	// Some instructions always use an additive offset.
				3258	switch (Inst.getOpcode()) {
				3259	case ARM::t2LDRT:
				3260	case ARM::t2LDRBT:
				3261	case ARM::t2LDRHT:
				3262	case ARM::t2LDRSBT:
				3263	case ARM::t2LDRSHT:
Owen Anderson	ecd1c55	2011-09-19 18:07:10 +0000	[diff] [blame]	3264	case ARM::t2STRT:
				3265	case ARM::t2STRBT:
				3266	case ARM::t2STRHT:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3267	imm \|= 0x100;
				3268	break;
				3269	default:
				3270	break;
				3271	}
				3272
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3273	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3274	return MCDisassembler::Fail;
				3275	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3276	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3277
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3278	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3279	}
				3280
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3281	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3282	uint64_t Address, const void *Decoder) {
				3283	DecodeStatus S = MCDisassembler::Success;
				3284
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3285	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3286	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3287	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3288	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3289	addr \|= Rn << 9;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3290	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3291
				3292	if (!load) {
				3293	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3294	return MCDisassembler::Fail;
				3295	}
				3296
Owen Anderson	e4f2df9	2011-09-16 22:42:36 +0000	[diff] [blame]	3297	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3298	return MCDisassembler::Fail;
				3299
				3300	if (load) {
				3301	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3302	return MCDisassembler::Fail;
				3303	}
				3304
				3305	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3306	return MCDisassembler::Fail;
				3307
				3308	return S;
				3309	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3310
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3311	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3312	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3313	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3314
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3315	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3316	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3317
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3318	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3319	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3320	Inst.addOperand(MCOperand::CreateImm(imm));
				3321
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3322	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3323	}
				3324
				3325
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3326	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3327	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3328	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3329
				3330	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3331	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3332	Inst.addOperand(MCOperand::CreateImm(imm));
				3333
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3334	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3335	}
				3336
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3337	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3338	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3339	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3340
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3341	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3342	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3343	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3344
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3345	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3346	return MCDisassembler::Fail;
Jim Grosbach	bb32f1d	2012-04-27 23:51:33 +0000	[diff] [blame]	3347	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3348	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3349	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3350	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3351	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3352
				3353	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3354	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3355	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3356	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3357	}
				3358
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3359	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3360	}
				3361
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3362	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3363	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3364	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3365	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3366
				3367	Inst.addOperand(MCOperand::CreateImm(imod));
				3368	Inst.addOperand(MCOperand::CreateImm(flags));
				3369
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3370	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3371	}
				3372
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3373	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3374	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3375	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3376	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3377	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3378
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	3379	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3380	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3381	Inst.addOperand(MCOperand::CreateImm(add));
				3382
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3383	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3384	}
				3385
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3386	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3387	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3388	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3389	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3390	// the encoded instruction. So here change to I1 and I2 values via:
				3391	// I1 = NOT(J1 EOR S);
				3392	// I2 = NOT(J2 EOR S);
				3393	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3394	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3395	unsigned S = (Val >> 23) & 1;
				3396	unsigned J1 = (Val >> 22) & 1;
				3397	unsigned J2 = (Val >> 21) & 1;
				3398	unsigned I1 = !(J1 ^ S);
				3399	unsigned I2 = !(J2 ^ S);
				3400	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3401	int imm32 = SignExtend32<25>(tmp << 1);
				3402
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	3403	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3404	(Address & ~2u) + imm32 + 4,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3405	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3406	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3407	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3408	}
				3409
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3410	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3411	uint64_t Address, const void *Decoder) {
				3412	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3413	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3414
				3415	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3416	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3417	}
				3418
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3419	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3420	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3421	uint64_t Address, const void *Decoder) {
				3422	DecodeStatus S = MCDisassembler::Success;
				3423
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3424	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3425	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3426
				3427	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3428	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3429	return MCDisassembler::Fail;
				3430	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3431	return MCDisassembler::Fail;
				3432	return S;
				3433	}
				3434
				3435	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3436	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3437	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3438	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3439
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3440	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3441	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3442	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3443	switch (opc) {
				3444	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3445	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3446	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3447	Inst.setOpcode(ARM::t2DSB);
				3448	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3449	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3450	Inst.setOpcode(ARM::t2DMB);
				3451	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3452	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3453	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	3454	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3455	}
				3456
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3457	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3458	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3459	}
				3460
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3461	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3462	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3463	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3464	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3465	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3466
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3467	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3468	return MCDisassembler::Fail;
				3469	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3470	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3471
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3472	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3473	}
				3474
				3475	// Decode a shifted immediate operand. These basically consist
				3476	// of an 8-bit value, and a 4-bit directive that specifies either
				3477	// a splat operation or a rotation.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3478	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3479	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3480	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3481	if (ctrl == 0) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3482	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3483	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3484	switch (byte) {
				3485	case 0:
				3486	Inst.addOperand(MCOperand::CreateImm(imm));
				3487	break;
				3488	case 1:
				3489	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3490	break;
				3491	case 2:
				3492	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3493	break;
				3494	case 3:
				3495	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3496	(imm << 8) \| imm));
				3497	break;
				3498	}
				3499	} else {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3500	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3501	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3502	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3503	Inst.addOperand(MCOperand::CreateImm(imm));
				3504	}
				3505
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3506	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3507	}
				3508
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3509	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3510	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3511	uint64_t Address, const void *Decoder){
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3512	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3513	true, 2, Inst, Decoder))
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3514	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3515	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3516	}
				3517
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3518	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3519	uint64_t Address, const void *Decoder){
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3520	// Val is passed in as S:J1:J2:imm10:imm11
				3521	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3522	// the encoded instruction. So here change to I1 and I2 values via:
				3523	// I1 = NOT(J1 EOR S);
				3524	// I2 = NOT(J2 EOR S);
				3525	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3526	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3527	unsigned S = (Val >> 23) & 1;
				3528	unsigned J1 = (Val >> 22) & 1;
				3529	unsigned J2 = (Val >> 21) & 1;
				3530	unsigned I1 = !(J1 ^ S);
				3531	unsigned I2 = !(J2 ^ S);
				3532	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3533	int imm32 = SignExtend32<25>(tmp << 1);
				3534
				3535	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	3536	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3537	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3538	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3539	}
				3540
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3541	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3542	uint64_t Address, const void *Decoder) {
Jiangning Liu	c1b7ca5	2012-08-02 08:21:27 +0000	[diff] [blame]	3543	if (Val & ~0xf)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3544	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3545
				3546	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3547	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3548	}
				3549
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3550	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3551	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3552	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3553	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3554	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3555	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3556
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3557	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3558	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3559	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3560
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3561	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3562	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3563	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3564
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3565	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3566
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3567	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3568	return MCDisassembler::Fail;
				3569	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3570	return MCDisassembler::Fail;
				3571	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3572	return MCDisassembler::Fail;
				3573	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3574	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3575
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3576	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3577	}
				3578
				3579
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3580	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3581	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3582	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3583
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3584	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3585	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3586	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3587	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3588
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3589	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				3590	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3591
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3592	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3593	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3594
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3595	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3596	return MCDisassembler::Fail;
				3597	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3598	return MCDisassembler::Fail;
				3599	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3600	return MCDisassembler::Fail;
				3601	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3602	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3603
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3604	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3605	}
				3606
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3607	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3608	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3609	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3610
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3611	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3612	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3613	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3614	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3615	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3616	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3617
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3618	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3619
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3620	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3621	return MCDisassembler::Fail;
				3622	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3623	return MCDisassembler::Fail;
				3624	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3625	return MCDisassembler::Fail;
				3626	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3627	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3628
				3629	return S;
				3630	}
				3631
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3632	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3633	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3634	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3635
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3636	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3637	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3638	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3639	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3640	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3641	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				3642	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3643
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3644	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3645	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3646
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3647	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3648	return MCDisassembler::Fail;
				3649	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3650	return MCDisassembler::Fail;
				3651	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3652	return MCDisassembler::Fail;
				3653	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3654	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3655
				3656	return S;
				3657	}
				3658
				3659
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3660	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3661	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3662	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3663
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3664	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3665	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3666	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3667	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3668	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3669	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3670
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3671	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3672
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3673	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3674	return MCDisassembler::Fail;
				3675	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3676	return MCDisassembler::Fail;
				3677	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3678	return MCDisassembler::Fail;
				3679	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3680	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3681
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3682	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3683	}
				3684
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3685	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3686	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3687	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3688
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3689	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3690	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3691	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3692	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3693	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3694	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3695
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3696	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3697
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3698	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3699	return MCDisassembler::Fail;
				3700	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3701	return MCDisassembler::Fail;
				3702	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3703	return MCDisassembler::Fail;
				3704	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3705	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3706
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3707	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3708	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3709
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3710	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3711	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3712	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3713
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3714	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3715	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3716	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3717	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3718	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3719
				3720	unsigned align = 0;
				3721	unsigned index = 0;
				3722	switch (size) {
				3723	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3724	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3725	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3726	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3727	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3728	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3729	break;
				3730	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3731	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3732	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3733	index = fieldFromInstruction(Insn, 6, 2);
				3734	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3735	align = 2;
				3736	break;
				3737	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3738	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3739	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3740	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3741
				3742	switch (fieldFromInstruction(Insn, 4, 2)) {
				3743	case 0 :
				3744	align = 0; break;
				3745	case 3:
				3746	align = 4; break;
				3747	default:
				3748	return MCDisassembler::Fail;
				3749	}
				3750	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3751	}
				3752
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3753	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3754	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3755	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3756	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3757	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3758	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3759	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3760	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3761	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3762	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3763	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3764	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3765	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3766	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3767	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3768	}
				3769
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3770	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3771	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3772	Inst.addOperand(MCOperand::CreateImm(index));
				3773
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3774	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3775	}
				3776
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3777	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3778	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3779	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3780
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3781	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3782	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3783	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3784	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3785	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3786
				3787	unsigned align = 0;
				3788	unsigned index = 0;
				3789	switch (size) {
				3790	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3791	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3792	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3793	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3794	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3795	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3796	break;
				3797	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3798	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3799	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3800	index = fieldFromInstruction(Insn, 6, 2);
				3801	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3802	align = 2;
				3803	break;
				3804	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3805	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3806	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3807	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3808
				3809	switch (fieldFromInstruction(Insn, 4, 2)) {
				3810	case 0:
				3811	align = 0; break;
				3812	case 3:
				3813	align = 4; break;
				3814	default:
				3815	return MCDisassembler::Fail;
				3816	}
				3817	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3818	}
				3819
				3820	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3821	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3822	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3823	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3824	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3825	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3826	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3827	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3828	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3829	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3830	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3831	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3832	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3833	}
				3834
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3835	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3836	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3837	Inst.addOperand(MCOperand::CreateImm(index));
				3838
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3839	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3840	}
				3841
				3842
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3843	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3844	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3845	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3846
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3847	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3848	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3849	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3850	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3851	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3852
				3853	unsigned align = 0;
				3854	unsigned index = 0;
				3855	unsigned inc = 1;
				3856	switch (size) {
				3857	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3858	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3859	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3860	index = fieldFromInstruction(Insn, 5, 3);
				3861	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3862	align = 2;
				3863	break;
				3864	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3865	index = fieldFromInstruction(Insn, 6, 2);
				3866	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3867	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3868	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3869	inc = 2;
				3870	break;
				3871	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3872	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3873	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3874	index = fieldFromInstruction(Insn, 7, 1);
				3875	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3876	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3877	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3878	inc = 2;
				3879	break;
				3880	}
				3881
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3882	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3883	return MCDisassembler::Fail;
				3884	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3885	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3886	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3887	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3888	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3889	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3890	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3891	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3892	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3893	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3894	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3895	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3896	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3897	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3898	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3899	}
				3900
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3901	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3902	return MCDisassembler::Fail;
				3903	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3904	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3905	Inst.addOperand(MCOperand::CreateImm(index));
				3906
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3907	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3908	}
				3909
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3910	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3911	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3912	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3913
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3914	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3915	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3916	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3917	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3918	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3919
				3920	unsigned align = 0;
				3921	unsigned index = 0;
				3922	unsigned inc = 1;
				3923	switch (size) {
				3924	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3925	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3926	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3927	index = fieldFromInstruction(Insn, 5, 3);
				3928	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3929	align = 2;
				3930	break;
				3931	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3932	index = fieldFromInstruction(Insn, 6, 2);
				3933	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3934	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3935	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3936	inc = 2;
				3937	break;
				3938	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3939	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3940	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3941	index = fieldFromInstruction(Insn, 7, 1);
				3942	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3943	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3944	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3945	inc = 2;
				3946	break;
				3947	}
				3948
				3949	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3950	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3951	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3952	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3953	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3954	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3955	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3956	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3957	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3958	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3959	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3960	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3961	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3962	}
				3963
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3964	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3965	return MCDisassembler::Fail;
				3966	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3967	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3968	Inst.addOperand(MCOperand::CreateImm(index));
				3969
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3970	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3971	}
				3972
				3973
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3974	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3975	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3976	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3977
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3978	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3979	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3980	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3981	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3982	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3983
				3984	unsigned align = 0;
				3985	unsigned index = 0;
				3986	unsigned inc = 1;
				3987	switch (size) {
				3988	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3989	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3990	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3991	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3992	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3993	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3994	break;
				3995	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3996	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3997	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3998	index = fieldFromInstruction(Insn, 6, 2);
				3999	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4000	inc = 2;
				4001	break;
				4002	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4003	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4004	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4005	index = fieldFromInstruction(Insn, 7, 1);
				4006	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4007	inc = 2;
				4008	break;
				4009	}
				4010
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4011	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4012	return MCDisassembler::Fail;
				4013	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4014	return MCDisassembler::Fail;
				4015	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4016	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4017
				4018	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4019	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4020	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4021	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4022	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4023	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4024	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4025	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4026	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4027	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4028	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4029	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4030	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4031	}
				4032
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4033	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4034	return MCDisassembler::Fail;
				4035	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4036	return MCDisassembler::Fail;
				4037	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4038	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4039	Inst.addOperand(MCOperand::CreateImm(index));
				4040
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4041	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4042	}
				4043
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4044	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4045	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4046	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4047
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4048	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4049	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4050	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4051	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4052	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4053
				4054	unsigned align = 0;
				4055	unsigned index = 0;
				4056	unsigned inc = 1;
				4057	switch (size) {
				4058	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4059	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4060	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4061	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4062	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4063	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4064	break;
				4065	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4066	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4067	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4068	index = fieldFromInstruction(Insn, 6, 2);
				4069	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4070	inc = 2;
				4071	break;
				4072	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4073	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4074	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4075	index = fieldFromInstruction(Insn, 7, 1);
				4076	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4077	inc = 2;
				4078	break;
				4079	}
				4080
				4081	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4082	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4083	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4084	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4085	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4086	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4087	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4088	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4089	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4090	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4091	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4092	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4093	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4094	}
				4095
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4096	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4097	return MCDisassembler::Fail;
				4098	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4099	return MCDisassembler::Fail;
				4100	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4101	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4102	Inst.addOperand(MCOperand::CreateImm(index));
				4103
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4104	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4105	}
				4106
				4107
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4108	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4109	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4110	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4111
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4112	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4113	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4114	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4115	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4116	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4117
				4118	unsigned align = 0;
				4119	unsigned index = 0;
				4120	unsigned inc = 1;
				4121	switch (size) {
				4122	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4123	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4124	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4125	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4126	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4127	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4128	break;
				4129	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4130	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4131	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4132	index = fieldFromInstruction(Insn, 6, 2);
				4133	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4134	inc = 2;
				4135	break;
				4136	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4137	switch (fieldFromInstruction(Insn, 4, 2)) {
				4138	case 0:
				4139	align = 0; break;
				4140	case 3:
				4141	return MCDisassembler::Fail;
				4142	default:
				4143	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4144	}
				4145
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4146	index = fieldFromInstruction(Insn, 7, 1);
				4147	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4148	inc = 2;
				4149	break;
				4150	}
				4151
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4152	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4153	return MCDisassembler::Fail;
				4154	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4155	return MCDisassembler::Fail;
				4156	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4157	return MCDisassembler::Fail;
				4158	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4159	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4160
				4161	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4162	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4163	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4164	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4165	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4166	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4167	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4168	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4169	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4170	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4171	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4172	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4173	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4174	}
				4175
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4176	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4177	return MCDisassembler::Fail;
				4178	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4179	return MCDisassembler::Fail;
				4180	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4181	return MCDisassembler::Fail;
				4182	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4183	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4184	Inst.addOperand(MCOperand::CreateImm(index));
				4185
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4186	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4187	}
				4188
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4189	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4190	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4191	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4192
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4193	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4194	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4195	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4196	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4197	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4198
				4199	unsigned align = 0;
				4200	unsigned index = 0;
				4201	unsigned inc = 1;
				4202	switch (size) {
				4203	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4204	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4205	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4206	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4207	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4208	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4209	break;
				4210	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4211	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4212	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4213	index = fieldFromInstruction(Insn, 6, 2);
				4214	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4215	inc = 2;
				4216	break;
				4217	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4218	switch (fieldFromInstruction(Insn, 4, 2)) {
				4219	case 0:
				4220	align = 0; break;
				4221	case 3:
				4222	return MCDisassembler::Fail;
				4223	default:
				4224	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4225	}
				4226
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4227	index = fieldFromInstruction(Insn, 7, 1);
				4228	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4229	inc = 2;
				4230	break;
				4231	}
				4232
				4233	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4234	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4235	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4236	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4237	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4238	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4239	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4240	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4241	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4242	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4243	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4244	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4245	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4246	}
				4247
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4248	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4249	return MCDisassembler::Fail;
				4250	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4251	return MCDisassembler::Fail;
				4252	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4253	return MCDisassembler::Fail;
				4254	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4255	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4256	Inst.addOperand(MCOperand::CreateImm(index));
				4257
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4258	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4259	}
				4260
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4261	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4262	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4263	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4264	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4265	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4266	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4267	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4268	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4269
				4270	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4271	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4272
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4273	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4274	return MCDisassembler::Fail;
				4275	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4276	return MCDisassembler::Fail;
				4277	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4278	return MCDisassembler::Fail;
				4279	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4280	return MCDisassembler::Fail;
				4281	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4282	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4283
				4284	return S;
				4285	}
				4286
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4287	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4288	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4289	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4290	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4291	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4292	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4293	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4294	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4295
				4296	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4297	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4298
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4299	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4300	return MCDisassembler::Fail;
				4301	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4302	return MCDisassembler::Fail;
				4303	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4304	return MCDisassembler::Fail;
				4305	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4306	return MCDisassembler::Fail;
				4307	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4308	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4309
				4310	return S;
				4311	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	4312
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4313	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4314	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4315	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4316	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4317	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4318
				4319	if (pred == 0xF) {
				4320	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4321	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	4322	}
				4323
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	4324	if (mask == 0x0) {
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4325	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4326	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4327	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4328
				4329	Inst.addOperand(MCOperand::CreateImm(pred));
				4330	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4331	return S;
				4332	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4333
				4334	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4335	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4336	uint64_t Address, const void *Decoder) {
				4337	DecodeStatus S = MCDisassembler::Success;
				4338
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4339	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4340	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4341	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4342	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4343	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4344	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4345	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4346	bool writeback = (W == 1) \| (P == 0);
				4347
				4348	addr \|= (U << 8) \| (Rn << 9);
				4349
				4350	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4351	Check(S, MCDisassembler::SoftFail);
				4352	if (Rt == Rt2)
				4353	Check(S, MCDisassembler::SoftFail);
				4354
				4355	// Rt
				4356	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4357	return MCDisassembler::Fail;
				4358	// Rt2
				4359	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4360	return MCDisassembler::Fail;
				4361	// Writeback operand
				4362	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4363	return MCDisassembler::Fail;
				4364	// addr
				4365	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4366	return MCDisassembler::Fail;
				4367
				4368	return S;
				4369	}
				4370
				4371	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4372	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4373	uint64_t Address, const void *Decoder) {
				4374	DecodeStatus S = MCDisassembler::Success;
				4375
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4376	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4377	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4378	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4379	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4380	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4381	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4382	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4383	bool writeback = (W == 1) \| (P == 0);
				4384
				4385	addr \|= (U << 8) \| (Rn << 9);
				4386
				4387	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4388	Check(S, MCDisassembler::SoftFail);
				4389
				4390	// Writeback operand
				4391	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4392	return MCDisassembler::Fail;
				4393	// Rt
				4394	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4395	return MCDisassembler::Fail;
				4396	// Rt2
				4397	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4398	return MCDisassembler::Fail;
				4399	// addr
				4400	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4401	return MCDisassembler::Fail;
				4402
				4403	return S;
				4404	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4405
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4406	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4407	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4408	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4409	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4410	if (sign1 != sign2) return MCDisassembler::Fail;
				4411
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4412	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4413	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4414	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4415	Val \|= sign1 << 12;
				4416	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4417
				4418	return MCDisassembler::Success;
				4419	}
				4420
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4421	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	4422	uint64_t Address,
				4423	const void *Decoder) {
				4424	DecodeStatus S = MCDisassembler::Success;
				4425
				4426	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4427	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4428	Inst.addOperand(MCOperand::CreateImm(Val));
				4429	return S;
				4430	}
				4431
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4432	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4433	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4434	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4435	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4436	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4437	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4438
				4439	if (pred == 0xF)
				4440	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4441
				4442	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	35ee7d2	2012-04-18 14:18:57 +0000	[diff] [blame]	4443
				4444	if (Rt == Rn \|\| Rn == Rt2)
				4445	S = MCDisassembler::SoftFail;
				4446
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4447	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4448	return MCDisassembler::Fail;
				4449	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4450	return MCDisassembler::Fail;
				4451	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4452	return MCDisassembler::Fail;
				4453	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4454	return MCDisassembler::Fail;
				4455
				4456	return S;
				4457	}
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4458
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4459	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4460	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4461	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4462	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4463	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4464	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4465	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4466	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4467
				4468	DecodeStatus S = MCDisassembler::Success;
				4469
				4470	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	22925d9	2011-11-15 20:30:41 +0000	[diff] [blame]	4471	if (!(imm & 0x38) && cmode == 0xF) {
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4472	Inst.setOpcode(ARM::VMOVv2f32);
				4473	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4474	}
				4475
				4476	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4477
				4478	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4479	return MCDisassembler::Fail;
				4480	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4481	return MCDisassembler::Fail;
				4482	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4483
				4484	return S;
				4485	}
				4486
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4487	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4488	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4489	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4490	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4491	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4492	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4493	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4494	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4495
				4496	DecodeStatus S = MCDisassembler::Success;
				4497
				4498	// VMOVv4f32 is ambiguous with these decodings.
				4499	if (!(imm & 0x38) && cmode == 0xF) {
				4500	Inst.setOpcode(ARM::VMOVv4f32);
				4501	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4502	}
				4503
				4504	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4505
				4506	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4507	return MCDisassembler::Fail;
				4508	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4509	return MCDisassembler::Fail;
				4510	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4511
				4512	return S;
				4513	}
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4514
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4515	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4516	uint64_t Address, const void *Decoder) {
				4517	DecodeStatus S = MCDisassembler::Success;
				4518
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4519	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4520	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4521	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4522	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4523	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4524
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4525	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4526	S = MCDisassembler::SoftFail;
				4527
				4528	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4529	return MCDisassembler::Fail;
				4530	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4531	return MCDisassembler::Fail;
				4532	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4533	return MCDisassembler::Fail;
				4534	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4535	return MCDisassembler::Fail;
				4536	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4537	return MCDisassembler::Fail;
				4538
				4539	return S;
				4540	}
				4541
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4542	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4543	uint64_t Address, const void *Decoder) {
				4544
				4545	DecodeStatus S = MCDisassembler::Success;
				4546
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4547	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4548	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4549	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4550	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4551	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4552
				4553	if ((cop & ~0x1) == 0xa)
				4554	return MCDisassembler::Fail;
				4555
				4556	if (Rt == Rt2)
				4557	S = MCDisassembler::SoftFail;
				4558
				4559	Inst.addOperand(MCOperand::CreateImm(cop));
				4560	Inst.addOperand(MCOperand::CreateImm(opc1));
				4561	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4562	return MCDisassembler::Fail;
				4563	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4564	return MCDisassembler::Fail;
				4565	Inst.addOperand(MCOperand::CreateImm(CRm));
				4566
				4567	return S;
				4568	}
				4569