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gerrit-public.fairphone.software / platform / external / llvm / d213ee764341b5bf6664469a5404fe19c9732828 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 81a61fe96462de793410d0f723d56b2a2576c94f [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]27#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]34 // Handles the condition code status of instructions in IT blocks
35 class ITStatus
36 {
37 public:
38 // Returns the condition code for instruction in IT block
39 unsigned getITCC() {
40 unsigned CC = ARMCC::AL;
41 if (instrInITBlock())
42 CC = ITStates.back();
43 return CC;
44 }
45
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
48 ITStates.pop_back();
49 }
50
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
54 }
55
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
59 }
60
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Mask >> 4 & 1;
67 unsigned NumTZ = CountTrailingZeros_32(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
73 if (T)
74 ITStates.push_back(CCBits);
75 else
76 ITStates.push_back(CCBits ^ 1);
77 }
78 ITStates.push_back(CCBits);
79 }
80
81 private:
82 std::vector<unsigned char> ITStates;
83 };
84}
85
86namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]87/// ARMDisassembler - ARM disassembler for all ARM platforms.
88class ARMDisassembler : public MCDisassembler {
89public:
90 /// Constructor - Initializes the disassembler.
91 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]92 ARMDisassembler(const MCSubtargetInfo &STI) :
93 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]94 }
95
96 ~ARMDisassembler() {
97 }
98
99 /// getInstruction - See MCDisassembler.
100 DecodeStatus getInstruction(MCInst &instr,
101 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]102 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]103 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]104 raw_ostream &vStream,
105 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]106
107 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]108 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]109private:
110};
111
112/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
113class ThumbDisassembler : public MCDisassembler {
114public:
115 /// Constructor - Initializes the disassembler.
116 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]117 ThumbDisassembler(const MCSubtargetInfo &STI) :
118 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]119 }
120
121 ~ThumbDisassembler() {
122 }
123
124 /// getInstruction - See MCDisassembler.
125 DecodeStatus getInstruction(MCInst &instr,
126 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]127 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]128 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]129 raw_ostream &vStream,
130 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]131
132 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]133 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]134private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]135 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]136 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]137 void UpdateThumbVFPPredicate(MCInst&) const;
138};
139}
140
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]141static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]142 switch (In) {
143 case MCDisassembler::Success:
144 // Out stays the same.
145 return true;
146 case MCDisassembler::SoftFail:
147 Out = In;
148 return true;
149 case MCDisassembler::Fail:
150 Out = In;
151 return false;
152 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]153 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]154}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]155
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]156
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157// Forward declare these because the autogenerated code will reference them.
158// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]162 unsigned RegNo, uint64_t Address,
163 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]166static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]177 unsigned RegNo,
178 uint64_t Address,
179 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]184static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]187
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]200
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]201static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]203static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]205static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]206 unsigned Insn,
207 uint64_t Address,
208 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]209static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]211static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]215static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
217
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]218static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]219 unsigned Insn,
220 uint64_t Adddress,
221 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]238static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]326static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]328static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]330static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]332static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]333 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]334static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]336static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]338static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]340static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]342static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]343 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]344static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]346static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]348static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]350static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]352static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]354static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]356static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]358static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]359 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]360static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]362static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]364static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]366static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]368static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]369 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]370static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]371 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]372static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]373 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]374static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]375 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]376static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]377 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
380
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]381static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]382 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]383static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385#include "ARMGenDisassemblerTables.inc"
386#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]387#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]388
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]389static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
390 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]391}
392
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]393static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
394 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]395}
396
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]397const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]398 return instInfoARM;
399}
400
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]401const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]402 return instInfoARM;
403}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]404
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]405DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]406 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]407 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]408 raw_ostream &os,
409 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]410 CommentStream = &cs;
411
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]412 uint8_t bytes[4];
413
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
416
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]417 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
419 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]420 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]421 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]422
423 // Encoded as a small-endian 32-bit word in the stream.
424 uint32_t insn = (bytes[3] << 24) |
425 (bytes[2] << 16) |
426 (bytes[1] << 8) |
427 (bytes[0] << 0);
428
429 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]431 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]432 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]433 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]434 }
435
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 // VFP and NEON instructions, similarly, are shared between ARM
437 // and Thumb modes.
438 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]439 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]440 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]441 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]442 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]443 }
444
445 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]447 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]448 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]453 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]454 }
455
456 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]458 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]459 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]460 // Add a fake predicate operand, because we share these instruction
461 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]462 if (!DecodePredicateOperand(MI, 0xE, Address, this))
463 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]464 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]465 }
466
467 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]469 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]470 Size = 4;
471 // Add a fake predicate operand, because we share these instruction
472 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]473 if (!DecodePredicateOperand(MI, 0xE, Address, this))
474 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]475 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]476 }
477
478 MI.clear();
479
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]480 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]481 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]482}
483
484namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]485extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]486}
487
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]488/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
489/// immediate Value in the MCInst. The immediate Value has had any PC
490/// adjustment made by the caller. If the instruction is a branch instruction
491/// then isBranch is true, else false. If the getOpInfo() function was set as
492/// part of the setupForSymbolicDisassembly() call then that function is called
493/// to get any symbolic information at the Address for this instruction. If
494/// that returns non-zero then the symbolic information it returns is used to
495/// create an MCExpr and that is added as an operand to the MCInst. If
496/// getOpInfo() returns zero and isBranch is true then a symbol look up for
497/// Value is done and if a symbol is found an MCExpr is created with that, else
498/// an MCExpr with Value is created. This function returns true if it adds an
499/// operand to the MCInst and false otherwise.
500static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
501 bool isBranch, uint64_t InstSize,
502 MCInst &MI, const void *Decoder) {
503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]505 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]507 SymbolicOp.Value = Value;
508 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]509
510 if (!getOpInfo ||
511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
512 // Clear SymbolicOp.Value from above and also all other fields.
513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
515 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]516 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]517 uint64_t ReferenceType;
518 if (isBranch)
519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
520 else
521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
522 const char *ReferenceName;
523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
524 &ReferenceName);
525 if (Name) {
526 SymbolicOp.AddSymbol.Name = Name;
527 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]528 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]529 // For branches always create an MCExpr so it gets printed as hex address.
530 else if (isBranch) {
531 SymbolicOp.Value = Value;
532 }
533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
535 if (!Name && !isBranch)
536 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]537 }
538
539 MCContext *Ctx = Dis->getMCContext();
540 const MCExpr *Add = NULL;
541 if (SymbolicOp.AddSymbol.Present) {
542 if (SymbolicOp.AddSymbol.Name) {
543 StringRef Name(SymbolicOp.AddSymbol.Name);
544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
545 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
546 } else {
547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
548 }
549 }
550
551 const MCExpr *Sub = NULL;
552 if (SymbolicOp.SubtractSymbol.Present) {
553 if (SymbolicOp.SubtractSymbol.Name) {
554 StringRef Name(SymbolicOp.SubtractSymbol.Name);
555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
557 } else {
558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
559 }
560 }
561
562 const MCExpr *Off = NULL;
563 if (SymbolicOp.Value != 0)
564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
565
566 const MCExpr *Expr;
567 if (Sub) {
568 const MCExpr *LHS;
569 if (Add)
570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
571 else
572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
573 if (Off != 0)
574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
575 else
576 Expr = LHS;
577 } else if (Add) {
578 if (Off != 0)
579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
580 else
581 Expr = Add;
582 } else {
583 if (Off != 0)
584 Expr = Off;
585 else
586 Expr = MCConstantExpr::Create(0, *Ctx);
587 }
588
589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
594 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]595 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]596 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]597
598 return true;
599}
600
601/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
602/// referenced by a load instruction with the base register that is the Pc.
603/// These can often be values in a literal pool near the Address of the
604/// instruction. The Address of the instruction and its immediate Value are
605/// used as a possible literal pool entry. The SymbolLookUp call back will
606/// return the name of a symbol referenced by the the literal pool's entry if
607/// the referenced address is that of a symbol. Or it will return a pointer to
608/// a literal 'C' string if the referenced address of the literal pool's entry
609/// is an address into a section with 'C' string literals.
610static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]611 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
614 if (SymbolLookUp) {
615 void *DisInfo = Dis->getDisInfoBlock();
616 uint64_t ReferenceType;
617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
618 const char *ReferenceName;
619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
623 }
624}
625
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626// Thumb1 instructions don't have explicit S bits. Rather, they
627// implicitly set CPSR. Since it's not represented in the encoding, the
628// auto-generated decoder won't inject the CPSR operand. We need to fix
629// that as a post-pass.
630static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]633 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]634 for (unsigned i = 0; i < NumOps; ++i, ++I) {
635 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]637 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
639 return;
640 }
641 }
642
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]644}
645
646// Most Thumb instructions don't have explicit predicates in the
647// encoding, but rather get their predicates from IT context. We need
648// to fix up the predicate operands using this context information as a
649// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]650MCDisassembler::DecodeStatus
651ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]652 MCDisassembler::DecodeStatus S = Success;
653
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]654 // A few instructions actually have predicates encoded in them. Don't
655 // try to overwrite it if we're seeing one of those.
656 switch (MI.getOpcode()) {
657 case ARM::tBcc:
658 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]659 case ARM::tCBZ:
660 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]661 case ARM::tCPS:
662 case ARM::t2CPS3p:
663 case ARM::t2CPS2p:
664 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]665 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]666 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]667 // Some instructions (mostly conditional branches) are not
668 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]669 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]670 S = SoftFail;
671 else
672 return Success;
673 break;
674 case ARM::tB:
675 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]676 case ARM::t2TBB:
677 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]678 // Some instructions (mostly unconditional branches) can
679 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]681 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]682 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683 default:
684 break;
685 }
686
687 // If we're in an IT block, base the predicate on that. Otherwise,
688 // assume a predicate of AL.
689 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]690 CC = ITBlock.getITCC();
691 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]692 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]693 if (ITBlock.instrInITBlock())
694 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]695
696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]699 for (unsigned i = 0; i < NumOps; ++i, ++I) {
700 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701 if (OpInfo[i].isPredicate()) {
702 I = MI.insert(I, MCOperand::CreateImm(CC));
703 ++I;
704 if (CC == ARMCC::AL)
705 MI.insert(I, MCOperand::CreateReg(0));
706 else
707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]708 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 }
710 }
711
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]712 I = MI.insert(I, MCOperand::CreateImm(CC));
713 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]714 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]715 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]716 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]719 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720}
721
722// Thumb VFP instructions are a special case. Because we share their
723// encodings between ARM and Thumb modes, and they are predicable in ARM
724// mode, the auto-generated decoder will give them an (incorrect)
725// predicate operand. We need to rewrite these operands based on the IT
726// context as a post-pass.
727void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
728 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]729 CC = ITBlock.getITCC();
730 if (ITBlock.instrInITBlock())
731 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732
733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
734 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
736 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]737 if (OpInfo[i].isPredicate() ) {
738 I->setImm(CC);
739 ++I;
740 if (CC == ARMCC::AL)
741 I->setReg(0);
742 else
743 I->setReg(ARM::CPSR);
744 return;
745 }
746 }
747}
748
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]749DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]750 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]751 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]752 raw_ostream &os,
753 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]754 CommentStream = &cs;
755
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]756 uint8_t bytes[4];
757
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]758 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
760
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
763 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]764 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]765 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766
767 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]769 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]771 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]772 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]773 }
774
775 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]777 if (result) {
778 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]779 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]780 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]782 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 }
784
785 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]787 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]789
790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
791 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]793 result = MCDisassembler::SoftFail;
794
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]795 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796
797 // If we find an IT instruction, we need to parse its condition
798 // code and mask operands so that we can apply them correctly
799 // to the subsequent instructions.
800 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]801
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]802 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]803 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]804 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]805 }
806
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]807 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808 }
809
810 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
812 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]814 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]815
816 uint32_t insn32 = (bytes[3] << 8) |
817 (bytes[2] << 0) |
818 (bytes[1] << 24) |
819 (bytes[0] << 16);
820 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]823 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]824 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]825 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]826 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]827 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]828 }
829
830 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]834 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]835 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836 }
837
838 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841 Size = 4;
842 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]843 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 }
845
846 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]848 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]849 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]850 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]851 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]852 }
853
854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
855 MI.clear();
856 uint32_t NEONLdStInsn = insn32;
857 NEONLdStInsn &= 0xF0FFFFFF;
858 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]861 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]862 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]863 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]864 }
865 }
866
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]868 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]869 uint32_t NEONDataInsn = insn32;
870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]874 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]875 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]876 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]877 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]878 }
879 }
880
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]881 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883}
884
885
886extern "C" void LLVMInitializeARMDisassembler() {
887 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
888 createARMDisassembler);
889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
890 createThumbDisassembler);
891}
892
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]893static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]894 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
895 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
896 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
897 ARM::R12, ARM::SP, ARM::LR, ARM::PC
898};
899
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]900static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 uint64_t Address, const void *Decoder) {
902 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904
905 unsigned Register = GPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908}
909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]910static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]911DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]912 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]913 DecodeStatus S = MCDisassembler::Success;
914
915 if (RegNo == 15)
916 S = MCDisassembler::SoftFail;
917
918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
919
920 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]921}
922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]923static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]924 uint64_t Address, const void *Decoder) {
925 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]926 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
928}
929
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]930static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]931 uint64_t Address, const void *Decoder) {
932 unsigned Register = 0;
933 switch (RegNo) {
934 case 0:
935 Register = ARM::R0;
936 break;
937 case 1:
938 Register = ARM::R1;
939 break;
940 case 2:
941 Register = ARM::R2;
942 break;
943 case 3:
944 Register = ARM::R3;
945 break;
946 case 9:
947 Register = ARM::R9;
948 break;
949 case 12:
950 Register = ARM::R12;
951 break;
952 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 }
955
956 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]957 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958}
959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]960static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
964}
965
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]966static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
968 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
969 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
970 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
971 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
972 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
973 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
974 ARM::S28, ARM::S29, ARM::S30, ARM::S31
975};
976
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]977static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978 uint64_t Address, const void *Decoder) {
979 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981
982 unsigned Register = SPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]984 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985}
986
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]987static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
989 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
990 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
991 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
992 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
993 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
994 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
995 ARM::D28, ARM::D29, ARM::D30, ARM::D31
996};
997
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]998static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999 uint64_t Address, const void *Decoder) {
1000 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1001 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002
1003 unsigned Register = DPRDecoderTable[RegNo];
1004 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1005 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006}
1007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1008static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 uint64_t Address, const void *Decoder) {
1010 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1011 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1013}
1014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1015static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1016DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1017 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1018 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1019 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1021}
1022
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1023static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1028};
1029
1030
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1031static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 uint64_t Address, const void *Decoder) {
1033 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1034 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1035 RegNo >>= 1;
1036
1037 unsigned Register = QPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1039 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1040}
1041
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1042static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1048 ARM::Q15
1049};
1050
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1051static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1052 uint64_t Address, const void *Decoder) {
1053 if (RegNo > 30)
1054 return MCDisassembler::Fail;
1055
1056 unsigned Register = DPairDecoderTable[RegNo];
1057 Inst.addOperand(MCOperand::CreateReg(Register));
1058 return MCDisassembler::Success;
1059}
1060
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1061static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1069 ARM::D28_D30, ARM::D29_D31
1070};
1071
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1072static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1073 unsigned RegNo,
1074 uint64_t Address,
1075 const void *Decoder) {
1076 if (RegNo > 29)
1077 return MCDisassembler::Fail;
1078
1079 unsigned Register = DPairSpacedDecoderTable[RegNo];
1080 Inst.addOperand(MCOperand::CreateReg(Register));
1081 return MCDisassembler::Success;
1082}
1083
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1084static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1085 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1086 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1087 // AL predicate is not allowed on Thumb1 branches.
1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1090 Inst.addOperand(MCOperand::CreateImm(Val));
1091 if (Val == ARMCC::AL) {
1092 Inst.addOperand(MCOperand::CreateReg(0));
1093 } else
1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1095 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1096}
1097
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1098static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1099 uint64_t Address, const void *Decoder) {
1100 if (Val)
1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1102 else
1103 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1104 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1105}
1106
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1107static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1108 uint64_t Address, const void *Decoder) {
1109 uint32_t imm = Val & 0xFF;
1110 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1113 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114}
1115
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1116static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119
1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1121 unsigned type = fieldFromInstruction32(Val, 5, 2);
1122 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1123
1124 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1126 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127
1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1129 switch (type) {
1130 case 0:
1131 Shift = ARM_AM::lsl;
1132 break;
1133 case 1:
1134 Shift = ARM_AM::lsr;
1135 break;
1136 case 2:
1137 Shift = ARM_AM::asr;
1138 break;
1139 case 3:
1140 Shift = ARM_AM::ror;
1141 break;
1142 }
1143
1144 if (Shift == ARM_AM::ror && imm == 0)
1145 Shift = ARM_AM::rrx;
1146
1147 unsigned Op = Shift | (imm << 3);
1148 Inst.addOperand(MCOperand::CreateImm(Op));
1149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1150 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1151}
1152
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1153static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1154 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1155 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1158 unsigned type = fieldFromInstruction32(Val, 5, 2);
1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1160
1161 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1163 return MCDisassembler::Fail;
1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1165 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166
1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1168 switch (type) {
1169 case 0:
1170 Shift = ARM_AM::lsl;
1171 break;
1172 case 1:
1173 Shift = ARM_AM::lsr;
1174 break;
1175 case 2:
1176 Shift = ARM_AM::asr;
1177 break;
1178 case 3:
1179 Shift = ARM_AM::ror;
1180 break;
1181 }
1182
1183 Inst.addOperand(MCOperand::CreateImm(Shift));
1184
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1185 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186}
1187
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1188static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1189 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1190 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1191
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1192 bool writebackLoad = false;
1193 unsigned writebackReg = 0;
1194 switch (Inst.getOpcode()) {
1195 default:
1196 break;
1197 case ARM::LDMIA_UPD:
1198 case ARM::LDMDB_UPD:
1199 case ARM::LDMIB_UPD:
1200 case ARM::LDMDA_UPD:
1201 case ARM::t2LDMIA_UPD:
1202 case ARM::t2LDMDB_UPD:
1203 writebackLoad = true;
1204 writebackReg = Inst.getOperand(0).getReg();
1205 break;
1206 }
1207
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1208 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1211 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1213 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1214 // Writeback not allowed if Rn is in the target list.
1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1216 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1217 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 }
1219
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1220 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221}
1222
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1223static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1226
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1227 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1228 unsigned regs = Val & 0xFF;
1229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1231 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1232 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1235 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1237 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238}
1239
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1240static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1241 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1242 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1243
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1244 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1245 unsigned regs = (Val & 0xFF) / 2;
1246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1247 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1249 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1250 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1251 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1252 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1253
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1254 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255}
1256
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1257static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1258 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1259 // This operand encodes a mask of contiguous zeros between a specified MSB
1260 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1261 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1262 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1263 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1264 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1265 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1266
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1267 DecodeStatus S = MCDisassembler::Success;
1268 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1269
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1270 uint32_t msb_mask = 0xFFFFFFFF;
1271 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1272 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1273
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1274 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1275 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1276}
1277
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1278static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1279 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1280 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1281
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1283 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1284 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1285 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1287 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1288
1289 switch (Inst.getOpcode()) {
1290 case ARM::LDC_OFFSET:
1291 case ARM::LDC_PRE:
1292 case ARM::LDC_POST:
1293 case ARM::LDC_OPTION:
1294 case ARM::LDCL_OFFSET:
1295 case ARM::LDCL_PRE:
1296 case ARM::LDCL_POST:
1297 case ARM::LDCL_OPTION:
1298 case ARM::STC_OFFSET:
1299 case ARM::STC_PRE:
1300 case ARM::STC_POST:
1301 case ARM::STC_OPTION:
1302 case ARM::STCL_OFFSET:
1303 case ARM::STCL_PRE:
1304 case ARM::STCL_POST:
1305 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1306 case ARM::t2LDC_OFFSET:
1307 case ARM::t2LDC_PRE:
1308 case ARM::t2LDC_POST:
1309 case ARM::t2LDC_OPTION:
1310 case ARM::t2LDCL_OFFSET:
1311 case ARM::t2LDCL_PRE:
1312 case ARM::t2LDCL_POST:
1313 case ARM::t2LDCL_OPTION:
1314 case ARM::t2STC_OFFSET:
1315 case ARM::t2STC_PRE:
1316 case ARM::t2STC_POST:
1317 case ARM::t2STC_OPTION:
1318 case ARM::t2STCL_OFFSET:
1319 case ARM::t2STCL_PRE:
1320 case ARM::t2STCL_POST:
1321 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1322 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1323 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1324 break;
1325 default:
1326 break;
1327 }
1328
1329 Inst.addOperand(MCOperand::CreateImm(coproc));
1330 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1332 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1333
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1334 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1335 case ARM::t2LDC2_OFFSET:
1336 case ARM::t2LDC2L_OFFSET:
1337 case ARM::t2LDC2_PRE:
1338 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1339 case ARM::t2STC2_OFFSET:
1340 case ARM::t2STC2L_OFFSET:
1341 case ARM::t2STC2_PRE:
1342 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1343 case ARM::LDC2_OFFSET:
1344 case ARM::LDC2L_OFFSET:
1345 case ARM::LDC2_PRE:
1346 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1347 case ARM::STC2_OFFSET:
1348 case ARM::STC2L_OFFSET:
1349 case ARM::STC2_PRE:
1350 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1351 case ARM::t2LDC_OFFSET:
1352 case ARM::t2LDCL_OFFSET:
1353 case ARM::t2LDC_PRE:
1354 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1355 case ARM::t2STC_OFFSET:
1356 case ARM::t2STCL_OFFSET:
1357 case ARM::t2STC_PRE:
1358 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1359 case ARM::LDC_OFFSET:
1360 case ARM::LDCL_OFFSET:
1361 case ARM::LDC_PRE:
1362 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1363 case ARM::STC_OFFSET:
1364 case ARM::STCL_OFFSET:
1365 case ARM::STC_PRE:
1366 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1367 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1368 Inst.addOperand(MCOperand::CreateImm(imm));
1369 break;
1370 case ARM::t2LDC2_POST:
1371 case ARM::t2LDC2L_POST:
1372 case ARM::t2STC2_POST:
1373 case ARM::t2STC2L_POST:
1374 case ARM::LDC2_POST:
1375 case ARM::LDC2L_POST:
1376 case ARM::STC2_POST:
1377 case ARM::STC2L_POST:
1378 case ARM::t2LDC_POST:
1379 case ARM::t2LDCL_POST:
1380 case ARM::t2STC_POST:
1381 case ARM::t2STCL_POST:
1382 case ARM::LDC_POST:
1383 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1384 case ARM::STC_POST:
1385 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1387 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1388 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1389 // The 'option' variant doesn't encode 'U' in the immediate since
1390 // the immediate is unsigned [0,255].
1391 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1392 break;
1393 }
1394
1395 switch (Inst.getOpcode()) {
1396 case ARM::LDC_OFFSET:
1397 case ARM::LDC_PRE:
1398 case ARM::LDC_POST:
1399 case ARM::LDC_OPTION:
1400 case ARM::LDCL_OFFSET:
1401 case ARM::LDCL_PRE:
1402 case ARM::LDCL_POST:
1403 case ARM::LDCL_OPTION:
1404 case ARM::STC_OFFSET:
1405 case ARM::STC_PRE:
1406 case ARM::STC_POST:
1407 case ARM::STC_OPTION:
1408 case ARM::STCL_OFFSET:
1409 case ARM::STCL_PRE:
1410 case ARM::STCL_POST:
1411 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1412 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1413 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1414 break;
1415 default:
1416 break;
1417 }
1418
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1419 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1420}
1421
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1422static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1423DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1424 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1426
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1428 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1429 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1430 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1431 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1432 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1433 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1434 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1435
1436 // On stores, the writeback operand precedes Rt.
1437 switch (Inst.getOpcode()) {
1438 case ARM::STR_POST_IMM:
1439 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1440 case ARM::STRB_POST_IMM:
1441 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1442 case ARM::STRT_POST_REG:
1443 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1444 case ARM::STRBT_POST_REG:
1445 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1447 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1448 break;
1449 default:
1450 break;
1451 }
1452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1454 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1455
1456 // On loads, the writeback operand comes after Rt.
1457 switch (Inst.getOpcode()) {
1458 case ARM::LDR_POST_IMM:
1459 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1460 case ARM::LDRB_POST_IMM:
1461 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1462 case ARM::LDRBT_POST_REG:
1463 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1464 case ARM::LDRT_POST_REG:
1465 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1467 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468 break;
1469 default:
1470 break;
1471 }
1472
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1474 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1475
1476 ARM_AM::AddrOpc Op = ARM_AM::add;
1477 if (!fieldFromInstruction32(Insn, 23, 1))
1478 Op = ARM_AM::sub;
1479
1480 bool writeback = (P == 0) || (W == 1);
1481 unsigned idx_mode = 0;
1482 if (P && writeback)
1483 idx_mode = ARMII::IndexModePre;
1484 else if (!P && writeback)
1485 idx_mode = ARMII::IndexModePost;
1486
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1487 if (writeback && (Rn == 15 || Rn == Rt))
1488 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1489
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1490 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1491 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1492 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1493 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1494 switch( fieldFromInstruction32(Insn, 5, 2)) {
1495 case 0:
1496 Opc = ARM_AM::lsl;
1497 break;
1498 case 1:
1499 Opc = ARM_AM::lsr;
1500 break;
1501 case 2:
1502 Opc = ARM_AM::asr;
1503 break;
1504 case 3:
1505 Opc = ARM_AM::ror;
1506 break;
1507 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1508 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1509 }
1510 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1511 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1512
1513 Inst.addOperand(MCOperand::CreateImm(imm));
1514 } else {
1515 Inst.addOperand(MCOperand::CreateReg(0));
1516 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1517 Inst.addOperand(MCOperand::CreateImm(tmp));
1518 }
1519
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1520 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1521 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1522
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1523 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524}
1525
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1526static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1527 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1528 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1529
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1531 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1532 unsigned type = fieldFromInstruction32(Val, 5, 2);
1533 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1534 unsigned U = fieldFromInstruction32(Val, 12, 1);
1535
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1536 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537 switch (type) {
1538 case 0:
1539 ShOp = ARM_AM::lsl;
1540 break;
1541 case 1:
1542 ShOp = ARM_AM::lsr;
1543 break;
1544 case 2:
1545 ShOp = ARM_AM::asr;
1546 break;
1547 case 3:
1548 ShOp = ARM_AM::ror;
1549 break;
1550 }
1551
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1553 return MCDisassembler::Fail;
1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1555 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1556 unsigned shift;
1557 if (U)
1558 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1559 else
1560 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1561 Inst.addOperand(MCOperand::CreateImm(shift));
1562
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1563 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1564}
1565
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1566static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1567DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1568 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1569 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1570
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1571 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1572 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1573 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1574 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1575 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1576 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1577 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1578 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1579 unsigned P = fieldFromInstruction32(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1580 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581
1582 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1583
1584 // For {LD,ST}RD, Rt must be even, else undefined.
1585 switch (Inst.getOpcode()) {
1586 case ARM::STRD:
1587 case ARM::STRD_PRE:
1588 case ARM::STRD_POST:
1589 case ARM::LDRD:
1590 case ARM::LDRD_PRE:
1591 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1592 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1593 break;
1594 default:
1595 break;
1596 }
1597 switch (Inst.getOpcode()) {
1598 case ARM::STRD:
1599 case ARM::STRD_PRE:
1600 case ARM::STRD_POST:
1601 if (P == 0 && W == 1)
1602 S = MCDisassembler::SoftFail;
1603
1604 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1605 S = MCDisassembler::SoftFail;
1606 if (type && Rm == 15)
1607 S = MCDisassembler::SoftFail;
1608 if (Rt2 == 15)
1609 S = MCDisassembler::SoftFail;
1610 if (!type && fieldFromInstruction32(Insn, 8, 4))
1611 S = MCDisassembler::SoftFail;
1612 break;
1613 case ARM::STRH:
1614 case ARM::STRH_PRE:
1615 case ARM::STRH_POST:
1616 if (Rt == 15)
1617 S = MCDisassembler::SoftFail;
1618 if (writeback && (Rn == 15 || Rn == Rt))
1619 S = MCDisassembler::SoftFail;
1620 if (!type && Rm == 15)
1621 S = MCDisassembler::SoftFail;
1622 break;
1623 case ARM::LDRD:
1624 case ARM::LDRD_PRE:
1625 case ARM::LDRD_POST:
1626 if (type && Rn == 15){
1627 if (Rt2 == 15)
1628 S = MCDisassembler::SoftFail;
1629 break;
1630 }
1631 if (P == 0 && W == 1)
1632 S = MCDisassembler::SoftFail;
1633 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1634 S = MCDisassembler::SoftFail;
1635 if (!type && writeback && Rn == 15)
1636 S = MCDisassembler::SoftFail;
1637 if (writeback && (Rn == Rt || Rn == Rt2))
1638 S = MCDisassembler::SoftFail;
1639 break;
1640 case ARM::LDRH:
1641 case ARM::LDRH_PRE:
1642 case ARM::LDRH_POST:
1643 if (type && Rn == 15){
1644 if (Rt == 15)
1645 S = MCDisassembler::SoftFail;
1646 break;
1647 }
1648 if (Rt == 15)
1649 S = MCDisassembler::SoftFail;
1650 if (!type && Rm == 15)
1651 S = MCDisassembler::SoftFail;
1652 if (!type && writeback && (Rn == 15 || Rn == Rt))
1653 S = MCDisassembler::SoftFail;
1654 break;
1655 case ARM::LDRSH:
1656 case ARM::LDRSH_PRE:
1657 case ARM::LDRSH_POST:
1658 case ARM::LDRSB:
1659 case ARM::LDRSB_PRE:
1660 case ARM::LDRSB_POST:
1661 if (type && Rn == 15){
1662 if (Rt == 15)
1663 S = MCDisassembler::SoftFail;
1664 break;
1665 }
1666 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1667 S = MCDisassembler::SoftFail;
1668 if (!type && (Rt == 15 || Rm == 15))
1669 S = MCDisassembler::SoftFail;
1670 if (!type && writeback && (Rn == 15 || Rn == Rt))
1671 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1672 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1673 default:
1674 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1675 }
1676
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1677 if (writeback) { // Writeback
1678 if (P)
1679 U |= ARMII::IndexModePre << 9;
1680 else
1681 U |= ARMII::IndexModePost << 9;
1682
1683 // On stores, the writeback operand precedes Rt.
1684 switch (Inst.getOpcode()) {
1685 case ARM::STRD:
1686 case ARM::STRD_PRE:
1687 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1688 case ARM::STRH:
1689 case ARM::STRH_PRE:
1690 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1692 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1693 break;
1694 default:
1695 break;
1696 }
1697 }
1698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1700 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701 switch (Inst.getOpcode()) {
1702 case ARM::STRD:
1703 case ARM::STRD_PRE:
1704 case ARM::STRD_POST:
1705 case ARM::LDRD:
1706 case ARM::LDRD_PRE:
1707 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1709 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1710 break;
1711 default:
1712 break;
1713 }
1714
1715 if (writeback) {
1716 // On loads, the writeback operand comes after Rt.
1717 switch (Inst.getOpcode()) {
1718 case ARM::LDRD:
1719 case ARM::LDRD_PRE:
1720 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1721 case ARM::LDRH:
1722 case ARM::LDRH_PRE:
1723 case ARM::LDRH_POST:
1724 case ARM::LDRSH:
1725 case ARM::LDRSH_PRE:
1726 case ARM::LDRSH_POST:
1727 case ARM::LDRSB:
1728 case ARM::LDRSB_PRE:
1729 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1730 case ARM::LDRHTr:
1731 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1733 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1734 break;
1735 default:
1736 break;
1737 }
1738 }
1739
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1741 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1742
1743 if (type) {
1744 Inst.addOperand(MCOperand::CreateReg(0));
1745 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1746 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1748 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1749 Inst.addOperand(MCOperand::CreateImm(U));
1750 }
1751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1752 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1753 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1754
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1755 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1756}
1757
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1758static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1759 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1760 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1761
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1762 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1763 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1764
1765 switch (mode) {
1766 case 0:
1767 mode = ARM_AM::da;
1768 break;
1769 case 1:
1770 mode = ARM_AM::ia;
1771 break;
1772 case 2:
1773 mode = ARM_AM::db;
1774 break;
1775 case 3:
1776 mode = ARM_AM::ib;
1777 break;
1778 }
1779
1780 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1782 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1783
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1784 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1785}
1786
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1787static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1788 unsigned Insn,
1789 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1790 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1791
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1793 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1794 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1795
1796 if (pred == 0xF) {
1797 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1798 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1799 Inst.setOpcode(ARM::RFEDA);
1800 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1801 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1802 Inst.setOpcode(ARM::RFEDA_UPD);
1803 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1804 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1805 Inst.setOpcode(ARM::RFEDB);
1806 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1807 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1808 Inst.setOpcode(ARM::RFEDB_UPD);
1809 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1810 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1811 Inst.setOpcode(ARM::RFEIA);
1812 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1813 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1814 Inst.setOpcode(ARM::RFEIA_UPD);
1815 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1816 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1817 Inst.setOpcode(ARM::RFEIB);
1818 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1819 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1820 Inst.setOpcode(ARM::RFEIB_UPD);
1821 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1822 case ARM::STMDA:
1823 Inst.setOpcode(ARM::SRSDA);
1824 break;
1825 case ARM::STMDA_UPD:
1826 Inst.setOpcode(ARM::SRSDA_UPD);
1827 break;
1828 case ARM::STMDB:
1829 Inst.setOpcode(ARM::SRSDB);
1830 break;
1831 case ARM::STMDB_UPD:
1832 Inst.setOpcode(ARM::SRSDB_UPD);
1833 break;
1834 case ARM::STMIA:
1835 Inst.setOpcode(ARM::SRSIA);
1836 break;
1837 case ARM::STMIA_UPD:
1838 Inst.setOpcode(ARM::SRSIA_UPD);
1839 break;
1840 case ARM::STMIB:
1841 Inst.setOpcode(ARM::SRSIB);
1842 break;
1843 case ARM::STMIB_UPD:
1844 Inst.setOpcode(ARM::SRSIB_UPD);
1845 break;
1846 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1847 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1848 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1849
1850 // For stores (which become SRS's, the only operand is the mode.
1851 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1852 Inst.addOperand(
1853 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1854 return S;
1855 }
1856
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1857 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1858 }
1859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1861 return MCDisassembler::Fail;
1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863 return MCDisassembler::Fail; // Tied
1864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1865 return MCDisassembler::Fail;
1866 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1867 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1868
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1869 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870}
1871
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1872static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1873 uint64_t Address, const void *Decoder) {
1874 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1875 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1876 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1878
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1880
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1881 // imod == '01' --> UNPREDICTABLE
1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1883 // return failure here. The '01' imod value is unprintable, so there's
1884 // nothing useful we could do even if we returned UNPREDICTABLE.
1885
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1886 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1887
1888 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889 Inst.setOpcode(ARM::CPS3p);
1890 Inst.addOperand(MCOperand::CreateImm(imod));
1891 Inst.addOperand(MCOperand::CreateImm(iflags));
1892 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1893 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1894 Inst.setOpcode(ARM::CPS2p);
1895 Inst.addOperand(MCOperand::CreateImm(imod));
1896 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1897 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1898 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899 Inst.setOpcode(ARM::CPS1p);
1900 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1901 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1902 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1903 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1904 Inst.setOpcode(ARM::CPS1p);
1905 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1906 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1907 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1908
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1909 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910}
1911
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1912static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1913 uint64_t Address, const void *Decoder) {
1914 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1915 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1916 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1917 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1918
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1919 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1920
1921 // imod == '01' --> UNPREDICTABLE
1922 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1923 // return failure here. The '01' imod value is unprintable, so there's
1924 // nothing useful we could do even if we returned UNPREDICTABLE.
1925
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1926 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1927
1928 if (imod && M) {
1929 Inst.setOpcode(ARM::t2CPS3p);
1930 Inst.addOperand(MCOperand::CreateImm(imod));
1931 Inst.addOperand(MCOperand::CreateImm(iflags));
1932 Inst.addOperand(MCOperand::CreateImm(mode));
1933 } else if (imod && !M) {
1934 Inst.setOpcode(ARM::t2CPS2p);
1935 Inst.addOperand(MCOperand::CreateImm(imod));
1936 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1937 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1938 } else if (!imod && M) {
1939 Inst.setOpcode(ARM::t2CPS1p);
1940 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1941 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1942 } else {
1943 // imod == '00' && M == '0' --> UNPREDICTABLE
1944 Inst.setOpcode(ARM::t2CPS1p);
1945 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1946 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1947 }
1948
1949 return S;
1950}
1951
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1952static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1953 uint64_t Address, const void *Decoder) {
1954 DecodeStatus S = MCDisassembler::Success;
1955
1956 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1957 unsigned imm = 0;
1958
1959 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1960 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1961 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1962 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1963
1964 if (Inst.getOpcode() == ARM::t2MOVTi16)
1965 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1966 return MCDisassembler::Fail;
1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1968 return MCDisassembler::Fail;
1969
1970 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1971 Inst.addOperand(MCOperand::CreateImm(imm));
1972
1973 return S;
1974}
1975
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1976static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1977 uint64_t Address, const void *Decoder) {
1978 DecodeStatus S = MCDisassembler::Success;
1979
1980 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1981 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1982 unsigned imm = 0;
1983
1984 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1985 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1986
1987 if (Inst.getOpcode() == ARM::MOVTi16)
1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1989 return MCDisassembler::Fail;
1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1991 return MCDisassembler::Fail;
1992
1993 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1994 Inst.addOperand(MCOperand::CreateImm(imm));
1995
1996 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1997 return MCDisassembler::Fail;
1998
1999 return S;
2000}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]2001
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2002static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2003 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2004 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2005
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2006 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
2007 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
2008 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
2009 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
2010 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2011
2012 if (pred == 0xF)
2013 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2015 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2016 return MCDisassembler::Fail;
2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2020 return MCDisassembler::Fail;
2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2022 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2023
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2024 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2025 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]2026
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2027 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2028}
2029
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2030static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2031 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2032 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2033
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2034 unsigned add = fieldFromInstruction32(Val, 12, 1);
2035 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2036 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2039 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2040
2041 if (!add) imm *= -1;
2042 if (imm == 0 && !add) imm = INT32_MIN;
2043 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2044 if (Rn == 15)
2045 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2046
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2047 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2048}
2049
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2050static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2051 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2052 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2053
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2054 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2055 unsigned U = fieldFromInstruction32(Val, 8, 1);
2056 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2057
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2059 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2060
2061 if (U)
2062 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2063 else
2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2065
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2066 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2067}
2068
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2069static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2070 uint64_t Address, const void *Decoder) {
2071 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2072}
2073
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2074static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2075DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2076 uint64_t Address, const void *Decoder) {
2077 DecodeStatus S = MCDisassembler::Success;
2078 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2079 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2080 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2081 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2082 (fieldFromInstruction32(Insn, 26, 1) << 19);
2083 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2084 true, 4, Inst, Decoder))
2085 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2086 return S;
2087}
2088
2089static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2090DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2093
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2095 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2096
2097 if (pred == 0xF) {
2098 Inst.setOpcode(ARM::BLXi);
2099 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2100 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2101 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2102 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2103 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2104 }
2105
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2106 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2107 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2110 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2111
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2112 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2113}
2114
2115
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2116static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2119
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2121 unsigned align = fieldFromInstruction32(Val, 4, 2);
2122
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2124 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2125 if (!align)
2126 Inst.addOperand(MCOperand::CreateImm(0));
2127 else
2128 Inst.addOperand(MCOperand::CreateImm(4 << align));
2129
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2130 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2131}
2132
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2133static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2135 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2136
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2139 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2140 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2141 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2142 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2143
2144 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2145 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2146 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2147 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2148 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2149 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2150 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2151 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2152 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2153 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2154 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2155 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2156 return MCDisassembler::Fail;
2157 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2158 case ARM::VLD2b16:
2159 case ARM::VLD2b32:
2160 case ARM::VLD2b8:
2161 case ARM::VLD2b16wb_fixed:
2162 case ARM::VLD2b16wb_register:
2163 case ARM::VLD2b32wb_fixed:
2164 case ARM::VLD2b32wb_register:
2165 case ARM::VLD2b8wb_fixed:
2166 case ARM::VLD2b8wb_register:
2167 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2168 return MCDisassembler::Fail;
2169 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2170 default:
2171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2172 return MCDisassembler::Fail;
2173 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2174
2175 // Second output register
2176 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2177 case ARM::VLD3d8:
2178 case ARM::VLD3d16:
2179 case ARM::VLD3d32:
2180 case ARM::VLD3d8_UPD:
2181 case ARM::VLD3d16_UPD:
2182 case ARM::VLD3d32_UPD:
2183 case ARM::VLD4d8:
2184 case ARM::VLD4d16:
2185 case ARM::VLD4d32:
2186 case ARM::VLD4d8_UPD:
2187 case ARM::VLD4d16_UPD:
2188 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2190 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2191 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2192 case ARM::VLD3q8:
2193 case ARM::VLD3q16:
2194 case ARM::VLD3q32:
2195 case ARM::VLD3q8_UPD:
2196 case ARM::VLD3q16_UPD:
2197 case ARM::VLD3q32_UPD:
2198 case ARM::VLD4q8:
2199 case ARM::VLD4q16:
2200 case ARM::VLD4q32:
2201 case ARM::VLD4q8_UPD:
2202 case ARM::VLD4q16_UPD:
2203 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2205 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2206 default:
2207 break;
2208 }
2209
2210 // Third output register
2211 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2212 case ARM::VLD3d8:
2213 case ARM::VLD3d16:
2214 case ARM::VLD3d32:
2215 case ARM::VLD3d8_UPD:
2216 case ARM::VLD3d16_UPD:
2217 case ARM::VLD3d32_UPD:
2218 case ARM::VLD4d8:
2219 case ARM::VLD4d16:
2220 case ARM::VLD4d32:
2221 case ARM::VLD4d8_UPD:
2222 case ARM::VLD4d16_UPD:
2223 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2224 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2225 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2226 break;
2227 case ARM::VLD3q8:
2228 case ARM::VLD3q16:
2229 case ARM::VLD3q32:
2230 case ARM::VLD3q8_UPD:
2231 case ARM::VLD3q16_UPD:
2232 case ARM::VLD3q32_UPD:
2233 case ARM::VLD4q8:
2234 case ARM::VLD4q16:
2235 case ARM::VLD4q32:
2236 case ARM::VLD4q8_UPD:
2237 case ARM::VLD4q16_UPD:
2238 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2240 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2241 break;
2242 default:
2243 break;
2244 }
2245
2246 // Fourth output register
2247 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2248 case ARM::VLD4d8:
2249 case ARM::VLD4d16:
2250 case ARM::VLD4d32:
2251 case ARM::VLD4d8_UPD:
2252 case ARM::VLD4d16_UPD:
2253 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2255 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2256 break;
2257 case ARM::VLD4q8:
2258 case ARM::VLD4q16:
2259 case ARM::VLD4q32:
2260 case ARM::VLD4q8_UPD:
2261 case ARM::VLD4q16_UPD:
2262 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2263 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2264 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2265 break;
2266 default:
2267 break;
2268 }
2269
2270 // Writeback operand
2271 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2272 case ARM::VLD1d8wb_fixed:
2273 case ARM::VLD1d16wb_fixed:
2274 case ARM::VLD1d32wb_fixed:
2275 case ARM::VLD1d64wb_fixed:
2276 case ARM::VLD1d8wb_register:
2277 case ARM::VLD1d16wb_register:
2278 case ARM::VLD1d32wb_register:
2279 case ARM::VLD1d64wb_register:
2280 case ARM::VLD1q8wb_fixed:
2281 case ARM::VLD1q16wb_fixed:
2282 case ARM::VLD1q32wb_fixed:
2283 case ARM::VLD1q64wb_fixed:
2284 case ARM::VLD1q8wb_register:
2285 case ARM::VLD1q16wb_register:
2286 case ARM::VLD1q32wb_register:
2287 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2288 case ARM::VLD1d8Twb_fixed:
2289 case ARM::VLD1d8Twb_register:
2290 case ARM::VLD1d16Twb_fixed:
2291 case ARM::VLD1d16Twb_register:
2292 case ARM::VLD1d32Twb_fixed:
2293 case ARM::VLD1d32Twb_register:
2294 case ARM::VLD1d64Twb_fixed:
2295 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2296 case ARM::VLD1d8Qwb_fixed:
2297 case ARM::VLD1d8Qwb_register:
2298 case ARM::VLD1d16Qwb_fixed:
2299 case ARM::VLD1d16Qwb_register:
2300 case ARM::VLD1d32Qwb_fixed:
2301 case ARM::VLD1d32Qwb_register:
2302 case ARM::VLD1d64Qwb_fixed:
2303 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2304 case ARM::VLD2d8wb_fixed:
2305 case ARM::VLD2d16wb_fixed:
2306 case ARM::VLD2d32wb_fixed:
2307 case ARM::VLD2q8wb_fixed:
2308 case ARM::VLD2q16wb_fixed:
2309 case ARM::VLD2q32wb_fixed:
2310 case ARM::VLD2d8wb_register:
2311 case ARM::VLD2d16wb_register:
2312 case ARM::VLD2d32wb_register:
2313 case ARM::VLD2q8wb_register:
2314 case ARM::VLD2q16wb_register:
2315 case ARM::VLD2q32wb_register:
2316 case ARM::VLD2b8wb_fixed:
2317 case ARM::VLD2b16wb_fixed:
2318 case ARM::VLD2b32wb_fixed:
2319 case ARM::VLD2b8wb_register:
2320 case ARM::VLD2b16wb_register:
2321 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2322 Inst.addOperand(MCOperand::CreateImm(0));
2323 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2324 case ARM::VLD3d8_UPD:
2325 case ARM::VLD3d16_UPD:
2326 case ARM::VLD3d32_UPD:
2327 case ARM::VLD3q8_UPD:
2328 case ARM::VLD3q16_UPD:
2329 case ARM::VLD3q32_UPD:
2330 case ARM::VLD4d8_UPD:
2331 case ARM::VLD4d16_UPD:
2332 case ARM::VLD4d32_UPD:
2333 case ARM::VLD4q8_UPD:
2334 case ARM::VLD4q16_UPD:
2335 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2336 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2337 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2338 break;
2339 default:
2340 break;
2341 }
2342
2343 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2344 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2345 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346
2347 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2348 switch (Inst.getOpcode()) {
2349 default:
2350 // The below have been updated to have explicit am6offset split
2351 // between fixed and register offset. For those instructions not
2352 // yet updated, we need to add an additional reg0 operand for the
2353 // fixed variant.
2354 //
2355 // The fixed offset encodes as Rm == 0xd, so we check for that.
2356 if (Rm == 0xd) {
2357 Inst.addOperand(MCOperand::CreateReg(0));
2358 break;
2359 }
2360 // Fall through to handle the register offset variant.
2361 case ARM::VLD1d8wb_fixed:
2362 case ARM::VLD1d16wb_fixed:
2363 case ARM::VLD1d32wb_fixed:
2364 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2365 case ARM::VLD1d8Twb_fixed:
2366 case ARM::VLD1d16Twb_fixed:
2367 case ARM::VLD1d32Twb_fixed:
2368 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2369 case ARM::VLD1d8Qwb_fixed:
2370 case ARM::VLD1d16Qwb_fixed:
2371 case ARM::VLD1d32Qwb_fixed:
2372 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2373 case ARM::VLD1d8wb_register:
2374 case ARM::VLD1d16wb_register:
2375 case ARM::VLD1d32wb_register:
2376 case ARM::VLD1d64wb_register:
2377 case ARM::VLD1q8wb_fixed:
2378 case ARM::VLD1q16wb_fixed:
2379 case ARM::VLD1q32wb_fixed:
2380 case ARM::VLD1q64wb_fixed:
2381 case ARM::VLD1q8wb_register:
2382 case ARM::VLD1q16wb_register:
2383 case ARM::VLD1q32wb_register:
2384 case ARM::VLD1q64wb_register:
2385 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2386 // variant encodes Rm == 0xf. Anything else is a register offset post-
2387 // increment and we need to add the register operand to the instruction.
2388 if (Rm != 0xD && Rm != 0xF &&
2389 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2390 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2391 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2392 case ARM::VLD2d8wb_fixed:
2393 case ARM::VLD2d16wb_fixed:
2394 case ARM::VLD2d32wb_fixed:
2395 case ARM::VLD2b8wb_fixed:
2396 case ARM::VLD2b16wb_fixed:
2397 case ARM::VLD2b32wb_fixed:
2398 case ARM::VLD2q8wb_fixed:
2399 case ARM::VLD2q16wb_fixed:
2400 case ARM::VLD2q32wb_fixed:
2401 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2402 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2403
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2404 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2405}
2406
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2407static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2408 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2409 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2410
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2411 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2412 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2413 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2414 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2415 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2416 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2417
2418 // Writeback Operand
2419 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2420 case ARM::VST1d8wb_fixed:
2421 case ARM::VST1d16wb_fixed:
2422 case ARM::VST1d32wb_fixed:
2423 case ARM::VST1d64wb_fixed:
2424 case ARM::VST1d8wb_register:
2425 case ARM::VST1d16wb_register:
2426 case ARM::VST1d32wb_register:
2427 case ARM::VST1d64wb_register:
2428 case ARM::VST1q8wb_fixed:
2429 case ARM::VST1q16wb_fixed:
2430 case ARM::VST1q32wb_fixed:
2431 case ARM::VST1q64wb_fixed:
2432 case ARM::VST1q8wb_register:
2433 case ARM::VST1q16wb_register:
2434 case ARM::VST1q32wb_register:
2435 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2436 case ARM::VST1d8Twb_fixed:
2437 case ARM::VST1d16Twb_fixed:
2438 case ARM::VST1d32Twb_fixed:
2439 case ARM::VST1d64Twb_fixed:
2440 case ARM::VST1d8Twb_register:
2441 case ARM::VST1d16Twb_register:
2442 case ARM::VST1d32Twb_register:
2443 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2444 case ARM::VST1d8Qwb_fixed:
2445 case ARM::VST1d16Qwb_fixed:
2446 case ARM::VST1d32Qwb_fixed:
2447 case ARM::VST1d64Qwb_fixed:
2448 case ARM::VST1d8Qwb_register:
2449 case ARM::VST1d16Qwb_register:
2450 case ARM::VST1d32Qwb_register:
2451 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2452 case ARM::VST2d8wb_fixed:
2453 case ARM::VST2d16wb_fixed:
2454 case ARM::VST2d32wb_fixed:
2455 case ARM::VST2d8wb_register:
2456 case ARM::VST2d16wb_register:
2457 case ARM::VST2d32wb_register:
2458 case ARM::VST2q8wb_fixed:
2459 case ARM::VST2q16wb_fixed:
2460 case ARM::VST2q32wb_fixed:
2461 case ARM::VST2q8wb_register:
2462 case ARM::VST2q16wb_register:
2463 case ARM::VST2q32wb_register:
2464 case ARM::VST2b8wb_fixed:
2465 case ARM::VST2b16wb_fixed:
2466 case ARM::VST2b32wb_fixed:
2467 case ARM::VST2b8wb_register:
2468 case ARM::VST2b16wb_register:
2469 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2470 if (Rm == 0xF)
2471 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2472 Inst.addOperand(MCOperand::CreateImm(0));
2473 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2474 case ARM::VST3d8_UPD:
2475 case ARM::VST3d16_UPD:
2476 case ARM::VST3d32_UPD:
2477 case ARM::VST3q8_UPD:
2478 case ARM::VST3q16_UPD:
2479 case ARM::VST3q32_UPD:
2480 case ARM::VST4d8_UPD:
2481 case ARM::VST4d16_UPD:
2482 case ARM::VST4d32_UPD:
2483 case ARM::VST4q8_UPD:
2484 case ARM::VST4q16_UPD:
2485 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2487 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2488 break;
2489 default:
2490 break;
2491 }
2492
2493 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2495 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496
2497 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2498 switch (Inst.getOpcode()) {
2499 default:
2500 if (Rm == 0xD)
2501 Inst.addOperand(MCOperand::CreateReg(0));
2502 else if (Rm != 0xF) {
2503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2504 return MCDisassembler::Fail;
2505 }
2506 break;
2507 case ARM::VST1d8wb_fixed:
2508 case ARM::VST1d16wb_fixed:
2509 case ARM::VST1d32wb_fixed:
2510 case ARM::VST1d64wb_fixed:
2511 case ARM::VST1q8wb_fixed:
2512 case ARM::VST1q16wb_fixed:
2513 case ARM::VST1q32wb_fixed:
2514 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2515 case ARM::VST1d8Twb_fixed:
2516 case ARM::VST1d16Twb_fixed:
2517 case ARM::VST1d32Twb_fixed:
2518 case ARM::VST1d64Twb_fixed:
2519 case ARM::VST1d8Qwb_fixed:
2520 case ARM::VST1d16Qwb_fixed:
2521 case ARM::VST1d32Qwb_fixed:
2522 case ARM::VST1d64Qwb_fixed:
2523 case ARM::VST2d8wb_fixed:
2524 case ARM::VST2d16wb_fixed:
2525 case ARM::VST2d32wb_fixed:
2526 case ARM::VST2q8wb_fixed:
2527 case ARM::VST2q16wb_fixed:
2528 case ARM::VST2q32wb_fixed:
2529 case ARM::VST2b8wb_fixed:
2530 case ARM::VST2b16wb_fixed:
2531 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2532 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2533 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2534
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2535
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2536 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2537 switch (Inst.getOpcode()) {
2538 case ARM::VST1q16:
2539 case ARM::VST1q32:
2540 case ARM::VST1q64:
2541 case ARM::VST1q8:
2542 case ARM::VST1q16wb_fixed:
2543 case ARM::VST1q16wb_register:
2544 case ARM::VST1q32wb_fixed:
2545 case ARM::VST1q32wb_register:
2546 case ARM::VST1q64wb_fixed:
2547 case ARM::VST1q64wb_register:
2548 case ARM::VST1q8wb_fixed:
2549 case ARM::VST1q8wb_register:
2550 case ARM::VST2d16:
2551 case ARM::VST2d32:
2552 case ARM::VST2d8:
2553 case ARM::VST2d16wb_fixed:
2554 case ARM::VST2d16wb_register:
2555 case ARM::VST2d32wb_fixed:
2556 case ARM::VST2d32wb_register:
2557 case ARM::VST2d8wb_fixed:
2558 case ARM::VST2d8wb_register:
2559 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2560 return MCDisassembler::Fail;
2561 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2562 case ARM::VST2b16:
2563 case ARM::VST2b32:
2564 case ARM::VST2b8:
2565 case ARM::VST2b16wb_fixed:
2566 case ARM::VST2b16wb_register:
2567 case ARM::VST2b32wb_fixed:
2568 case ARM::VST2b32wb_register:
2569 case ARM::VST2b8wb_fixed:
2570 case ARM::VST2b8wb_register:
2571 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2572 return MCDisassembler::Fail;
2573 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2574 default:
2575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2576 return MCDisassembler::Fail;
2577 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2578
2579 // Second input register
2580 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2581 case ARM::VST3d8:
2582 case ARM::VST3d16:
2583 case ARM::VST3d32:
2584 case ARM::VST3d8_UPD:
2585 case ARM::VST3d16_UPD:
2586 case ARM::VST3d32_UPD:
2587 case ARM::VST4d8:
2588 case ARM::VST4d16:
2589 case ARM::VST4d32:
2590 case ARM::VST4d8_UPD:
2591 case ARM::VST4d16_UPD:
2592 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2593 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2594 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2596 case ARM::VST3q8:
2597 case ARM::VST3q16:
2598 case ARM::VST3q32:
2599 case ARM::VST3q8_UPD:
2600 case ARM::VST3q16_UPD:
2601 case ARM::VST3q32_UPD:
2602 case ARM::VST4q8:
2603 case ARM::VST4q16:
2604 case ARM::VST4q32:
2605 case ARM::VST4q8_UPD:
2606 case ARM::VST4q16_UPD:
2607 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2608 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2609 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2610 break;
2611 default:
2612 break;
2613 }
2614
2615 // Third input register
2616 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2617 case ARM::VST3d8:
2618 case ARM::VST3d16:
2619 case ARM::VST3d32:
2620 case ARM::VST3d8_UPD:
2621 case ARM::VST3d16_UPD:
2622 case ARM::VST3d32_UPD:
2623 case ARM::VST4d8:
2624 case ARM::VST4d16:
2625 case ARM::VST4d32:
2626 case ARM::VST4d8_UPD:
2627 case ARM::VST4d16_UPD:
2628 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2629 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2630 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631 break;
2632 case ARM::VST3q8:
2633 case ARM::VST3q16:
2634 case ARM::VST3q32:
2635 case ARM::VST3q8_UPD:
2636 case ARM::VST3q16_UPD:
2637 case ARM::VST3q32_UPD:
2638 case ARM::VST4q8:
2639 case ARM::VST4q16:
2640 case ARM::VST4q32:
2641 case ARM::VST4q8_UPD:
2642 case ARM::VST4q16_UPD:
2643 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2644 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2645 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2646 break;
2647 default:
2648 break;
2649 }
2650
2651 // Fourth input register
2652 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2653 case ARM::VST4d8:
2654 case ARM::VST4d16:
2655 case ARM::VST4d32:
2656 case ARM::VST4d8_UPD:
2657 case ARM::VST4d16_UPD:
2658 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2659 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2660 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2661 break;
2662 case ARM::VST4q8:
2663 case ARM::VST4q16:
2664 case ARM::VST4q32:
2665 case ARM::VST4q8_UPD:
2666 case ARM::VST4q16_UPD:
2667 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 break;
2671 default:
2672 break;
2673 }
2674
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2675 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2676}
2677
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2678static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2680 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2681
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2683 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2684 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2685 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2686 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2687 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688
2689 align *= (1 << size);
2690
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2691 switch (Inst.getOpcode()) {
2692 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2693 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2694 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2695 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2696 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2697 return MCDisassembler::Fail;
2698 break;
2699 default:
2700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2701 return MCDisassembler::Fail;
2702 break;
2703 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2704 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2706 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2707 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2710 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2711 Inst.addOperand(MCOperand::CreateImm(align));
2712
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2713 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2714 // variant encodes Rm == 0xf. Anything else is a register offset post-
2715 // increment and we need to add the register operand to the instruction.
2716 if (Rm != 0xD && Rm != 0xF &&
2717 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2718 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2720 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721}
2722
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2723static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2725 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2726
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2727 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2728 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2729 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2730 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2731 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2732 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2733 align *= 2*size;
2734
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2735 switch (Inst.getOpcode()) {
2736 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2737 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2738 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2739 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2740 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2741 return MCDisassembler::Fail;
2742 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2743 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2744 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2745 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2746 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2747 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2748 return MCDisassembler::Fail;
2749 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2750 default:
2751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2752 return MCDisassembler::Fail;
2753 break;
2754 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2755
2756 if (Rm != 0xF)
2757 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2760 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761 Inst.addOperand(MCOperand::CreateImm(align));
2762
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2763 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2765 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2766 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2768 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769}
2770
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2771static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2772 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2773 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2774
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2775 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2776 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2777 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2778 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2779 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2780
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2784 return MCDisassembler::Fail;
2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2786 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2787 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2789 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2790 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2791
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2793 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2794 Inst.addOperand(MCOperand::CreateImm(0));
2795
2796 if (Rm == 0xD)
2797 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2798 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2800 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2801 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2803 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804}
2805
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2806static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2808 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2809
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2810 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2811 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2812 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2813 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2814 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2815 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2816 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2817
2818 if (size == 0x3) {
2819 size = 4;
2820 align = 16;
2821 } else {
2822 if (size == 2) {
2823 size = 1 << size;
2824 align *= 8;
2825 } else {
2826 size = 1 << size;
2827 align *= 4*size;
2828 }
2829 }
2830
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2832 return MCDisassembler::Fail;
2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2836 return MCDisassembler::Fail;
2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2838 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2839 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2841 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2842 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2845 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2846 Inst.addOperand(MCOperand::CreateImm(align));
2847
2848 if (Rm == 0xD)
2849 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2850 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2852 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2853 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2854
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2855 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856}
2857
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2858static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2859DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2860 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2861 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2862
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2863 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2864 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2865 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2866 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2867 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2868 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2869 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2870 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2871
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2872 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2873 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2874 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2875 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2877 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2878 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879
2880 Inst.addOperand(MCOperand::CreateImm(imm));
2881
2882 switch (Inst.getOpcode()) {
2883 case ARM::VORRiv4i16:
2884 case ARM::VORRiv2i32:
2885 case ARM::VBICiv4i16:
2886 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889 break;
2890 case ARM::VORRiv8i16:
2891 case ARM::VORRiv4i32:
2892 case ARM::VBICiv8i16:
2893 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2894 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2895 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896 break;
2897 default:
2898 break;
2899 }
2900
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2901 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2902}
2903
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2904static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2906 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2907
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2909 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2911 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2912 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2913
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2914 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2917 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2918 Inst.addOperand(MCOperand::CreateImm(8 << size));
2919
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2920 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921}
2922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2923static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2924 uint64_t Address, const void *Decoder) {
2925 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2926 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2927}
2928
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2929static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2930 uint64_t Address, const void *Decoder) {
2931 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2932 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933}
2934
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2935static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2936 uint64_t Address, const void *Decoder) {
2937 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2938 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939}
2940
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2941static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942 uint64_t Address, const void *Decoder) {
2943 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2944 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2945}
2946
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2947static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2948 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2949 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2950
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2953 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2954 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2955 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2956 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2957 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2960 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2961 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2963 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2964 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2965
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2966 switch (Inst.getOpcode()) {
2967 case ARM::VTBL2:
2968 case ARM::VTBX2:
2969 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2970 return MCDisassembler::Fail;
2971 break;
2972 default:
2973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2974 return MCDisassembler::Fail;
2975 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2976
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2979
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2980 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2981}
2982
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2983static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2984 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2985 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2986
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2988 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2989
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2990 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2991 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2992
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2993 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2994 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2995 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2996 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2997 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2998 case ARM::tADDrSPi:
2999 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3000 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3001 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3002
3003 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3004 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3005}
3006
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3007static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3009 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3010 true, 2, Inst, Decoder))
3011 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3012 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013}
3014
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3015static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3016 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3017 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3018 true, 4, Inst, Decoder))
3019 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3020 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021}
3022
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3023static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3024 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3025 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3026 true, 2, Inst, Decoder))
3027 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3028 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3029}
3030
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3031static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3032 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3033 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3034
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3035 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3036 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3038 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3039 return MCDisassembler::Fail;
3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3041 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3042
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3043 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3044}
3045
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3046static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3047 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3048 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3049
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3051 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3052
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3053 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3054 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3055 Inst.addOperand(MCOperand::CreateImm(imm));
3056
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3057 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3058}
3059
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3060static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3061 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3062 unsigned imm = Val << 2;
3063
3064 Inst.addOperand(MCOperand::CreateImm(imm));
3065 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3067 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3068}
3069
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3070static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3071 uint64_t Address, const void *Decoder) {
3072 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3073 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3075 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3076}
3077
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3078static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3080 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3081
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3082 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3083 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3084 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3085
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3087 return MCDisassembler::Fail;
3088 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3090 Inst.addOperand(MCOperand::CreateImm(imm));
3091
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3092 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3093}
3094
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3095static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3096 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3097 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3098
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3099 switch (Inst.getOpcode()) {
3100 case ARM::t2PLDs:
3101 case ARM::t2PLDWs:
3102 case ARM::t2PLIs:
3103 break;
3104 default: {
3105 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3106 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3107 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3108 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3109 }
3110
3111 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3112 if (Rn == 0xF) {
3113 switch (Inst.getOpcode()) {
3114 case ARM::t2LDRBs:
3115 Inst.setOpcode(ARM::t2LDRBpci);
3116 break;
3117 case ARM::t2LDRHs:
3118 Inst.setOpcode(ARM::t2LDRHpci);
3119 break;
3120 case ARM::t2LDRSHs:
3121 Inst.setOpcode(ARM::t2LDRSHpci);
3122 break;
3123 case ARM::t2LDRSBs:
3124 Inst.setOpcode(ARM::t2LDRSBpci);
3125 break;
3126 case ARM::t2PLDs:
3127 Inst.setOpcode(ARM::t2PLDi12);
3128 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3129 break;
3130 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3131 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3132 }
3133
3134 int imm = fieldFromInstruction32(Insn, 0, 12);
3135 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3136 Inst.addOperand(MCOperand::CreateImm(imm));
3137
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3138 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3139 }
3140
3141 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3142 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3143 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3144 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3145 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3146
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3147 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3148}
3149
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3150static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3151 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3152 int imm = Val & 0xFF;
3153 if (!(Val & 0x100)) imm *= -1;
3154 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3155
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3156 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3157}
3158
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3159static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3160 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3161 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3162
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3163 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3164 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3165
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3167 return MCDisassembler::Fail;
3168 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3169 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3170
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3171 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3172}
3173
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3174static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3175 uint64_t Address, const void *Decoder) {
3176 DecodeStatus S = MCDisassembler::Success;
3177
3178 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3179 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3180
3181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3182 return MCDisassembler::Fail;
3183
3184 Inst.addOperand(MCOperand::CreateImm(imm));
3185
3186 return S;
3187}
3188
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3189static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3190 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3191 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3192 if (Val == 0)
3193 imm = INT32_MIN;
3194 else if (!(Val & 0x100))
3195 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3196 Inst.addOperand(MCOperand::CreateImm(imm));
3197
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3198 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3199}
3200
3201
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3202static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3203 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3204 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3205
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3206 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3207 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3208
3209 // Some instructions always use an additive offset.
3210 switch (Inst.getOpcode()) {
3211 case ARM::t2LDRT:
3212 case ARM::t2LDRBT:
3213 case ARM::t2LDRHT:
3214 case ARM::t2LDRSBT:
3215 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3216 case ARM::t2STRT:
3217 case ARM::t2STRBT:
3218 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3219 imm |= 0x100;
3220 break;
3221 default:
3222 break;
3223 }
3224
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3226 return MCDisassembler::Fail;
3227 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3228 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3229
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3230 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3231}
3232
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3233static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3234 uint64_t Address, const void *Decoder) {
3235 DecodeStatus S = MCDisassembler::Success;
3236
3237 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3238 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3239 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3240 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3241 addr |= Rn << 9;
3242 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3243
3244 if (!load) {
3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3246 return MCDisassembler::Fail;
3247 }
3248
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3249 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3250 return MCDisassembler::Fail;
3251
3252 if (load) {
3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3254 return MCDisassembler::Fail;
3255 }
3256
3257 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3258 return MCDisassembler::Fail;
3259
3260 return S;
3261}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3262
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3263static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3264 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3266
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3267 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3268 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3269
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3271 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3272 Inst.addOperand(MCOperand::CreateImm(imm));
3273
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3274 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3275}
3276
3277
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3278static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3279 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3280 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3281
3282 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3283 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3284 Inst.addOperand(MCOperand::CreateImm(imm));
3285
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3286 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3287}
3288
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3289static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3290 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3291 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3292
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3293 if (Inst.getOpcode() == ARM::tADDrSP) {
3294 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3295 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3296
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3298 return MCDisassembler::Fail;
3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3300 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3301 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3302 } else if (Inst.getOpcode() == ARM::tADDspr) {
3303 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3304
3305 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3306 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3308 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3309 }
3310
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3311 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3312}
3313
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3314static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3315 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3316 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3317 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3318
3319 Inst.addOperand(MCOperand::CreateImm(imod));
3320 Inst.addOperand(MCOperand::CreateImm(flags));
3321
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3322 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3323}
3324
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3325static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3326 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3327 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3329 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3330
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3331 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3332 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3333 Inst.addOperand(MCOperand::CreateImm(add));
3334
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3335 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3336}
3337
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3338static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3339 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3340 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3341 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3342 true, 4, Inst, Decoder))
3343 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3344 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3345}
3346
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3347static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3348 uint64_t Address, const void *Decoder) {
3349 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3350 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3351
3352 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3353 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3354}
3355
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3356static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3357DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3358 uint64_t Address, const void *Decoder) {
3359 DecodeStatus S = MCDisassembler::Success;
3360
3361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3363
3364 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3366 return MCDisassembler::Fail;
3367 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3368 return MCDisassembler::Fail;
3369 return S;
3370}
3371
3372static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3373DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3374 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3375 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3376
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3377 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3378 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3379 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3380 switch (opc) {
3381 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3382 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3383 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3384 Inst.setOpcode(ARM::t2DSB);
3385 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3386 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3387 Inst.setOpcode(ARM::t2DMB);
3388 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3389 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3390 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3391 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3392 }
3393
3394 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3395 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3396 }
3397
3398 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3399 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3400 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3401 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3402 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3403
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3404 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3405 return MCDisassembler::Fail;
3406 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3407 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3408
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3409 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3410}
3411
3412// Decode a shifted immediate operand. These basically consist
3413// of an 8-bit value, and a 4-bit directive that specifies either
3414// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3415static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3416 uint64_t Address, const void *Decoder) {
3417 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3418 if (ctrl == 0) {
3419 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3420 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3421 switch (byte) {
3422 case 0:
3423 Inst.addOperand(MCOperand::CreateImm(imm));
3424 break;
3425 case 1:
3426 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3427 break;
3428 case 2:
3429 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3430 break;
3431 case 3:
3432 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3433 (imm << 8) | imm));
3434 break;
3435 }
3436 } else {
3437 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3438 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3439 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3440 Inst.addOperand(MCOperand::CreateImm(imm));
3441 }
3442
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3443 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3444}
3445
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3446static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3447DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3448 uint64_t Address, const void *Decoder){
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3449 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3450 true, 2, Inst, Decoder))
3451 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3453}
3454
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3455static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3456 uint64_t Address, const void *Decoder){
Kevin Enderby09433032012-02-27 18:15:15 +0000[diff] [blame]3457 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3458 true, 4, Inst, Decoder))
3459 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3460 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3461}
3462
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3463static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3464 uint64_t Address, const void *Decoder) {
3465 switch (Val) {
3466 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3467 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3468 case 0xF: // SY
3469 case 0xE: // ST
3470 case 0xB: // ISH
3471 case 0xA: // ISHST
3472 case 0x7: // NSH
3473 case 0x6: // NSHST
3474 case 0x3: // OSH
3475 case 0x2: // OSHST
3476 break;
3477 }
3478
3479 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3480 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3481}
3482
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3483static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3484 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3485 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3486 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3487 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3488}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3489
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3490static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3491 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3492 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3493
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3494 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3495 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3496 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3497
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3498 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3499
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3501 return MCDisassembler::Fail;
3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3503 return MCDisassembler::Fail;
3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3505 return MCDisassembler::Fail;
3506 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3507 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3508
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3509 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3510}
3511
3512
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3513static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3514 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3515 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3516
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3517 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3518 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3519 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3520 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3522 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3523 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3524
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3525 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3526 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3529 return MCDisassembler::Fail;
3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3531 return MCDisassembler::Fail;
3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3535 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3536
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3537 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3538}
3539
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3540static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3541 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3542 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3543
3544 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3545 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3546 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3547 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3548 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3549 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3550
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3551 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3552
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3554 return MCDisassembler::Fail;
3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3556 return MCDisassembler::Fail;
3557 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3558 return MCDisassembler::Fail;
3559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3560 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3561
3562 return S;
3563}
3564
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3565static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3566 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3567 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3568
3569 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3570 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3571 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3572 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3573 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3574 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3576
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3577 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3578 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3579
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3581 return MCDisassembler::Fail;
3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3583 return MCDisassembler::Fail;
3584 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3585 return MCDisassembler::Fail;
3586 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3587 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3588
3589 return S;
3590}
3591
3592
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3593static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3594 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3595 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3596
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3597 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3598 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3599 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3600 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3601 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3602 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3603
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3604 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3605
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3607 return MCDisassembler::Fail;
3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3609 return MCDisassembler::Fail;
3610 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3611 return MCDisassembler::Fail;
3612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3613 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3614
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3615 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3616}
3617
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3618static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3619 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3620 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3621
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3622 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3623 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3624 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3625 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3626 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3627 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3628
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3629 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3630
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3632 return MCDisassembler::Fail;
3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3634 return MCDisassembler::Fail;
3635 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3638 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3639
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3640 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3641}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3642
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3643static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3644 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3645 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3646
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3647 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3648 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3649 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3650 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3651 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3652
3653 unsigned align = 0;
3654 unsigned index = 0;
3655 switch (size) {
3656 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 case 0:
3659 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3660 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3661 index = fieldFromInstruction32(Insn, 5, 3);
3662 break;
3663 case 1:
3664 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3665 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3666 index = fieldFromInstruction32(Insn, 6, 2);
3667 if (fieldFromInstruction32(Insn, 4, 1))
3668 align = 2;
3669 break;
3670 case 2:
3671 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3672 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3673 index = fieldFromInstruction32(Insn, 7, 1);
3674 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3675 align = 4;
3676 }
3677
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3679 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3680 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3682 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3683 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3685 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3686 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3687 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3688 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3690 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3691 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3692 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3693 }
3694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3696 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3697 Inst.addOperand(MCOperand::CreateImm(index));
3698
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3699 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3700}
3701
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3702static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3703 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3704 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3705
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3706 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3707 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3708 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3709 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3710 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3711
3712 unsigned align = 0;
3713 unsigned index = 0;
3714 switch (size) {
3715 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3716 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3717 case 0:
3718 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3719 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3720 index = fieldFromInstruction32(Insn, 5, 3);
3721 break;
3722 case 1:
3723 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3724 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3725 index = fieldFromInstruction32(Insn, 6, 2);
3726 if (fieldFromInstruction32(Insn, 4, 1))
3727 align = 2;
3728 break;
3729 case 2:
3730 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3731 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3732 index = fieldFromInstruction32(Insn, 7, 1);
3733 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3734 align = 4;
3735 }
3736
3737 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3739 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3740 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3743 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3744 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3745 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3747 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3748 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3749 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3750 }
3751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3753 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3754 Inst.addOperand(MCOperand::CreateImm(index));
3755
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3756 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757}
3758
3759
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3760static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3761 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3762 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3763
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3765 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3766 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3767 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3768 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3769
3770 unsigned align = 0;
3771 unsigned index = 0;
3772 unsigned inc = 1;
3773 switch (size) {
3774 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3775 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3776 case 0:
3777 index = fieldFromInstruction32(Insn, 5, 3);
3778 if (fieldFromInstruction32(Insn, 4, 1))
3779 align = 2;
3780 break;
3781 case 1:
3782 index = fieldFromInstruction32(Insn, 6, 2);
3783 if (fieldFromInstruction32(Insn, 4, 1))
3784 align = 4;
3785 if (fieldFromInstruction32(Insn, 5, 1))
3786 inc = 2;
3787 break;
3788 case 2:
3789 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3790 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3791 index = fieldFromInstruction32(Insn, 7, 1);
3792 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3793 align = 8;
3794 if (fieldFromInstruction32(Insn, 6, 1))
3795 inc = 2;
3796 break;
3797 }
3798
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3800 return MCDisassembler::Fail;
3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3802 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3803 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3805 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3806 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3808 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3809 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3810 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3811 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3813 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3814 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3815 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3816 }
3817
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3819 return MCDisassembler::Fail;
3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3821 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3822 Inst.addOperand(MCOperand::CreateImm(index));
3823
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3824 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3825}
3826
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3827static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3828 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3829 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3830
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3832 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3833 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3834 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3835 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3836
3837 unsigned align = 0;
3838 unsigned index = 0;
3839 unsigned inc = 1;
3840 switch (size) {
3841 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3842 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3843 case 0:
3844 index = fieldFromInstruction32(Insn, 5, 3);
3845 if (fieldFromInstruction32(Insn, 4, 1))
3846 align = 2;
3847 break;
3848 case 1:
3849 index = fieldFromInstruction32(Insn, 6, 2);
3850 if (fieldFromInstruction32(Insn, 4, 1))
3851 align = 4;
3852 if (fieldFromInstruction32(Insn, 5, 1))
3853 inc = 2;
3854 break;
3855 case 2:
3856 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3857 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3858 index = fieldFromInstruction32(Insn, 7, 1);
3859 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3860 align = 8;
3861 if (fieldFromInstruction32(Insn, 6, 1))
3862 inc = 2;
3863 break;
3864 }
3865
3866 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3868 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3869 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3871 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3873 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3874 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3876 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3877 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3878 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3879 }
3880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3882 return MCDisassembler::Fail;
3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3884 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3885 Inst.addOperand(MCOperand::CreateImm(index));
3886
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3887 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3888}
3889
3890
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3891static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3892 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3893 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3894
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3895 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3896 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3897 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3898 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3899 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3900
3901 unsigned align = 0;
3902 unsigned index = 0;
3903 unsigned inc = 1;
3904 switch (size) {
3905 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3906 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3907 case 0:
3908 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3909 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3910 index = fieldFromInstruction32(Insn, 5, 3);
3911 break;
3912 case 1:
3913 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3914 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3915 index = fieldFromInstruction32(Insn, 6, 2);
3916 if (fieldFromInstruction32(Insn, 5, 1))
3917 inc = 2;
3918 break;
3919 case 2:
3920 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3921 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3922 index = fieldFromInstruction32(Insn, 7, 1);
3923 if (fieldFromInstruction32(Insn, 6, 1))
3924 inc = 2;
3925 break;
3926 }
3927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3929 return MCDisassembler::Fail;
3930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3931 return MCDisassembler::Fail;
3932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3933 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3934
3935 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3937 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3938 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3940 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3941 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3942 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3943 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3945 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3946 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3947 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3948 }
3949
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3951 return MCDisassembler::Fail;
3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3953 return MCDisassembler::Fail;
3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3955 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3956 Inst.addOperand(MCOperand::CreateImm(index));
3957
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3958 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3959}
3960
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3961static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3962 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3963 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3964
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3965 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3966 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3969 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3970
3971 unsigned align = 0;
3972 unsigned index = 0;
3973 unsigned inc = 1;
3974 switch (size) {
3975 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3976 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3977 case 0:
3978 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3979 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3980 index = fieldFromInstruction32(Insn, 5, 3);
3981 break;
3982 case 1:
3983 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3984 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3985 index = fieldFromInstruction32(Insn, 6, 2);
3986 if (fieldFromInstruction32(Insn, 5, 1))
3987 inc = 2;
3988 break;
3989 case 2:
3990 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3991 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3992 index = fieldFromInstruction32(Insn, 7, 1);
3993 if (fieldFromInstruction32(Insn, 6, 1))
3994 inc = 2;
3995 break;
3996 }
3997
3998 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4000 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4001 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4003 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4004 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4005 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4006 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4008 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4009 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4010 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4011 }
4012
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4014 return MCDisassembler::Fail;
4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4016 return MCDisassembler::Fail;
4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4018 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4019 Inst.addOperand(MCOperand::CreateImm(index));
4020
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4021 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4022}
4023
4024
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4025static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4026 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4027 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4028
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4031 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4032 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4033 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4034
4035 unsigned align = 0;
4036 unsigned index = 0;
4037 unsigned inc = 1;
4038 switch (size) {
4039 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4040 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4041 case 0:
4042 if (fieldFromInstruction32(Insn, 4, 1))
4043 align = 4;
4044 index = fieldFromInstruction32(Insn, 5, 3);
4045 break;
4046 case 1:
4047 if (fieldFromInstruction32(Insn, 4, 1))
4048 align = 8;
4049 index = fieldFromInstruction32(Insn, 6, 2);
4050 if (fieldFromInstruction32(Insn, 5, 1))
4051 inc = 2;
4052 break;
4053 case 2:
4054 if (fieldFromInstruction32(Insn, 4, 2))
4055 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4056 index = fieldFromInstruction32(Insn, 7, 1);
4057 if (fieldFromInstruction32(Insn, 6, 1))
4058 inc = 2;
4059 break;
4060 }
4061
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4063 return MCDisassembler::Fail;
4064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4065 return MCDisassembler::Fail;
4066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4067 return MCDisassembler::Fail;
4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4069 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4070
4071 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4073 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4074 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4076 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4077 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4078 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4079 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4081 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4082 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4083 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4084 }
4085
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4087 return MCDisassembler::Fail;
4088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4089 return MCDisassembler::Fail;
4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4093 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4094 Inst.addOperand(MCOperand::CreateImm(index));
4095
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4096 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4097}
4098
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4099static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4100 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4101 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4102
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4103 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4104 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4105 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4106 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4107 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4108
4109 unsigned align = 0;
4110 unsigned index = 0;
4111 unsigned inc = 1;
4112 switch (size) {
4113 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4114 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4115 case 0:
4116 if (fieldFromInstruction32(Insn, 4, 1))
4117 align = 4;
4118 index = fieldFromInstruction32(Insn, 5, 3);
4119 break;
4120 case 1:
4121 if (fieldFromInstruction32(Insn, 4, 1))
4122 align = 8;
4123 index = fieldFromInstruction32(Insn, 6, 2);
4124 if (fieldFromInstruction32(Insn, 5, 1))
4125 inc = 2;
4126 break;
4127 case 2:
4128 if (fieldFromInstruction32(Insn, 4, 2))
4129 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4130 index = fieldFromInstruction32(Insn, 7, 1);
4131 if (fieldFromInstruction32(Insn, 6, 1))
4132 inc = 2;
4133 break;
4134 }
4135
4136 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4138 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4139 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4141 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4142 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4143 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4144 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4146 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4147 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4148 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4149 }
4150
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4152 return MCDisassembler::Fail;
4153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4154 return MCDisassembler::Fail;
4155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4156 return MCDisassembler::Fail;
4157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4158 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4159 Inst.addOperand(MCOperand::CreateImm(index));
4160
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4161 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4162}
4163
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4164static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4165 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4166 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4167 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4168 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4169 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4170 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4171 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4172
4173 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4174 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4175
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4176 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4183 return MCDisassembler::Fail;
4184 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4185 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4186
4187 return S;
4188}
4189
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4190static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4191 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4192 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4193 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4194 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4195 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4196 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4197 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4198
4199 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4200 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4201
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4205 return MCDisassembler::Fail;
4206 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4207 return MCDisassembler::Fail;
4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4211 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4212
4213 return S;
4214}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4215
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4216static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4217 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4218 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4219 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4220 // The InstPrinter needs to have the low bit of the predicate in
4221 // the mask operand to be able to print it properly.
4222 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4223
4224 if (pred == 0xF) {
4225 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4226 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4227 }
4228
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4229 if ((mask & 0xF) == 0) {
4230 // Preserve the high bit of the mask, which is the low bit of
4231 // the predicate.
4232 mask &= 0x10;
4233 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4234 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4235 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4236
4237 Inst.addOperand(MCOperand::CreateImm(pred));
4238 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4239 return S;
4240}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4241
4242static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4243DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4244 uint64_t Address, const void *Decoder) {
4245 DecodeStatus S = MCDisassembler::Success;
4246
4247 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4248 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4249 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4250 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4251 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4252 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4253 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4254 bool writeback = (W == 1) | (P == 0);
4255
4256 addr |= (U << 8) | (Rn << 9);
4257
4258 if (writeback && (Rn == Rt || Rn == Rt2))
4259 Check(S, MCDisassembler::SoftFail);
4260 if (Rt == Rt2)
4261 Check(S, MCDisassembler::SoftFail);
4262
4263 // Rt
4264 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4265 return MCDisassembler::Fail;
4266 // Rt2
4267 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4268 return MCDisassembler::Fail;
4269 // Writeback operand
4270 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4271 return MCDisassembler::Fail;
4272 // addr
4273 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4274 return MCDisassembler::Fail;
4275
4276 return S;
4277}
4278
4279static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4280DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4281 uint64_t Address, const void *Decoder) {
4282 DecodeStatus S = MCDisassembler::Success;
4283
4284 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4285 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4287 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4288 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4289 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4290 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4291 bool writeback = (W == 1) | (P == 0);
4292
4293 addr |= (U << 8) | (Rn << 9);
4294
4295 if (writeback && (Rn == Rt || Rn == Rt2))
4296 Check(S, MCDisassembler::SoftFail);
4297
4298 // Writeback operand
4299 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4300 return MCDisassembler::Fail;
4301 // Rt
4302 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4303 return MCDisassembler::Fail;
4304 // Rt2
4305 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4306 return MCDisassembler::Fail;
4307 // addr
4308 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4309 return MCDisassembler::Fail;
4310
4311 return S;
4312}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4313
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4314static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4315 uint64_t Address, const void *Decoder) {
4316 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4317 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4318 if (sign1 != sign2) return MCDisassembler::Fail;
4319
4320 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4321 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4322 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4323 Val |= sign1 << 12;
4324 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4325
4326 return MCDisassembler::Success;
4327}
4328
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4329static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4330 uint64_t Address,
4331 const void *Decoder) {
4332 DecodeStatus S = MCDisassembler::Success;
4333
4334 // Shift of "asr #32" is not allowed in Thumb2 mode.
4335 if (Val == 0x20) S = MCDisassembler::SoftFail;
4336 Inst.addOperand(MCOperand::CreateImm(Val));
4337 return S;
4338}
4339
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4340static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4341 uint64_t Address, const void *Decoder) {
4342 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4343 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4344 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4345 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4346
4347 if (pred == 0xF)
4348 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4349
4350 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4351
4352 if (Rt == Rn || Rn == Rt2)
4353 S = MCDisassembler::SoftFail;
4354
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4355 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4356 return MCDisassembler::Fail;
4357 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4362 return MCDisassembler::Fail;
4363
4364 return S;
4365}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4366
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4367static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4368 uint64_t Address, const void *Decoder) {
4369 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4370 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4371 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4372 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4373 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4374 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4375
4376 DecodeStatus S = MCDisassembler::Success;
4377
4378 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4379 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4380 Inst.setOpcode(ARM::VMOVv2f32);
4381 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4382 }
4383
4384 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4385
4386 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4389 return MCDisassembler::Fail;
4390 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4391
4392 return S;
4393}
4394
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4395static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4396 uint64_t Address, const void *Decoder) {
4397 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4398 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4399 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4400 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4401 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4402 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4403
4404 DecodeStatus S = MCDisassembler::Success;
4405
4406 // VMOVv4f32 is ambiguous with these decodings.
4407 if (!(imm & 0x38) && cmode == 0xF) {
4408 Inst.setOpcode(ARM::VMOVv4f32);
4409 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4410 }
4411
4412 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4413
4414 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4415 return MCDisassembler::Fail;
4416 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4417 return MCDisassembler::Fail;
4418 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4419
4420 return S;
4421}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4422
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4423static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4424 uint64_t Address, const void *Decoder) {
4425 DecodeStatus S = MCDisassembler::Success;
4426
4427 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4428 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4429 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4430 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4431 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4432
4433 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4434 S = MCDisassembler::SoftFail;
4435
4436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4437 return MCDisassembler::Fail;
4438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4439 return MCDisassembler::Fail;
4440 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4441 return MCDisassembler::Fail;
4442 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4443 return MCDisassembler::Fail;
4444 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4445 return MCDisassembler::Fail;
4446
4447 return S;
4448}
4449
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4450static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4451 uint64_t Address, const void *Decoder) {
4452
4453 DecodeStatus S = MCDisassembler::Success;
4454
4455 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4456 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4457 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4458 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4459 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4460
4461 if ((cop & ~0x1) == 0xa)
4462 return MCDisassembler::Fail;
4463
4464 if (Rt == Rt2)
4465 S = MCDisassembler::SoftFail;
4466
4467 Inst.addOperand(MCOperand::CreateImm(cop));
4468 Inst.addOperand(MCOperand::CreateImm(opc1));
4469 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4470 return MCDisassembler::Fail;
4471 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4472 return MCDisassembler::Fail;
4473 Inst.addOperand(MCOperand::CreateImm(CRm));
4474
4475 return S;
4476}
4477