Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Chris Lattner and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "X86.h" |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 16 | #include "X86InstrBuilder.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 17 | #include "X86ISelLowering.h" |
| 18 | #include "X86TargetMachine.h" |
| 19 | #include "llvm/CallingConv.h" |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 20 | #include "llvm/Constants.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 21 | #include "llvm/Function.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/SelectionDAG.h" |
| 26 | #include "llvm/CodeGen/SSARegMap.h" |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 27 | #include "llvm/Support/MathExtras.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 28 | #include "llvm/Target/TargetOptions.h" |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 29 | #include "llvm/ADT/VectorExtras.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 30 | using namespace llvm; |
| 31 | |
| 32 | // FIXME: temporary. |
| 33 | #include "llvm/Support/CommandLine.h" |
| 34 | static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, |
| 35 | cl::desc("Enable fastcc on X86")); |
| 36 | |
| 37 | X86TargetLowering::X86TargetLowering(TargetMachine &TM) |
| 38 | : TargetLowering(TM) { |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 39 | Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 40 | X86ScalarSSE = Subtarget->hasSSE2(); |
| 41 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 42 | // Set up the TargetLowering object. |
| 43 | |
| 44 | // X86 is weird, it always uses i8 for shift amounts and setcc results. |
| 45 | setShiftAmountType(MVT::i8); |
| 46 | setSetCCResultType(MVT::i8); |
| 47 | setSetCCResultContents(ZeroOrOneSetCCResult); |
Evan Cheng | 0b2afbd | 2006-01-25 09:15:17 +0000 | [diff] [blame] | 48 | setSchedulingPreference(SchedulingForRegPressure); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 49 | setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 |
Chris Lattner | 9edba76 | 2006-01-13 18:00:54 +0000 | [diff] [blame] | 50 | setStackPointerRegisterToSaveRestore(X86::ESP); |
Chris Lattner | a54aa94 | 2006-01-29 06:26:08 +0000 | [diff] [blame] | 51 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 52 | // Set up the register classes. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 53 | addRegisterClass(MVT::i8, X86::R8RegisterClass); |
| 54 | addRegisterClass(MVT::i16, X86::R16RegisterClass); |
| 55 | addRegisterClass(MVT::i32, X86::R32RegisterClass); |
| 56 | |
| 57 | // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this |
| 58 | // operation. |
| 59 | setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); |
| 60 | setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); |
| 61 | setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); |
Evan Cheng | 6892f28 | 2006-01-17 02:32:49 +0000 | [diff] [blame] | 62 | |
| 63 | if (X86ScalarSSE) |
| 64 | // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead. |
| 65 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); |
| 66 | else |
| 67 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 68 | |
| 69 | // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have |
| 70 | // this operation. |
| 71 | setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); |
| 72 | setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 73 | // SSE has no i16 to fp conversion, only i32 |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 74 | if (X86ScalarSSE) |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 75 | setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 76 | else { |
| 77 | setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); |
| 78 | setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); |
| 79 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 80 | |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 81 | // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64 |
| 82 | // isn't legal. |
| 83 | setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); |
| 84 | setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); |
| 85 | |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 86 | // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have |
| 87 | // this operation. |
| 88 | setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); |
| 89 | setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); |
| 90 | |
| 91 | if (X86ScalarSSE) { |
| 92 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); |
| 93 | } else { |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 94 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 95 | setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | // Handle FP_TO_UINT by promoting the destination to a larger signed |
| 99 | // conversion. |
| 100 | setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); |
| 101 | setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); |
| 102 | setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); |
| 103 | |
Evan Cheng | 45af8fd | 2006-02-18 07:26:17 +0000 | [diff] [blame] | 104 | if (X86ScalarSSE && !Subtarget->hasSSE3()) |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 105 | // Expand FP_TO_UINT into a select. |
| 106 | // FIXME: We would like to use a Custom expander here eventually to do |
| 107 | // the optimal thing for SSE vs. the default expansion in the legalizer. |
| 108 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); |
| 109 | else |
Evan Cheng | 45af8fd | 2006-02-18 07:26:17 +0000 | [diff] [blame] | 110 | // With SSE3 we can use fisttpll to convert to a signed i64. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 111 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); |
| 112 | |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 113 | setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); |
| 114 | setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); |
Chris Lattner | 21f6685 | 2005-12-23 05:15:23 +0000 | [diff] [blame] | 115 | |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 116 | setOperationAction(ISD::BRCOND , MVT::Other, Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 117 | setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); |
| 118 | setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 119 | setOperationAction(ISD::BR_CC , MVT::Other, Expand); |
| 120 | setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 121 | setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); |
| 122 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); |
Chris Lattner | e80242a | 2005-12-07 17:59:14 +0000 | [diff] [blame] | 123 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 124 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); |
| 125 | setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); |
| 126 | setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); |
| 127 | setOperationAction(ISD::FREM , MVT::f64 , Expand); |
| 128 | setOperationAction(ISD::CTPOP , MVT::i8 , Expand); |
| 129 | setOperationAction(ISD::CTTZ , MVT::i8 , Expand); |
| 130 | setOperationAction(ISD::CTLZ , MVT::i8 , Expand); |
| 131 | setOperationAction(ISD::CTPOP , MVT::i16 , Expand); |
| 132 | setOperationAction(ISD::CTTZ , MVT::i16 , Expand); |
| 133 | setOperationAction(ISD::CTLZ , MVT::i16 , Expand); |
| 134 | setOperationAction(ISD::CTPOP , MVT::i32 , Expand); |
| 135 | setOperationAction(ISD::CTTZ , MVT::i32 , Expand); |
| 136 | setOperationAction(ISD::CTLZ , MVT::i32 , Expand); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 137 | setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 138 | setOperationAction(ISD::BSWAP , MVT::i16 , Expand); |
Nate Begeman | 35ef913 | 2006-01-11 21:21:00 +0000 | [diff] [blame] | 139 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 140 | setOperationAction(ISD::READIO , MVT::i1 , Expand); |
| 141 | setOperationAction(ISD::READIO , MVT::i8 , Expand); |
| 142 | setOperationAction(ISD::READIO , MVT::i16 , Expand); |
| 143 | setOperationAction(ISD::READIO , MVT::i32 , Expand); |
| 144 | setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); |
| 145 | setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); |
| 146 | setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); |
| 147 | setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); |
| 148 | |
| 149 | // These should be promoted to a larger select which is supported. |
| 150 | setOperationAction(ISD::SELECT , MVT::i1 , Promote); |
| 151 | setOperationAction(ISD::SELECT , MVT::i8 , Promote); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 152 | |
| 153 | // X86 wants to expand cmov itself. |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 154 | setOperationAction(ISD::SELECT , MVT::i16 , Custom); |
| 155 | setOperationAction(ISD::SELECT , MVT::i32 , Custom); |
| 156 | setOperationAction(ISD::SELECT , MVT::f32 , Custom); |
| 157 | setOperationAction(ISD::SELECT , MVT::f64 , Custom); |
| 158 | setOperationAction(ISD::SETCC , MVT::i8 , Custom); |
| 159 | setOperationAction(ISD::SETCC , MVT::i16 , Custom); |
| 160 | setOperationAction(ISD::SETCC , MVT::i32 , Custom); |
| 161 | setOperationAction(ISD::SETCC , MVT::f32 , Custom); |
| 162 | setOperationAction(ISD::SETCC , MVT::f64 , Custom); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 163 | // X86 ret instruction may pop stack. |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 164 | setOperationAction(ISD::RET , MVT::Other, Custom); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 165 | // Darwin ABI issue. |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 166 | setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 167 | setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 168 | setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 169 | // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 170 | setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); |
| 171 | setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); |
| 172 | setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 173 | // X86 wants to expand memset / memcpy itself. |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 174 | setOperationAction(ISD::MEMSET , MVT::Other, Custom); |
| 175 | setOperationAction(ISD::MEMCPY , MVT::Other, Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 176 | |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 177 | // We don't have line number support yet. |
| 178 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
Jim Laskey | e0bce71 | 2006-01-05 01:47:43 +0000 | [diff] [blame] | 179 | setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); |
| 180 | setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 181 | |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 182 | // VASTART needs to be custom lowered to use the VarArgsFrameIndex |
| 183 | setOperationAction(ISD::VASTART , MVT::Other, Custom); |
| 184 | |
| 185 | // Use the default implementation. |
| 186 | setOperationAction(ISD::VAARG , MVT::Other, Expand); |
| 187 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); |
| 188 | setOperationAction(ISD::VAEND , MVT::Other, Expand); |
Chris Lattner | e112552 | 2006-01-15 09:00:21 +0000 | [diff] [blame] | 189 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| 190 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| 191 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); |
Chris Lattner | b99329e | 2006-01-13 02:42:53 +0000 | [diff] [blame] | 192 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 193 | if (X86ScalarSSE) { |
| 194 | // Set up the FP register classes. |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 195 | addRegisterClass(MVT::f32, X86::FR32RegisterClass); |
| 196 | addRegisterClass(MVT::f64, X86::FR64RegisterClass); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 197 | |
| 198 | // SSE has no load+extend ops |
| 199 | setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); |
| 200 | setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); |
| 201 | |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 202 | // Use ANDPD to simulate FABS. |
| 203 | setOperationAction(ISD::FABS , MVT::f64, Custom); |
| 204 | setOperationAction(ISD::FABS , MVT::f32, Custom); |
| 205 | |
| 206 | // Use XORP to simulate FNEG. |
| 207 | setOperationAction(ISD::FNEG , MVT::f64, Custom); |
| 208 | setOperationAction(ISD::FNEG , MVT::f32, Custom); |
| 209 | |
Evan Cheng | d25e9e8 | 2006-02-02 00:28:23 +0000 | [diff] [blame] | 210 | // We don't support sin/cos/fmod |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 211 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 212 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 213 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
| 214 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 215 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 216 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
| 217 | |
Chris Lattner | a54aa94 | 2006-01-29 06:26:08 +0000 | [diff] [blame] | 218 | // Expand FP immediates into loads from the stack, except for the special |
| 219 | // cases we handle. |
| 220 | setOperationAction(ISD::ConstantFP, MVT::f64, Expand); |
| 221 | setOperationAction(ISD::ConstantFP, MVT::f32, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 222 | addLegalFPImmediate(+0.0); // xorps / xorpd |
| 223 | } else { |
| 224 | // Set up the FP register classes. |
| 225 | addRegisterClass(MVT::f64, X86::RFPRegisterClass); |
Chris Lattner | 44d9b9b | 2006-01-29 06:44:22 +0000 | [diff] [blame] | 226 | |
| 227 | setOperationAction(ISD::UNDEF, MVT::f64, Expand); |
| 228 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 229 | if (!UnsafeFPMath) { |
| 230 | setOperationAction(ISD::FSIN , MVT::f64 , Expand); |
| 231 | setOperationAction(ISD::FCOS , MVT::f64 , Expand); |
| 232 | } |
| 233 | |
Chris Lattner | a54aa94 | 2006-01-29 06:26:08 +0000 | [diff] [blame] | 234 | setOperationAction(ISD::ConstantFP, MVT::f64, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 235 | addLegalFPImmediate(+0.0); // FLD0 |
| 236 | addLegalFPImmediate(+1.0); // FLD1 |
| 237 | addLegalFPImmediate(-0.0); // FLD0/FCHS |
| 238 | addLegalFPImmediate(-1.0); // FLD1/FCHS |
| 239 | } |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 240 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame^] | 241 | // First set operation action for all vector types to expand. Then we |
| 242 | // will selectively turn on ones that can be effectively codegen'd. |
| 243 | for (unsigned VT = (unsigned)MVT::Vector + 1; |
| 244 | VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { |
| 245 | setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); |
| 246 | setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); |
| 247 | setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); |
| 248 | setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); |
| 249 | } |
| 250 | |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 251 | if (TM.getSubtarget<X86Subtarget>().hasMMX()) { |
| 252 | addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); |
| 253 | addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); |
| 254 | addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); |
| 255 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame^] | 256 | // FIXME: add MMX packed arithmetics |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 257 | setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand); |
| 258 | setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand); |
| 259 | setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand); |
| 260 | } |
| 261 | |
| 262 | if (TM.getSubtarget<X86Subtarget>().hasSSE1()) { |
| 263 | addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); |
| 264 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame^] | 265 | setOperationAction(ISD::ADD , MVT::v4f32, Legal); |
| 266 | setOperationAction(ISD::SUB , MVT::v4f32, Legal); |
| 267 | setOperationAction(ISD::MUL , MVT::v4f32, Legal); |
| 268 | setOperationAction(ISD::LOAD , MVT::v4f32, Legal); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 269 | setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); |
| 270 | } |
| 271 | |
| 272 | if (TM.getSubtarget<X86Subtarget>().hasSSE2()) { |
| 273 | addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); |
| 274 | addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); |
| 275 | addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); |
| 276 | addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); |
| 277 | addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); |
| 278 | |
| 279 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame^] | 280 | setOperationAction(ISD::ADD , MVT::v2f64, Legal); |
| 281 | setOperationAction(ISD::SUB , MVT::v2f64, Legal); |
| 282 | setOperationAction(ISD::MUL , MVT::v2f64, Legal); |
| 283 | setOperationAction(ISD::LOAD , MVT::v2f64, Legal); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 284 | setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand); |
| 285 | setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand); |
| 286 | setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand); |
| 287 | setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); |
| 288 | setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand); |
| 289 | } |
| 290 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 291 | computeRegisterProperties(); |
| 292 | |
Evan Cheng | 87ed716 | 2006-02-14 08:25:08 +0000 | [diff] [blame] | 293 | // FIXME: These should be based on subtarget info. Plus, the values should |
| 294 | // be smaller when we are in optimizing for size mode. |
Evan Cheng | a03a5dc | 2006-02-14 08:38:30 +0000 | [diff] [blame] | 295 | maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores |
| 296 | maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores |
| 297 | maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 298 | allowUnalignedMemoryAccesses = true; // x86 supports it! |
| 299 | } |
| 300 | |
| 301 | std::vector<SDOperand> |
| 302 | X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { |
| 303 | if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) |
| 304 | return LowerFastCCArguments(F, DAG); |
| 305 | return LowerCCCArguments(F, DAG); |
| 306 | } |
| 307 | |
| 308 | std::pair<SDOperand, SDOperand> |
| 309 | X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, |
| 310 | bool isVarArg, unsigned CallingConv, |
| 311 | bool isTailCall, |
| 312 | SDOperand Callee, ArgListTy &Args, |
| 313 | SelectionDAG &DAG) { |
| 314 | assert((!isVarArg || CallingConv == CallingConv::C) && |
| 315 | "Only C takes varargs!"); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 316 | |
| 317 | // If the callee is a GlobalAddress node (quite common, every direct call is) |
| 318 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. |
| 319 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
| 320 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 321 | else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) |
| 322 | Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 323 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 324 | if (CallingConv == CallingConv::Fast && EnableFastCC) |
| 325 | return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); |
| 326 | return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); |
| 327 | } |
| 328 | |
| 329 | //===----------------------------------------------------------------------===// |
| 330 | // C Calling Convention implementation |
| 331 | //===----------------------------------------------------------------------===// |
| 332 | |
| 333 | std::vector<SDOperand> |
| 334 | X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { |
| 335 | std::vector<SDOperand> ArgValues; |
| 336 | |
| 337 | MachineFunction &MF = DAG.getMachineFunction(); |
| 338 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 339 | |
| 340 | // Add DAG nodes to load the arguments... On entry to a function on the X86, |
| 341 | // the stack frame looks like this: |
| 342 | // |
| 343 | // [ESP] -- return address |
| 344 | // [ESP + 4] -- first argument (leftmost lexically) |
| 345 | // [ESP + 8] -- second argument, if first argument is four bytes in size |
| 346 | // ... |
| 347 | // |
| 348 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 349 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 350 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 351 | unsigned ArgIncrement = 4; |
| 352 | unsigned ObjSize; |
| 353 | switch (ObjectVT) { |
| 354 | default: assert(0 && "Unhandled argument type!"); |
| 355 | case MVT::i1: |
| 356 | case MVT::i8: ObjSize = 1; break; |
| 357 | case MVT::i16: ObjSize = 2; break; |
| 358 | case MVT::i32: ObjSize = 4; break; |
| 359 | case MVT::i64: ObjSize = ArgIncrement = 8; break; |
| 360 | case MVT::f32: ObjSize = 4; break; |
| 361 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 362 | } |
| 363 | // Create the frame index object for this incoming parameter... |
| 364 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 365 | |
| 366 | // Create the SelectionDAG nodes corresponding to a load from this parameter |
| 367 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 368 | |
| 369 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 370 | // dead loads. |
| 371 | SDOperand ArgValue; |
| 372 | if (!I->use_empty()) |
| 373 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 374 | DAG.getSrcValue(NULL)); |
| 375 | else { |
| 376 | if (MVT::isInteger(ObjectVT)) |
| 377 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 378 | else |
| 379 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 380 | } |
| 381 | ArgValues.push_back(ArgValue); |
| 382 | |
| 383 | ArgOffset += ArgIncrement; // Move on to the next argument... |
| 384 | } |
| 385 | |
| 386 | // If the function takes variable number of arguments, make a frame index for |
| 387 | // the start of the first vararg value... for expansion of llvm.va_start. |
| 388 | if (F.isVarArg()) |
| 389 | VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); |
| 390 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 391 | BytesToPopOnReturn = 0; // Callee pops nothing. |
| 392 | BytesCallerReserves = ArgOffset; |
| 393 | |
| 394 | // Finally, inform the code generator which regs we return values in. |
| 395 | switch (getValueType(F.getReturnType())) { |
| 396 | default: assert(0 && "Unknown type!"); |
| 397 | case MVT::isVoid: break; |
| 398 | case MVT::i1: |
| 399 | case MVT::i8: |
| 400 | case MVT::i16: |
| 401 | case MVT::i32: |
| 402 | MF.addLiveOut(X86::EAX); |
| 403 | break; |
| 404 | case MVT::i64: |
| 405 | MF.addLiveOut(X86::EAX); |
| 406 | MF.addLiveOut(X86::EDX); |
| 407 | break; |
| 408 | case MVT::f32: |
| 409 | case MVT::f64: |
| 410 | MF.addLiveOut(X86::ST0); |
| 411 | break; |
| 412 | } |
| 413 | return ArgValues; |
| 414 | } |
| 415 | |
| 416 | std::pair<SDOperand, SDOperand> |
| 417 | X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, |
| 418 | bool isVarArg, bool isTailCall, |
| 419 | SDOperand Callee, ArgListTy &Args, |
| 420 | SelectionDAG &DAG) { |
| 421 | // Count how many bytes are to be pushed on the stack. |
| 422 | unsigned NumBytes = 0; |
| 423 | |
| 424 | if (Args.empty()) { |
| 425 | // Save zero bytes. |
Chris Lattner | 94dd292 | 2006-02-13 09:00:43 +0000 | [diff] [blame] | 426 | Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy())); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 427 | } else { |
| 428 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 429 | switch (getValueType(Args[i].second)) { |
| 430 | default: assert(0 && "Unknown value type!"); |
| 431 | case MVT::i1: |
| 432 | case MVT::i8: |
| 433 | case MVT::i16: |
| 434 | case MVT::i32: |
| 435 | case MVT::f32: |
| 436 | NumBytes += 4; |
| 437 | break; |
| 438 | case MVT::i64: |
| 439 | case MVT::f64: |
| 440 | NumBytes += 8; |
| 441 | break; |
| 442 | } |
| 443 | |
Chris Lattner | 94dd292 | 2006-02-13 09:00:43 +0000 | [diff] [blame] | 444 | Chain = DAG.getCALLSEQ_START(Chain, |
| 445 | DAG.getConstant(NumBytes, getPointerTy())); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 446 | |
| 447 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 448 | unsigned ArgOffset = 0; |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 449 | SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 450 | std::vector<SDOperand> Stores; |
| 451 | |
| 452 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 453 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 454 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 455 | |
| 456 | switch (getValueType(Args[i].second)) { |
| 457 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 458 | case MVT::i1: |
| 459 | case MVT::i8: |
| 460 | case MVT::i16: |
| 461 | // Promote the integer to 32 bits. If the input type is signed use a |
| 462 | // sign extend, otherwise use a zero extend. |
| 463 | if (Args[i].second->isSigned()) |
| 464 | Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); |
| 465 | else |
| 466 | Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); |
| 467 | |
| 468 | // FALL THROUGH |
| 469 | case MVT::i32: |
| 470 | case MVT::f32: |
| 471 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 472 | Args[i].first, PtrOff, |
| 473 | DAG.getSrcValue(NULL))); |
| 474 | ArgOffset += 4; |
| 475 | break; |
| 476 | case MVT::i64: |
| 477 | case MVT::f64: |
| 478 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 479 | Args[i].first, PtrOff, |
| 480 | DAG.getSrcValue(NULL))); |
| 481 | ArgOffset += 8; |
| 482 | break; |
| 483 | } |
| 484 | } |
| 485 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 486 | } |
| 487 | |
| 488 | std::vector<MVT::ValueType> RetVals; |
| 489 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 490 | RetVals.push_back(MVT::Other); |
| 491 | |
| 492 | // The result values produced have to be legal. Promote the result. |
| 493 | switch (RetTyVT) { |
| 494 | case MVT::isVoid: break; |
| 495 | default: |
| 496 | RetVals.push_back(RetTyVT); |
| 497 | break; |
| 498 | case MVT::i1: |
| 499 | case MVT::i8: |
| 500 | case MVT::i16: |
| 501 | RetVals.push_back(MVT::i32); |
| 502 | break; |
| 503 | case MVT::f32: |
| 504 | if (X86ScalarSSE) |
| 505 | RetVals.push_back(MVT::f32); |
| 506 | else |
| 507 | RetVals.push_back(MVT::f64); |
| 508 | break; |
| 509 | case MVT::i64: |
| 510 | RetVals.push_back(MVT::i32); |
| 511 | RetVals.push_back(MVT::i32); |
| 512 | break; |
| 513 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 514 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 515 | std::vector<MVT::ValueType> NodeTys; |
| 516 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 517 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 518 | std::vector<SDOperand> Ops; |
| 519 | Ops.push_back(Chain); |
| 520 | Ops.push_back(Callee); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 521 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 522 | // FIXME: Do not generate X86ISD::TAILCALL for now. |
| 523 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); |
| 524 | SDOperand InFlag = Chain.getValue(1); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 525 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 526 | NodeTys.clear(); |
| 527 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 528 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 529 | Ops.clear(); |
| 530 | Ops.push_back(Chain); |
| 531 | Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); |
| 532 | Ops.push_back(DAG.getConstant(0, getPointerTy())); |
| 533 | Ops.push_back(InFlag); |
| 534 | Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops); |
| 535 | InFlag = Chain.getValue(1); |
| 536 | |
| 537 | SDOperand RetVal; |
| 538 | if (RetTyVT != MVT::isVoid) { |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 539 | switch (RetTyVT) { |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 540 | default: assert(0 && "Unknown value type to return!"); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 541 | case MVT::i1: |
| 542 | case MVT::i8: |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 543 | RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); |
| 544 | Chain = RetVal.getValue(1); |
| 545 | if (RetTyVT == MVT::i1) |
| 546 | RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal); |
| 547 | break; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 548 | case MVT::i16: |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 549 | RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); |
| 550 | Chain = RetVal.getValue(1); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 551 | break; |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 552 | case MVT::i32: |
| 553 | RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 554 | Chain = RetVal.getValue(1); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 555 | break; |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 556 | case MVT::i64: { |
| 557 | SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 558 | SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, |
| 559 | Lo.getValue(2)); |
| 560 | RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 561 | Chain = Hi.getValue(1); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 562 | break; |
| 563 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 564 | case MVT::f32: |
| 565 | case MVT::f64: { |
| 566 | std::vector<MVT::ValueType> Tys; |
| 567 | Tys.push_back(MVT::f64); |
| 568 | Tys.push_back(MVT::Other); |
| 569 | Tys.push_back(MVT::Flag); |
| 570 | std::vector<SDOperand> Ops; |
| 571 | Ops.push_back(Chain); |
| 572 | Ops.push_back(InFlag); |
| 573 | RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); |
| 574 | Chain = RetVal.getValue(1); |
| 575 | InFlag = RetVal.getValue(2); |
| 576 | if (X86ScalarSSE) { |
| 577 | // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This |
| 578 | // shouldn't be necessary except that RFP cannot be live across |
| 579 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
| 580 | MachineFunction &MF = DAG.getMachineFunction(); |
| 581 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
| 582 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 583 | Tys.clear(); |
| 584 | Tys.push_back(MVT::Other); |
| 585 | Ops.clear(); |
| 586 | Ops.push_back(Chain); |
| 587 | Ops.push_back(RetVal); |
| 588 | Ops.push_back(StackSlot); |
| 589 | Ops.push_back(DAG.getValueType(RetTyVT)); |
| 590 | Ops.push_back(InFlag); |
| 591 | Chain = DAG.getNode(X86ISD::FST, Tys, Ops); |
| 592 | RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, |
| 593 | DAG.getSrcValue(NULL)); |
| 594 | Chain = RetVal.getValue(1); |
| 595 | } |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 596 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 597 | if (RetTyVT == MVT::f32 && !X86ScalarSSE) |
| 598 | // FIXME: we would really like to remember that this FP_ROUND |
| 599 | // operation is okay to eliminate if we allow excess FP precision. |
| 600 | RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); |
| 601 | break; |
| 602 | } |
| 603 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 604 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 605 | |
| 606 | return std::make_pair(RetVal, Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 607 | } |
| 608 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 609 | //===----------------------------------------------------------------------===// |
| 610 | // Fast Calling Convention implementation |
| 611 | //===----------------------------------------------------------------------===// |
| 612 | // |
| 613 | // The X86 'fast' calling convention passes up to two integer arguments in |
| 614 | // registers (an appropriate portion of EAX/EDX), passes arguments in C order, |
| 615 | // and requires that the callee pop its arguments off the stack (allowing proper |
| 616 | // tail calls), and has the same return value conventions as C calling convs. |
| 617 | // |
| 618 | // This calling convention always arranges for the callee pop value to be 8n+4 |
| 619 | // bytes, which is needed for tail recursion elimination and stack alignment |
| 620 | // reasons. |
| 621 | // |
| 622 | // Note that this can be enhanced in the future to pass fp vals in registers |
| 623 | // (when we have a global fp allocator) and do other tricks. |
| 624 | // |
| 625 | |
| 626 | /// AddLiveIn - This helper function adds the specified physical register to the |
| 627 | /// MachineFunction as a live in value. It also creates a corresponding virtual |
| 628 | /// register for it. |
| 629 | static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, |
| 630 | TargetRegisterClass *RC) { |
| 631 | assert(RC->contains(PReg) && "Not the correct regclass!"); |
| 632 | unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); |
| 633 | MF.addLiveIn(PReg, VReg); |
| 634 | return VReg; |
| 635 | } |
| 636 | |
| 637 | |
| 638 | std::vector<SDOperand> |
| 639 | X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { |
| 640 | std::vector<SDOperand> ArgValues; |
| 641 | |
| 642 | MachineFunction &MF = DAG.getMachineFunction(); |
| 643 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 644 | |
| 645 | // Add DAG nodes to load the arguments... On entry to a function the stack |
| 646 | // frame looks like this: |
| 647 | // |
| 648 | // [ESP] -- return address |
| 649 | // [ESP + 4] -- first nonreg argument (leftmost lexically) |
| 650 | // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size |
| 651 | // ... |
| 652 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 653 | |
| 654 | // Keep track of the number of integer regs passed so far. This can be either |
| 655 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 656 | // used). |
| 657 | unsigned NumIntRegs = 0; |
| 658 | |
| 659 | for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { |
| 660 | MVT::ValueType ObjectVT = getValueType(I->getType()); |
| 661 | unsigned ArgIncrement = 4; |
| 662 | unsigned ObjSize = 0; |
| 663 | SDOperand ArgValue; |
| 664 | |
| 665 | switch (ObjectVT) { |
| 666 | default: assert(0 && "Unhandled argument type!"); |
| 667 | case MVT::i1: |
| 668 | case MVT::i8: |
| 669 | if (NumIntRegs < 2) { |
| 670 | if (!I->use_empty()) { |
| 671 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, |
| 672 | X86::R8RegisterClass); |
| 673 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); |
| 674 | DAG.setRoot(ArgValue.getValue(1)); |
Chris Lattner | f31d193 | 2005-12-27 03:02:18 +0000 | [diff] [blame] | 675 | if (ObjectVT == MVT::i1) |
| 676 | // FIXME: Should insert a assertzext here. |
| 677 | ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 678 | } |
| 679 | ++NumIntRegs; |
| 680 | break; |
| 681 | } |
| 682 | |
| 683 | ObjSize = 1; |
| 684 | break; |
| 685 | case MVT::i16: |
| 686 | if (NumIntRegs < 2) { |
| 687 | if (!I->use_empty()) { |
| 688 | unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, |
| 689 | X86::R16RegisterClass); |
| 690 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); |
| 691 | DAG.setRoot(ArgValue.getValue(1)); |
| 692 | } |
| 693 | ++NumIntRegs; |
| 694 | break; |
| 695 | } |
| 696 | ObjSize = 2; |
| 697 | break; |
| 698 | case MVT::i32: |
| 699 | if (NumIntRegs < 2) { |
| 700 | if (!I->use_empty()) { |
| 701 | unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, |
| 702 | X86::R32RegisterClass); |
| 703 | ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); |
| 704 | DAG.setRoot(ArgValue.getValue(1)); |
| 705 | } |
| 706 | ++NumIntRegs; |
| 707 | break; |
| 708 | } |
| 709 | ObjSize = 4; |
| 710 | break; |
| 711 | case MVT::i64: |
| 712 | if (NumIntRegs == 0) { |
| 713 | if (!I->use_empty()) { |
| 714 | unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); |
| 715 | unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 716 | |
| 717 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 718 | SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); |
| 719 | DAG.setRoot(Hi.getValue(1)); |
| 720 | |
| 721 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 722 | } |
| 723 | NumIntRegs = 2; |
| 724 | break; |
| 725 | } else if (NumIntRegs == 1) { |
| 726 | if (!I->use_empty()) { |
| 727 | unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); |
| 728 | SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); |
| 729 | DAG.setRoot(Low.getValue(1)); |
| 730 | |
| 731 | // Load the high part from memory. |
| 732 | // Create the frame index object for this incoming parameter... |
| 733 | int FI = MFI->CreateFixedObject(4, ArgOffset); |
| 734 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 735 | SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, |
| 736 | DAG.getSrcValue(NULL)); |
| 737 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); |
| 738 | } |
| 739 | ArgOffset += 4; |
| 740 | NumIntRegs = 2; |
| 741 | break; |
| 742 | } |
| 743 | ObjSize = ArgIncrement = 8; |
| 744 | break; |
| 745 | case MVT::f32: ObjSize = 4; break; |
| 746 | case MVT::f64: ObjSize = ArgIncrement = 8; break; |
| 747 | } |
| 748 | |
| 749 | // Don't codegen dead arguments. FIXME: remove this check when we can nuke |
| 750 | // dead loads. |
| 751 | if (ObjSize && !I->use_empty()) { |
| 752 | // Create the frame index object for this incoming parameter... |
| 753 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 754 | |
| 755 | // Create the SelectionDAG nodes corresponding to a load from this |
| 756 | // parameter. |
| 757 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 758 | |
| 759 | ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, |
| 760 | DAG.getSrcValue(NULL)); |
| 761 | } else if (ArgValue.Val == 0) { |
| 762 | if (MVT::isInteger(ObjectVT)) |
| 763 | ArgValue = DAG.getConstant(0, ObjectVT); |
| 764 | else |
| 765 | ArgValue = DAG.getConstantFP(0, ObjectVT); |
| 766 | } |
| 767 | ArgValues.push_back(ArgValue); |
| 768 | |
| 769 | if (ObjSize) |
| 770 | ArgOffset += ArgIncrement; // Move on to the next argument. |
| 771 | } |
| 772 | |
| 773 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 774 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 775 | if ((ArgOffset & 7) == 0) |
| 776 | ArgOffset += 4; |
| 777 | |
| 778 | VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. |
| 779 | ReturnAddrIndex = 0; // No return address slot generated yet. |
| 780 | BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. |
| 781 | BytesCallerReserves = 0; |
| 782 | |
| 783 | // Finally, inform the code generator which regs we return values in. |
| 784 | switch (getValueType(F.getReturnType())) { |
| 785 | default: assert(0 && "Unknown type!"); |
| 786 | case MVT::isVoid: break; |
| 787 | case MVT::i1: |
| 788 | case MVT::i8: |
| 789 | case MVT::i16: |
| 790 | case MVT::i32: |
| 791 | MF.addLiveOut(X86::EAX); |
| 792 | break; |
| 793 | case MVT::i64: |
| 794 | MF.addLiveOut(X86::EAX); |
| 795 | MF.addLiveOut(X86::EDX); |
| 796 | break; |
| 797 | case MVT::f32: |
| 798 | case MVT::f64: |
| 799 | MF.addLiveOut(X86::ST0); |
| 800 | break; |
| 801 | } |
| 802 | return ArgValues; |
| 803 | } |
| 804 | |
| 805 | std::pair<SDOperand, SDOperand> |
| 806 | X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, |
| 807 | bool isTailCall, SDOperand Callee, |
| 808 | ArgListTy &Args, SelectionDAG &DAG) { |
| 809 | // Count how many bytes are to be pushed on the stack. |
| 810 | unsigned NumBytes = 0; |
| 811 | |
| 812 | // Keep track of the number of integer regs passed so far. This can be either |
| 813 | // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both |
| 814 | // used). |
| 815 | unsigned NumIntRegs = 0; |
| 816 | |
| 817 | for (unsigned i = 0, e = Args.size(); i != e; ++i) |
| 818 | switch (getValueType(Args[i].second)) { |
| 819 | default: assert(0 && "Unknown value type!"); |
| 820 | case MVT::i1: |
| 821 | case MVT::i8: |
| 822 | case MVT::i16: |
| 823 | case MVT::i32: |
| 824 | if (NumIntRegs < 2) { |
| 825 | ++NumIntRegs; |
| 826 | break; |
| 827 | } |
| 828 | // fall through |
| 829 | case MVT::f32: |
| 830 | NumBytes += 4; |
| 831 | break; |
| 832 | case MVT::i64: |
| 833 | if (NumIntRegs == 0) { |
| 834 | NumIntRegs = 2; |
| 835 | break; |
| 836 | } else if (NumIntRegs == 1) { |
| 837 | NumIntRegs = 2; |
| 838 | NumBytes += 4; |
| 839 | break; |
| 840 | } |
| 841 | |
| 842 | // fall through |
| 843 | case MVT::f64: |
| 844 | NumBytes += 8; |
| 845 | break; |
| 846 | } |
| 847 | |
| 848 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 849 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 850 | if ((NumBytes & 7) == 0) |
| 851 | NumBytes += 4; |
| 852 | |
Chris Lattner | 94dd292 | 2006-02-13 09:00:43 +0000 | [diff] [blame] | 853 | Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 854 | |
| 855 | // Arguments go on the stack in reverse order, as specified by the ABI. |
| 856 | unsigned ArgOffset = 0; |
Chris Lattner | 91cacc8 | 2006-01-24 06:14:44 +0000 | [diff] [blame] | 857 | SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 858 | NumIntRegs = 0; |
| 859 | std::vector<SDOperand> Stores; |
| 860 | std::vector<SDOperand> RegValuesToPass; |
| 861 | for (unsigned i = 0, e = Args.size(); i != e; ++i) { |
| 862 | switch (getValueType(Args[i].second)) { |
| 863 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 864 | case MVT::i1: |
Chris Lattner | f31d193 | 2005-12-27 03:02:18 +0000 | [diff] [blame] | 865 | Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first); |
| 866 | // Fall through. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 867 | case MVT::i8: |
| 868 | case MVT::i16: |
| 869 | case MVT::i32: |
| 870 | if (NumIntRegs < 2) { |
| 871 | RegValuesToPass.push_back(Args[i].first); |
| 872 | ++NumIntRegs; |
| 873 | break; |
| 874 | } |
| 875 | // Fall through |
| 876 | case MVT::f32: { |
| 877 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 878 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 879 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 880 | Args[i].first, PtrOff, |
| 881 | DAG.getSrcValue(NULL))); |
| 882 | ArgOffset += 4; |
| 883 | break; |
| 884 | } |
| 885 | case MVT::i64: |
| 886 | if (NumIntRegs < 2) { // Can pass part of it in regs? |
| 887 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 888 | Args[i].first, DAG.getConstant(1, MVT::i32)); |
| 889 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |
| 890 | Args[i].first, DAG.getConstant(0, MVT::i32)); |
| 891 | RegValuesToPass.push_back(Lo); |
| 892 | ++NumIntRegs; |
| 893 | if (NumIntRegs < 2) { // Pass both parts in regs? |
| 894 | RegValuesToPass.push_back(Hi); |
| 895 | ++NumIntRegs; |
| 896 | } else { |
| 897 | // Pass the high part in memory. |
| 898 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 899 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 900 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 901 | Hi, PtrOff, DAG.getSrcValue(NULL))); |
| 902 | ArgOffset += 4; |
| 903 | } |
| 904 | break; |
| 905 | } |
| 906 | // Fall through |
| 907 | case MVT::f64: |
| 908 | SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); |
| 909 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 910 | Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, |
| 911 | Args[i].first, PtrOff, |
| 912 | DAG.getSrcValue(NULL))); |
| 913 | ArgOffset += 8; |
| 914 | break; |
| 915 | } |
| 916 | } |
| 917 | if (!Stores.empty()) |
| 918 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); |
| 919 | |
| 920 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 921 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 922 | if ((ArgOffset & 7) == 0) |
| 923 | ArgOffset += 4; |
| 924 | |
| 925 | std::vector<MVT::ValueType> RetVals; |
| 926 | MVT::ValueType RetTyVT = getValueType(RetTy); |
| 927 | |
| 928 | RetVals.push_back(MVT::Other); |
| 929 | |
| 930 | // The result values produced have to be legal. Promote the result. |
| 931 | switch (RetTyVT) { |
| 932 | case MVT::isVoid: break; |
| 933 | default: |
| 934 | RetVals.push_back(RetTyVT); |
| 935 | break; |
| 936 | case MVT::i1: |
| 937 | case MVT::i8: |
| 938 | case MVT::i16: |
| 939 | RetVals.push_back(MVT::i32); |
| 940 | break; |
| 941 | case MVT::f32: |
| 942 | if (X86ScalarSSE) |
| 943 | RetVals.push_back(MVT::f32); |
| 944 | else |
| 945 | RetVals.push_back(MVT::f64); |
| 946 | break; |
| 947 | case MVT::i64: |
| 948 | RetVals.push_back(MVT::i32); |
| 949 | RetVals.push_back(MVT::i32); |
| 950 | break; |
| 951 | } |
| 952 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 953 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 954 | // and flag operands which copy the outgoing args into registers. |
| 955 | SDOperand InFlag; |
| 956 | for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { |
| 957 | unsigned CCReg; |
| 958 | SDOperand RegToPass = RegValuesToPass[i]; |
| 959 | switch (RegToPass.getValueType()) { |
| 960 | default: assert(0 && "Bad thing to pass in regs"); |
| 961 | case MVT::i8: |
| 962 | CCReg = (i == 0) ? X86::AL : X86::DL; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 963 | break; |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 964 | case MVT::i16: |
| 965 | CCReg = (i == 0) ? X86::AX : X86::DX; |
| 966 | break; |
| 967 | case MVT::i32: |
| 968 | CCReg = (i == 0) ? X86::EAX : X86::EDX; |
| 969 | break; |
| 970 | } |
| 971 | |
| 972 | Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag); |
| 973 | InFlag = Chain.getValue(1); |
| 974 | } |
| 975 | |
| 976 | std::vector<MVT::ValueType> NodeTys; |
| 977 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 978 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 979 | std::vector<SDOperand> Ops; |
| 980 | Ops.push_back(Chain); |
| 981 | Ops.push_back(Callee); |
| 982 | if (InFlag.Val) |
| 983 | Ops.push_back(InFlag); |
| 984 | |
| 985 | // FIXME: Do not generate X86ISD::TAILCALL for now. |
| 986 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); |
| 987 | InFlag = Chain.getValue(1); |
| 988 | |
| 989 | NodeTys.clear(); |
| 990 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 991 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 992 | Ops.clear(); |
| 993 | Ops.push_back(Chain); |
| 994 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 995 | Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); |
| 996 | Ops.push_back(InFlag); |
| 997 | Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops); |
| 998 | InFlag = Chain.getValue(1); |
| 999 | |
| 1000 | SDOperand RetVal; |
| 1001 | if (RetTyVT != MVT::isVoid) { |
| 1002 | switch (RetTyVT) { |
| 1003 | default: assert(0 && "Unknown value type to return!"); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1004 | case MVT::i1: |
| 1005 | case MVT::i8: |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1006 | RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); |
| 1007 | Chain = RetVal.getValue(1); |
| 1008 | if (RetTyVT == MVT::i1) |
| 1009 | RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal); |
| 1010 | break; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1011 | case MVT::i16: |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1012 | RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); |
| 1013 | Chain = RetVal.getValue(1); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1014 | break; |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1015 | case MVT::i32: |
| 1016 | RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 1017 | Chain = RetVal.getValue(1); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1018 | break; |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1019 | case MVT::i64: { |
| 1020 | SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); |
| 1021 | SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, |
| 1022 | Lo.getValue(2)); |
| 1023 | RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 1024 | Chain = Hi.getValue(1); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1025 | break; |
| 1026 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1027 | case MVT::f32: |
| 1028 | case MVT::f64: { |
| 1029 | std::vector<MVT::ValueType> Tys; |
| 1030 | Tys.push_back(MVT::f64); |
| 1031 | Tys.push_back(MVT::Other); |
| 1032 | Tys.push_back(MVT::Flag); |
| 1033 | std::vector<SDOperand> Ops; |
| 1034 | Ops.push_back(Chain); |
| 1035 | Ops.push_back(InFlag); |
| 1036 | RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); |
| 1037 | Chain = RetVal.getValue(1); |
| 1038 | InFlag = RetVal.getValue(2); |
| 1039 | if (X86ScalarSSE) { |
| 1040 | // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This |
| 1041 | // shouldn't be necessary except that RFP cannot be live across |
| 1042 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
| 1043 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1044 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
| 1045 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1046 | Tys.clear(); |
| 1047 | Tys.push_back(MVT::Other); |
| 1048 | Ops.clear(); |
| 1049 | Ops.push_back(Chain); |
| 1050 | Ops.push_back(RetVal); |
| 1051 | Ops.push_back(StackSlot); |
| 1052 | Ops.push_back(DAG.getValueType(RetTyVT)); |
| 1053 | Ops.push_back(InFlag); |
| 1054 | Chain = DAG.getNode(X86ISD::FST, Tys, Ops); |
| 1055 | RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, |
| 1056 | DAG.getSrcValue(NULL)); |
| 1057 | Chain = RetVal.getValue(1); |
| 1058 | } |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1059 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1060 | if (RetTyVT == MVT::f32 && !X86ScalarSSE) |
| 1061 | // FIXME: we would really like to remember that this FP_ROUND |
| 1062 | // operation is okay to eliminate if we allow excess FP precision. |
| 1063 | RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); |
| 1064 | break; |
| 1065 | } |
| 1066 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1067 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1068 | |
| 1069 | return std::make_pair(RetVal, Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1070 | } |
| 1071 | |
| 1072 | SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { |
| 1073 | if (ReturnAddrIndex == 0) { |
| 1074 | // Set up a frame object for the return address. |
| 1075 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1076 | ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); |
| 1077 | } |
| 1078 | |
| 1079 | return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); |
| 1080 | } |
| 1081 | |
| 1082 | |
| 1083 | |
| 1084 | std::pair<SDOperand, SDOperand> X86TargetLowering:: |
| 1085 | LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, |
| 1086 | SelectionDAG &DAG) { |
| 1087 | SDOperand Result; |
| 1088 | if (Depth) // Depths > 0 not supported yet! |
| 1089 | Result = DAG.getConstant(0, getPointerTy()); |
| 1090 | else { |
| 1091 | SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); |
| 1092 | if (!isFrameAddress) |
| 1093 | // Just load the return address |
| 1094 | Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, |
| 1095 | DAG.getSrcValue(NULL)); |
| 1096 | else |
| 1097 | Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, |
| 1098 | DAG.getConstant(4, MVT::i32)); |
| 1099 | } |
| 1100 | return std::make_pair(Result, Chain); |
| 1101 | } |
| 1102 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1103 | /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode |
| 1104 | /// which corresponds to the condition code. |
| 1105 | static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) { |
| 1106 | switch (X86CC) { |
| 1107 | default: assert(0 && "Unknown X86 conditional code!"); |
| 1108 | case X86ISD::COND_A: return X86::JA; |
| 1109 | case X86ISD::COND_AE: return X86::JAE; |
| 1110 | case X86ISD::COND_B: return X86::JB; |
| 1111 | case X86ISD::COND_BE: return X86::JBE; |
| 1112 | case X86ISD::COND_E: return X86::JE; |
| 1113 | case X86ISD::COND_G: return X86::JG; |
| 1114 | case X86ISD::COND_GE: return X86::JGE; |
| 1115 | case X86ISD::COND_L: return X86::JL; |
| 1116 | case X86ISD::COND_LE: return X86::JLE; |
| 1117 | case X86ISD::COND_NE: return X86::JNE; |
| 1118 | case X86ISD::COND_NO: return X86::JNO; |
| 1119 | case X86ISD::COND_NP: return X86::JNP; |
| 1120 | case X86ISD::COND_NS: return X86::JNS; |
| 1121 | case X86ISD::COND_O: return X86::JO; |
| 1122 | case X86ISD::COND_P: return X86::JP; |
| 1123 | case X86ISD::COND_S: return X86::JS; |
| 1124 | } |
| 1125 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1126 | |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1127 | /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 |
| 1128 | /// specific condition code. It returns a false if it cannot do a direct |
| 1129 | /// translation. X86CC is the translated CondCode. Flip is set to true if the |
| 1130 | /// the order of comparison operands should be flipped. |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 1131 | static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC, |
| 1132 | bool &Flip) { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1133 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1134 | Flip = false; |
| 1135 | X86CC = X86ISD::COND_INVALID; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1136 | if (!isFP) { |
| 1137 | switch (SetCCOpcode) { |
| 1138 | default: break; |
| 1139 | case ISD::SETEQ: X86CC = X86ISD::COND_E; break; |
| 1140 | case ISD::SETGT: X86CC = X86ISD::COND_G; break; |
| 1141 | case ISD::SETGE: X86CC = X86ISD::COND_GE; break; |
| 1142 | case ISD::SETLT: X86CC = X86ISD::COND_L; break; |
| 1143 | case ISD::SETLE: X86CC = X86ISD::COND_LE; break; |
| 1144 | case ISD::SETNE: X86CC = X86ISD::COND_NE; break; |
| 1145 | case ISD::SETULT: X86CC = X86ISD::COND_B; break; |
| 1146 | case ISD::SETUGT: X86CC = X86ISD::COND_A; break; |
| 1147 | case ISD::SETULE: X86CC = X86ISD::COND_BE; break; |
| 1148 | case ISD::SETUGE: X86CC = X86ISD::COND_AE; break; |
| 1149 | } |
| 1150 | } else { |
| 1151 | // On a floating point condition, the flags are set as follows: |
| 1152 | // ZF PF CF op |
| 1153 | // 0 | 0 | 0 | X > Y |
| 1154 | // 0 | 0 | 1 | X < Y |
| 1155 | // 1 | 0 | 0 | X == Y |
| 1156 | // 1 | 1 | 1 | unordered |
| 1157 | switch (SetCCOpcode) { |
| 1158 | default: break; |
| 1159 | case ISD::SETUEQ: |
| 1160 | case ISD::SETEQ: X86CC = X86ISD::COND_E; break; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1161 | case ISD::SETOLE: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1162 | case ISD::SETOGT: |
| 1163 | case ISD::SETGT: X86CC = X86ISD::COND_A; break; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1164 | case ISD::SETOLT: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1165 | case ISD::SETOGE: |
| 1166 | case ISD::SETGE: X86CC = X86ISD::COND_AE; break; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1167 | case ISD::SETUGE: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1168 | case ISD::SETULT: |
| 1169 | case ISD::SETLT: X86CC = X86ISD::COND_B; break; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1170 | case ISD::SETUGT: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1171 | case ISD::SETULE: |
| 1172 | case ISD::SETLE: X86CC = X86ISD::COND_BE; break; |
| 1173 | case ISD::SETONE: |
| 1174 | case ISD::SETNE: X86CC = X86ISD::COND_NE; break; |
| 1175 | case ISD::SETUO: X86CC = X86ISD::COND_P; break; |
| 1176 | case ISD::SETO: X86CC = X86ISD::COND_NP; break; |
| 1177 | } |
| 1178 | } |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1179 | |
| 1180 | return X86CC != X86ISD::COND_INVALID; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1183 | /// hasFPCMov - is there a floating point cmov for the specific X86 condition |
| 1184 | /// code. Current x86 isa includes the following FP cmov instructions: |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1185 | /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1186 | static bool hasFPCMov(unsigned X86CC) { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1187 | switch (X86CC) { |
| 1188 | default: |
| 1189 | return false; |
| 1190 | case X86ISD::COND_B: |
| 1191 | case X86ISD::COND_BE: |
| 1192 | case X86ISD::COND_E: |
| 1193 | case X86ISD::COND_P: |
| 1194 | case X86ISD::COND_A: |
| 1195 | case X86ISD::COND_AE: |
| 1196 | case X86ISD::COND_NE: |
| 1197 | case X86ISD::COND_NP: |
| 1198 | return true; |
| 1199 | } |
| 1200 | } |
| 1201 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1202 | MachineBasicBlock * |
| 1203 | X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, |
| 1204 | MachineBasicBlock *BB) { |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1205 | switch (MI->getOpcode()) { |
| 1206 | default: assert(false && "Unexpected instr type to insert"); |
| 1207 | case X86::CMOV_FR32: |
| 1208 | case X86::CMOV_FR64: { |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 1209 | // To "insert" a SELECT_CC instruction, we actually have to insert the |
| 1210 | // diamond control-flow pattern. The incoming instruction knows the |
| 1211 | // destination vreg to set, the condition code register to branch on, the |
| 1212 | // true/false values to select between, and a branch opcode to use. |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1213 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 1214 | ilist<MachineBasicBlock>::iterator It = BB; |
| 1215 | ++It; |
| 1216 | |
| 1217 | // thisMBB: |
| 1218 | // ... |
| 1219 | // TrueVal = ... |
| 1220 | // cmpTY ccX, r1, r2 |
| 1221 | // bCC copy1MBB |
| 1222 | // fallthrough --> copy0MBB |
| 1223 | MachineBasicBlock *thisMBB = BB; |
| 1224 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 1225 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
| 1226 | unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue()); |
| 1227 | BuildMI(BB, Opc, 1).addMBB(sinkMBB); |
| 1228 | MachineFunction *F = BB->getParent(); |
| 1229 | F->getBasicBlockList().insert(It, copy0MBB); |
| 1230 | F->getBasicBlockList().insert(It, sinkMBB); |
| 1231 | // Update machine-CFG edges |
| 1232 | BB->addSuccessor(copy0MBB); |
| 1233 | BB->addSuccessor(sinkMBB); |
| 1234 | |
| 1235 | // copy0MBB: |
| 1236 | // %FalseValue = ... |
| 1237 | // # fallthrough to sinkMBB |
| 1238 | BB = copy0MBB; |
| 1239 | |
| 1240 | // Update machine-CFG edges |
| 1241 | BB->addSuccessor(sinkMBB); |
| 1242 | |
| 1243 | // sinkMBB: |
| 1244 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 1245 | // ... |
| 1246 | BB = sinkMBB; |
| 1247 | BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg()) |
| 1248 | .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) |
| 1249 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1250 | |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1251 | delete MI; // The pseudo instruction is gone now. |
| 1252 | return BB; |
| 1253 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1254 | |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1255 | case X86::FP_TO_INT16_IN_MEM: |
| 1256 | case X86::FP_TO_INT32_IN_MEM: |
| 1257 | case X86::FP_TO_INT64_IN_MEM: { |
| 1258 | // Change the floating point control register to use "round towards zero" |
| 1259 | // mode when truncating to an integer value. |
| 1260 | MachineFunction *F = BB->getParent(); |
| 1261 | int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); |
| 1262 | addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); |
| 1263 | |
| 1264 | // Load the old value of the high byte of the control word... |
| 1265 | unsigned OldCW = |
| 1266 | F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass); |
| 1267 | addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); |
| 1268 | |
| 1269 | // Set the high part to be round to zero... |
| 1270 | addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); |
| 1271 | |
| 1272 | // Reload the modified control word now... |
| 1273 | addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); |
| 1274 | |
| 1275 | // Restore the memory image of control word to original value |
| 1276 | addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); |
| 1277 | |
| 1278 | // Get the X86 opcode to use. |
| 1279 | unsigned Opc; |
| 1280 | switch (MI->getOpcode()) { |
Chris Lattner | 6b2469c | 2006-01-28 10:34:47 +0000 | [diff] [blame] | 1281 | default: assert(0 && "illegal opcode!"); |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 1282 | case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; |
| 1283 | case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; |
| 1284 | case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; |
| 1285 | } |
| 1286 | |
| 1287 | X86AddressMode AM; |
| 1288 | MachineOperand &Op = MI->getOperand(0); |
| 1289 | if (Op.isRegister()) { |
| 1290 | AM.BaseType = X86AddressMode::RegBase; |
| 1291 | AM.Base.Reg = Op.getReg(); |
| 1292 | } else { |
| 1293 | AM.BaseType = X86AddressMode::FrameIndexBase; |
| 1294 | AM.Base.FrameIndex = Op.getFrameIndex(); |
| 1295 | } |
| 1296 | Op = MI->getOperand(1); |
| 1297 | if (Op.isImmediate()) |
| 1298 | AM.Scale = Op.getImmedValue(); |
| 1299 | Op = MI->getOperand(2); |
| 1300 | if (Op.isImmediate()) |
| 1301 | AM.IndexReg = Op.getImmedValue(); |
| 1302 | Op = MI->getOperand(3); |
| 1303 | if (Op.isGlobalAddress()) { |
| 1304 | AM.GV = Op.getGlobal(); |
| 1305 | } else { |
| 1306 | AM.Disp = Op.getImmedValue(); |
| 1307 | } |
| 1308 | addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg()); |
| 1309 | |
| 1310 | // Reload the original control word now. |
| 1311 | addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); |
| 1312 | |
| 1313 | delete MI; // The pseudo instruction is gone now. |
| 1314 | return BB; |
| 1315 | } |
| 1316 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1317 | } |
| 1318 | |
| 1319 | |
| 1320 | //===----------------------------------------------------------------------===// |
| 1321 | // X86 Custom Lowering Hooks |
| 1322 | //===----------------------------------------------------------------------===// |
| 1323 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1324 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 1325 | /// |
| 1326 | SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
| 1327 | switch (Op.getOpcode()) { |
| 1328 | default: assert(0 && "Should not custom lower this!"); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1329 | case ISD::SHL_PARTS: |
| 1330 | case ISD::SRA_PARTS: |
| 1331 | case ISD::SRL_PARTS: { |
| 1332 | assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && |
| 1333 | "Not an i64 shift!"); |
| 1334 | bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; |
| 1335 | SDOperand ShOpLo = Op.getOperand(0); |
| 1336 | SDOperand ShOpHi = Op.getOperand(1); |
| 1337 | SDOperand ShAmt = Op.getOperand(2); |
| 1338 | SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, |
Evan Cheng | 99fa0a1 | 2006-01-18 09:26:46 +0000 | [diff] [blame] | 1339 | DAG.getConstant(31, MVT::i8)) |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1340 | : DAG.getConstant(0, MVT::i32); |
| 1341 | |
| 1342 | SDOperand Tmp2, Tmp3; |
| 1343 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
| 1344 | Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); |
| 1345 | Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); |
| 1346 | } else { |
| 1347 | Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); |
Evan Cheng | b7b5706 | 2006-01-19 01:46:14 +0000 | [diff] [blame] | 1348 | Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag, |
| 1352 | ShAmt, DAG.getConstant(32, MVT::i8)); |
| 1353 | |
| 1354 | SDOperand Hi, Lo; |
Evan Cheng | 82a24b9 | 2006-01-09 20:49:21 +0000 | [diff] [blame] | 1355 | SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1356 | |
| 1357 | std::vector<MVT::ValueType> Tys; |
| 1358 | Tys.push_back(MVT::i32); |
| 1359 | Tys.push_back(MVT::Flag); |
| 1360 | std::vector<SDOperand> Ops; |
| 1361 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
| 1362 | Ops.push_back(Tmp2); |
| 1363 | Ops.push_back(Tmp3); |
| 1364 | Ops.push_back(CC); |
| 1365 | Ops.push_back(InFlag); |
| 1366 | Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1367 | InFlag = Hi.getValue(1); |
| 1368 | |
| 1369 | Ops.clear(); |
| 1370 | Ops.push_back(Tmp3); |
| 1371 | Ops.push_back(Tmp1); |
| 1372 | Ops.push_back(CC); |
| 1373 | Ops.push_back(InFlag); |
| 1374 | Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1375 | } else { |
| 1376 | Ops.push_back(Tmp2); |
| 1377 | Ops.push_back(Tmp3); |
| 1378 | Ops.push_back(CC); |
Evan Cheng | 910cd3c | 2006-01-09 22:29:54 +0000 | [diff] [blame] | 1379 | Ops.push_back(InFlag); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1380 | Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1381 | InFlag = Lo.getValue(1); |
| 1382 | |
| 1383 | Ops.clear(); |
| 1384 | Ops.push_back(Tmp3); |
| 1385 | Ops.push_back(Tmp1); |
| 1386 | Ops.push_back(CC); |
| 1387 | Ops.push_back(InFlag); |
| 1388 | Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); |
| 1389 | } |
| 1390 | |
| 1391 | Tys.clear(); |
| 1392 | Tys.push_back(MVT::i32); |
| 1393 | Tys.push_back(MVT::i32); |
| 1394 | Ops.clear(); |
| 1395 | Ops.push_back(Lo); |
| 1396 | Ops.push_back(Hi); |
| 1397 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
| 1398 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1399 | case ISD::SINT_TO_FP: { |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 1400 | assert(Op.getOperand(0).getValueType() <= MVT::i64 && |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1401 | Op.getOperand(0).getValueType() >= MVT::i16 && |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1402 | "Unknown SINT_TO_FP to lower!"); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1403 | |
| 1404 | SDOperand Result; |
| 1405 | MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); |
| 1406 | unsigned Size = MVT::getSizeInBits(SrcVT)/8; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1407 | MachineFunction &MF = DAG.getMachineFunction(); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1408 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1409 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1410 | SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, |
| 1411 | DAG.getEntryNode(), Op.getOperand(0), |
| 1412 | StackSlot, DAG.getSrcValue(NULL)); |
| 1413 | |
| 1414 | // Build the FILD |
| 1415 | std::vector<MVT::ValueType> Tys; |
| 1416 | Tys.push_back(MVT::f64); |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1417 | Tys.push_back(MVT::Other); |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 1418 | if (X86ScalarSSE) Tys.push_back(MVT::Flag); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1419 | std::vector<SDOperand> Ops; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1420 | Ops.push_back(Chain); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1421 | Ops.push_back(StackSlot); |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1422 | Ops.push_back(DAG.getValueType(SrcVT)); |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 1423 | Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD, |
| 1424 | Tys, Ops); |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1425 | |
| 1426 | if (X86ScalarSSE) { |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1427 | Chain = Result.getValue(1); |
| 1428 | SDOperand InFlag = Result.getValue(2); |
| 1429 | |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 1430 | // FIXME: Currently the FST is flagged to the FILD_FLAG. This |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1431 | // shouldn't be necessary except that RFP cannot be live across |
| 1432 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
| 1433 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1434 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
| 1435 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1436 | std::vector<MVT::ValueType> Tys; |
| 1437 | Tys.push_back(MVT::Other); |
| 1438 | std::vector<SDOperand> Ops; |
| 1439 | Ops.push_back(Chain); |
| 1440 | Ops.push_back(Result); |
| 1441 | Ops.push_back(StackSlot); |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 1442 | Ops.push_back(DAG.getValueType(Op.getValueType())); |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1443 | Ops.push_back(InFlag); |
| 1444 | Chain = DAG.getNode(X86ISD::FST, Tys, Ops); |
| 1445 | Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, |
| 1446 | DAG.getSrcValue(NULL)); |
| 1447 | } |
| 1448 | |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1449 | return Result; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1450 | } |
| 1451 | case ISD::FP_TO_SINT: { |
| 1452 | assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1453 | "Unknown FP_TO_SINT to lower!"); |
| 1454 | // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary |
| 1455 | // stack slot. |
| 1456 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1457 | unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; |
| 1458 | int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 1459 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1460 | |
| 1461 | unsigned Opc; |
| 1462 | switch (Op.getValueType()) { |
| 1463 | default: assert(0 && "Invalid FP_TO_SINT to lower!"); |
| 1464 | case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; |
| 1465 | case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; |
| 1466 | case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; |
| 1467 | } |
| 1468 | |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1469 | SDOperand Chain = DAG.getEntryNode(); |
| 1470 | SDOperand Value = Op.getOperand(0); |
| 1471 | if (X86ScalarSSE) { |
| 1472 | assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); |
| 1473 | Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot, |
| 1474 | DAG.getSrcValue(0)); |
| 1475 | std::vector<MVT::ValueType> Tys; |
| 1476 | Tys.push_back(MVT::f64); |
| 1477 | Tys.push_back(MVT::Other); |
| 1478 | std::vector<SDOperand> Ops; |
| 1479 | Ops.push_back(Chain); |
| 1480 | Ops.push_back(StackSlot); |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 1481 | Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType())); |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1482 | Value = DAG.getNode(X86ISD::FLD, Tys, Ops); |
| 1483 | Chain = Value.getValue(1); |
| 1484 | SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 1485 | StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1486 | } |
| 1487 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1488 | // Build the FP_TO_INT*_IN_MEM |
| 1489 | std::vector<SDOperand> Ops; |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 1490 | Ops.push_back(Chain); |
| 1491 | Ops.push_back(Value); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1492 | Ops.push_back(StackSlot); |
| 1493 | SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); |
| 1494 | |
| 1495 | // Load the result. |
| 1496 | return DAG.getLoad(Op.getValueType(), FIST, StackSlot, |
| 1497 | DAG.getSrcValue(NULL)); |
| 1498 | } |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 1499 | case ISD::READCYCLECOUNTER: { |
Chris Lattner | 81363c3 | 2005-11-20 22:01:40 +0000 | [diff] [blame] | 1500 | std::vector<MVT::ValueType> Tys; |
| 1501 | Tys.push_back(MVT::Other); |
| 1502 | Tys.push_back(MVT::Flag); |
| 1503 | std::vector<SDOperand> Ops; |
| 1504 | Ops.push_back(Op.getOperand(0)); |
| 1505 | SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); |
Chris Lattner | 81f803d | 2005-11-20 22:57:19 +0000 | [diff] [blame] | 1506 | Ops.clear(); |
| 1507 | Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); |
| 1508 | Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, |
| 1509 | MVT::i32, Ops[0].getValue(2))); |
| 1510 | Ops.push_back(Ops[1].getValue(1)); |
| 1511 | Tys[0] = Tys[1] = MVT::i32; |
| 1512 | Tys.push_back(MVT::Other); |
| 1513 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 1514 | } |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 1515 | case ISD::FABS: { |
| 1516 | MVT::ValueType VT = Op.getValueType(); |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 1517 | const Type *OpNTy = MVT::getTypeForValueType(VT); |
| 1518 | std::vector<Constant*> CV; |
| 1519 | if (VT == MVT::f64) { |
| 1520 | CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63)))); |
| 1521 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1522 | } else { |
| 1523 | CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31)))); |
| 1524 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1525 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1526 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1527 | } |
| 1528 | Constant *CS = ConstantStruct::get(CV); |
| 1529 | SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); |
| 1530 | SDOperand Mask |
| 1531 | = DAG.getNode(X86ISD::LOAD_PACK, |
| 1532 | VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 1533 | return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); |
| 1534 | } |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 1535 | case ISD::FNEG: { |
| 1536 | MVT::ValueType VT = Op.getValueType(); |
| 1537 | const Type *OpNTy = MVT::getTypeForValueType(VT); |
| 1538 | std::vector<Constant*> CV; |
| 1539 | if (VT == MVT::f64) { |
| 1540 | CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63))); |
| 1541 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1542 | } else { |
| 1543 | CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31))); |
| 1544 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1545 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1546 | CV.push_back(ConstantFP::get(OpNTy, 0.0)); |
| 1547 | } |
| 1548 | Constant *CS = ConstantStruct::get(CV); |
| 1549 | SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); |
| 1550 | SDOperand Mask |
| 1551 | = DAG.getNode(X86ISD::LOAD_PACK, |
| 1552 | VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); |
| 1553 | return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); |
| 1554 | } |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1555 | case ISD::SETCC: { |
| 1556 | assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1557 | SDOperand Cond; |
| 1558 | SDOperand CC = Op.getOperand(2); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1559 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); |
| 1560 | bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1561 | bool Flip; |
| 1562 | unsigned X86CC; |
| 1563 | if (translateX86CC(CC, isFP, X86CC, Flip)) { |
| 1564 | if (Flip) |
| 1565 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1566 | Op.getOperand(1), Op.getOperand(0)); |
| 1567 | else |
| 1568 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1569 | Op.getOperand(0), Op.getOperand(1)); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1570 | return DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1571 | DAG.getConstant(X86CC, MVT::i8), Cond); |
| 1572 | } else { |
| 1573 | assert(isFP && "Illegal integer SetCC!"); |
| 1574 | |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1575 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1576 | Op.getOperand(0), Op.getOperand(1)); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1577 | std::vector<MVT::ValueType> Tys; |
| 1578 | std::vector<SDOperand> Ops; |
| 1579 | switch (SetCCOpcode) { |
| 1580 | default: assert(false && "Illegal floating point SetCC!"); |
| 1581 | case ISD::SETOEQ: { // !PF & ZF |
| 1582 | Tys.push_back(MVT::i8); |
| 1583 | Tys.push_back(MVT::Flag); |
| 1584 | Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); |
| 1585 | Ops.push_back(Cond); |
| 1586 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1587 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1588 | DAG.getConstant(X86ISD::COND_E, MVT::i8), |
| 1589 | Tmp1.getValue(1)); |
| 1590 | return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); |
| 1591 | } |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1592 | case ISD::SETUNE: { // PF | !ZF |
| 1593 | Tys.push_back(MVT::i8); |
| 1594 | Tys.push_back(MVT::Flag); |
| 1595 | Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); |
| 1596 | Ops.push_back(Cond); |
| 1597 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1598 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 1599 | DAG.getConstant(X86ISD::COND_NE, MVT::i8), |
| 1600 | Tmp1.getValue(1)); |
| 1601 | return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); |
| 1602 | } |
| 1603 | } |
| 1604 | } |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1605 | } |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1606 | case ISD::SELECT: { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1607 | MVT::ValueType VT = Op.getValueType(); |
| 1608 | bool isFP = MVT::isFloatingPoint(VT); |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 1609 | bool isFPStack = isFP && !X86ScalarSSE; |
| 1610 | bool isFPSSE = isFP && X86ScalarSSE; |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1611 | bool addTest = false; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1612 | SDOperand Op0 = Op.getOperand(0); |
| 1613 | SDOperand Cond, CC; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1614 | if (Op0.getOpcode() == ISD::SETCC) |
| 1615 | Op0 = LowerOperation(Op0, DAG); |
| 1616 | |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1617 | if (Op0.getOpcode() == X86ISD::SETCC) { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1618 | // If condition flag is set by a X86ISD::CMP, then make a copy of it |
| 1619 | // (since flag operand cannot be shared). If the X86ISD::SETCC does not |
| 1620 | // have another use it will be eliminated. |
| 1621 | // If the X86ISD::SETCC has more than one use, then it's probably better |
| 1622 | // to use a test instead of duplicating the X86ISD::CMP (for register |
| 1623 | // pressure reason). |
Evan Cheng | 9bba894 | 2006-01-26 02:13:10 +0000 | [diff] [blame] | 1624 | if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) { |
| 1625 | if (!Op0.hasOneUse()) { |
| 1626 | std::vector<MVT::ValueType> Tys; |
| 1627 | for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i) |
| 1628 | Tys.push_back(Op0.Val->getValueType(i)); |
| 1629 | std::vector<SDOperand> Ops; |
| 1630 | for (unsigned i = 0; i < Op0.getNumOperands(); ++i) |
| 1631 | Ops.push_back(Op0.getOperand(i)); |
| 1632 | Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1633 | } |
| 1634 | |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1635 | CC = Op0.getOperand(0); |
| 1636 | Cond = Op0.getOperand(1); |
Evan Cheng | 0d718e9 | 2006-01-25 09:05:09 +0000 | [diff] [blame] | 1637 | // Make a copy as flag result cannot be used by more than one. |
| 1638 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
| 1639 | Cond.getOperand(0), Cond.getOperand(1)); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1640 | addTest = |
Evan Cheng | 80ebe38 | 2006-01-13 01:17:24 +0000 | [diff] [blame] | 1641 | isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1642 | } else |
| 1643 | addTest = true; |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1644 | } else |
| 1645 | addTest = true; |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1646 | |
Evan Cheng | 189d01e | 2006-01-13 01:06:49 +0000 | [diff] [blame] | 1647 | if (addTest) { |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1648 | CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1649 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1650 | } |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1651 | |
| 1652 | std::vector<MVT::ValueType> Tys; |
| 1653 | Tys.push_back(Op.getValueType()); |
| 1654 | Tys.push_back(MVT::Flag); |
| 1655 | std::vector<SDOperand> Ops; |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1656 | // X86ISD::CMOV means set the result (which is operand 1) to the RHS if |
| 1657 | // condition is true. |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1658 | Ops.push_back(Op.getOperand(2)); |
Evan Cheng | e90da97 | 2006-01-13 19:51:46 +0000 | [diff] [blame] | 1659 | Ops.push_back(Op.getOperand(1)); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1660 | Ops.push_back(CC); |
| 1661 | Ops.push_back(Cond); |
| 1662 | return DAG.getNode(X86ISD::CMOV, Tys, Ops); |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 1663 | } |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1664 | case ISD::BRCOND: { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1665 | bool addTest = false; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1666 | SDOperand Cond = Op.getOperand(1); |
| 1667 | SDOperand Dest = Op.getOperand(2); |
| 1668 | SDOperand CC; |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1669 | if (Cond.getOpcode() == ISD::SETCC) |
| 1670 | Cond = LowerOperation(Cond, DAG); |
| 1671 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 1672 | if (Cond.getOpcode() == X86ISD::SETCC) { |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1673 | // If condition flag is set by a X86ISD::CMP, then make a copy of it |
| 1674 | // (since flag operand cannot be shared). If the X86ISD::SETCC does not |
| 1675 | // have another use it will be eliminated. |
| 1676 | // If the X86ISD::SETCC has more than one use, then it's probably better |
| 1677 | // to use a test instead of duplicating the X86ISD::CMP (for register |
| 1678 | // pressure reason). |
Evan Cheng | 9bba894 | 2006-01-26 02:13:10 +0000 | [diff] [blame] | 1679 | if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) { |
| 1680 | if (!Cond.hasOneUse()) { |
| 1681 | std::vector<MVT::ValueType> Tys; |
| 1682 | for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i) |
| 1683 | Tys.push_back(Cond.Val->getValueType(i)); |
| 1684 | std::vector<SDOperand> Ops; |
| 1685 | for (unsigned i = 0; i < Cond.getNumOperands(); ++i) |
| 1686 | Ops.push_back(Cond.getOperand(i)); |
| 1687 | Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops); |
| 1688 | } |
| 1689 | |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1690 | CC = Cond.getOperand(0); |
Evan Cheng | 0d718e9 | 2006-01-25 09:05:09 +0000 | [diff] [blame] | 1691 | Cond = Cond.getOperand(1); |
| 1692 | // Make a copy as flag result cannot be used by more than one. |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1693 | Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, |
Evan Cheng | 0d718e9 | 2006-01-25 09:05:09 +0000 | [diff] [blame] | 1694 | Cond.getOperand(0), Cond.getOperand(1)); |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1695 | } else |
| 1696 | addTest = true; |
Evan Cheng | 1bcee36 | 2006-01-13 01:03:02 +0000 | [diff] [blame] | 1697 | } else |
| 1698 | addTest = true; |
| 1699 | |
| 1700 | if (addTest) { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1701 | CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 1702 | Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); |
| 1703 | } |
| 1704 | return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), |
| 1705 | Op.getOperand(0), Op.getOperand(2), CC, Cond); |
| 1706 | } |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1707 | case ISD::MEMSET: { |
| 1708 | SDOperand InFlag; |
| 1709 | SDOperand Chain = Op.getOperand(0); |
| 1710 | unsigned Align = |
| 1711 | (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); |
| 1712 | if (Align == 0) Align = 1; |
| 1713 | |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1714 | ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); |
| 1715 | // If not DWORD aligned, call memset if size is less than the threshold. |
| 1716 | // It knows how to align to the right boundary first. |
| 1717 | if ((Align & 3) != 0 && |
| 1718 | !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) { |
| 1719 | MVT::ValueType IntPtr = getPointerTy(); |
| 1720 | const Type *IntPtrTy = getTargetData().getIntPtrType(); |
| 1721 | std::vector<std::pair<SDOperand, const Type*> > Args; |
| 1722 | Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); |
| 1723 | // Extend the ubyte argument to be an int value for the call. |
| 1724 | SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); |
| 1725 | Args.push_back(std::make_pair(Val, IntPtrTy)); |
| 1726 | Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy)); |
| 1727 | std::pair<SDOperand,SDOperand> CallResult = |
| 1728 | LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false, |
| 1729 | DAG.getExternalSymbol("memset", IntPtr), Args, DAG); |
| 1730 | return CallResult.second; |
| 1731 | } |
| 1732 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1733 | MVT::ValueType AVT; |
| 1734 | SDOperand Count; |
| 1735 | if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) { |
| 1736 | unsigned ValReg; |
| 1737 | unsigned Val = ValC->getValue() & 255; |
| 1738 | |
| 1739 | // If the value is a constant, then we can potentially use larger sets. |
| 1740 | switch (Align & 3) { |
| 1741 | case 2: // WORD aligned |
| 1742 | AVT = MVT::i16; |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1743 | if (I) |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1744 | Count = DAG.getConstant(I->getValue() / 2, MVT::i32); |
| 1745 | else |
| 1746 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1747 | DAG.getConstant(1, MVT::i8)); |
| 1748 | Val = (Val << 8) | Val; |
| 1749 | ValReg = X86::AX; |
| 1750 | break; |
| 1751 | case 0: // DWORD aligned |
| 1752 | AVT = MVT::i32; |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1753 | if (I) |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1754 | Count = DAG.getConstant(I->getValue() / 4, MVT::i32); |
| 1755 | else |
| 1756 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1757 | DAG.getConstant(2, MVT::i8)); |
| 1758 | Val = (Val << 8) | Val; |
| 1759 | Val = (Val << 16) | Val; |
| 1760 | ValReg = X86::EAX; |
| 1761 | break; |
| 1762 | default: // Byte aligned |
| 1763 | AVT = MVT::i8; |
| 1764 | Count = Op.getOperand(3); |
| 1765 | ValReg = X86::AL; |
| 1766 | break; |
| 1767 | } |
| 1768 | |
| 1769 | Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), |
| 1770 | InFlag); |
| 1771 | InFlag = Chain.getValue(1); |
| 1772 | } else { |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1773 | AVT = MVT::i8; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1774 | Count = Op.getOperand(3); |
| 1775 | Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); |
| 1776 | InFlag = Chain.getValue(1); |
| 1777 | } |
| 1778 | |
| 1779 | Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); |
| 1780 | InFlag = Chain.getValue(1); |
| 1781 | Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); |
| 1782 | InFlag = Chain.getValue(1); |
| 1783 | |
| 1784 | return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain, |
| 1785 | DAG.getValueType(AVT), InFlag); |
| 1786 | } |
| 1787 | case ISD::MEMCPY: { |
| 1788 | SDOperand Chain = Op.getOperand(0); |
| 1789 | unsigned Align = |
| 1790 | (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); |
| 1791 | if (Align == 0) Align = 1; |
| 1792 | |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1793 | ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); |
| 1794 | // If not DWORD aligned, call memcpy if size is less than the threshold. |
| 1795 | // It knows how to align to the right boundary first. |
| 1796 | if ((Align & 3) != 0 && |
| 1797 | !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) { |
| 1798 | MVT::ValueType IntPtr = getPointerTy(); |
| 1799 | const Type *IntPtrTy = getTargetData().getIntPtrType(); |
| 1800 | std::vector<std::pair<SDOperand, const Type*> > Args; |
| 1801 | Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); |
| 1802 | Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy)); |
| 1803 | Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy)); |
| 1804 | std::pair<SDOperand,SDOperand> CallResult = |
| 1805 | LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false, |
| 1806 | DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); |
| 1807 | return CallResult.second; |
| 1808 | } |
| 1809 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1810 | MVT::ValueType AVT; |
| 1811 | SDOperand Count; |
| 1812 | switch (Align & 3) { |
| 1813 | case 2: // WORD aligned |
| 1814 | AVT = MVT::i16; |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1815 | if (I) |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1816 | Count = DAG.getConstant(I->getValue() / 2, MVT::i32); |
| 1817 | else |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1818 | Count = DAG.getConstant(I->getValue() / 2, MVT::i32); |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1819 | break; |
| 1820 | case 0: // DWORD aligned |
| 1821 | AVT = MVT::i32; |
Evan Cheng | 18a8452 | 2006-02-16 00:21:07 +0000 | [diff] [blame] | 1822 | if (I) |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 1823 | Count = DAG.getConstant(I->getValue() / 4, MVT::i32); |
| 1824 | else |
| 1825 | Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), |
| 1826 | DAG.getConstant(2, MVT::i8)); |
| 1827 | break; |
| 1828 | default: // Byte aligned |
| 1829 | AVT = MVT::i8; |
| 1830 | Count = Op.getOperand(3); |
| 1831 | break; |
| 1832 | } |
| 1833 | |
| 1834 | SDOperand InFlag; |
| 1835 | Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); |
| 1836 | InFlag = Chain.getValue(1); |
| 1837 | Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); |
| 1838 | InFlag = Chain.getValue(1); |
| 1839 | Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag); |
| 1840 | InFlag = Chain.getValue(1); |
| 1841 | |
| 1842 | return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain, |
| 1843 | DAG.getValueType(AVT), InFlag); |
| 1844 | } |
Evan Cheng | bbbb2fb | 2006-02-25 09:55:19 +0000 | [diff] [blame] | 1845 | |
| 1846 | // ConstantPool, GlobalAddress, and ExternalSymbol are lowered as their |
| 1847 | // target countpart wrapped in the X86ISD::Wrapper node. Suppose N is |
| 1848 | // one of the above mentioned nodes. It has to be wrapped because otherwise |
| 1849 | // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only |
| 1850 | // be used to form addressing mode. These wrapped nodes will be selected |
| 1851 | // into MOV32ri. |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1852 | case ISD::ConstantPool: { |
| 1853 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 1854 | SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), |
| 1855 | DAG.getTargetConstantPool(CP->get(), getPointerTy(), |
| 1856 | CP->getAlignment())); |
Evan Cheng | a0ea053 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 1857 | if (getTargetMachine().getSubtarget<X86Subtarget>().isTargetDarwin()) { |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1858 | // With PIC, the address is actually $g + Offset. |
Evan Cheng | 4c1aa86 | 2006-02-22 20:19:42 +0000 | [diff] [blame] | 1859 | if (getTargetMachine().getRelocationModel() == Reloc::PIC) |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1860 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 1861 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); |
| 1862 | } |
| 1863 | |
| 1864 | return Result; |
| 1865 | } |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 1866 | case ISD::GlobalAddress: { |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 1867 | GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); |
| 1868 | SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), |
| 1869 | DAG.getTargetGlobalAddress(GV, getPointerTy())); |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1870 | if (getTargetMachine(). |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1871 | getSubtarget<X86Subtarget>().isTargetDarwin()) { |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1872 | // With PIC, the address is actually $g + Offset. |
Evan Cheng | 4c1aa86 | 2006-02-22 20:19:42 +0000 | [diff] [blame] | 1873 | if (getTargetMachine().getRelocationModel() == Reloc::PIC) |
Evan Cheng | a0ea053 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 1874 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 1875 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1876 | |
| 1877 | // For Darwin, external and weak symbols are indirect, so we want to load |
| 1878 | // the value at address GV, not the value of GV itself. This means that |
| 1879 | // the GlobalAddress must be in the base or index register of the address, |
| 1880 | // not the GV offset field. |
Evan Cheng | 4c1aa86 | 2006-02-22 20:19:42 +0000 | [diff] [blame] | 1881 | if (getTargetMachine().getRelocationModel() != Reloc::Static && |
| 1882 | (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || |
| 1883 | (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()))) |
Evan Cheng | 2338c5c | 2006-02-07 08:38:37 +0000 | [diff] [blame] | 1884 | Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), |
Evan Cheng | a0ea053 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 1885 | Result, DAG.getSrcValue(NULL)); |
Evan Cheng | 2338c5c | 2006-02-07 08:38:37 +0000 | [diff] [blame] | 1886 | } |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 1887 | |
Evan Cheng | 002fe9b | 2006-01-12 07:56:47 +0000 | [diff] [blame] | 1888 | return Result; |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1889 | } |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 1890 | case ISD::ExternalSymbol: { |
| 1891 | const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); |
| 1892 | SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), |
| 1893 | DAG.getTargetExternalSymbol(Sym, getPointerTy())); |
| 1894 | if (getTargetMachine(). |
| 1895 | getSubtarget<X86Subtarget>().isTargetDarwin()) { |
| 1896 | // With PIC, the address is actually $g + Offset. |
| 1897 | if (getTargetMachine().getRelocationModel() == Reloc::PIC) |
| 1898 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 1899 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); |
| 1900 | } |
| 1901 | |
| 1902 | return Result; |
| 1903 | } |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 1904 | case ISD::VASTART: { |
| 1905 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
| 1906 | // memory location argument. |
| 1907 | // FIXME: Replace MVT::i32 with PointerTy |
| 1908 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); |
| 1909 | return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, |
| 1910 | Op.getOperand(1), Op.getOperand(2)); |
| 1911 | } |
Nate Begeman | ee62557 | 2006-01-27 21:09:22 +0000 | [diff] [blame] | 1912 | case ISD::RET: { |
| 1913 | SDOperand Copy; |
| 1914 | |
| 1915 | switch(Op.getNumOperands()) { |
| 1916 | default: |
| 1917 | assert(0 && "Do not know how to return this many arguments!"); |
| 1918 | abort(); |
| 1919 | case 1: |
| 1920 | return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), |
| 1921 | DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); |
| 1922 | case 2: { |
| 1923 | MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); |
| 1924 | if (MVT::isInteger(ArgVT)) |
| 1925 | Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1), |
| 1926 | SDOperand()); |
| 1927 | else if (!X86ScalarSSE) { |
| 1928 | std::vector<MVT::ValueType> Tys; |
| 1929 | Tys.push_back(MVT::Other); |
| 1930 | Tys.push_back(MVT::Flag); |
| 1931 | std::vector<SDOperand> Ops; |
| 1932 | Ops.push_back(Op.getOperand(0)); |
| 1933 | Ops.push_back(Op.getOperand(1)); |
| 1934 | Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); |
| 1935 | } else { |
Evan Cheng | 0d084c9 | 2006-02-01 00:20:21 +0000 | [diff] [blame] | 1936 | SDOperand MemLoc; |
| 1937 | SDOperand Chain = Op.getOperand(0); |
Evan Cheng | 0e8671b | 2006-01-31 23:19:54 +0000 | [diff] [blame] | 1938 | SDOperand Value = Op.getOperand(1); |
| 1939 | |
Evan Cheng | 760df29 | 2006-02-01 01:19:32 +0000 | [diff] [blame] | 1940 | if (Value.getOpcode() == ISD::LOAD && |
| 1941 | (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) { |
Evan Cheng | 0e8671b | 2006-01-31 23:19:54 +0000 | [diff] [blame] | 1942 | Chain = Value.getOperand(0); |
| 1943 | MemLoc = Value.getOperand(1); |
| 1944 | } else { |
| 1945 | // Spill the value to memory and reload it into top of stack. |
| 1946 | unsigned Size = MVT::getSizeInBits(ArgVT)/8; |
| 1947 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1948 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
| 1949 | MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 1950 | Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), |
| 1951 | Value, MemLoc, DAG.getSrcValue(0)); |
| 1952 | } |
Nate Begeman | ee62557 | 2006-01-27 21:09:22 +0000 | [diff] [blame] | 1953 | std::vector<MVT::ValueType> Tys; |
| 1954 | Tys.push_back(MVT::f64); |
| 1955 | Tys.push_back(MVT::Other); |
| 1956 | std::vector<SDOperand> Ops; |
| 1957 | Ops.push_back(Chain); |
Evan Cheng | 0e8671b | 2006-01-31 23:19:54 +0000 | [diff] [blame] | 1958 | Ops.push_back(MemLoc); |
Nate Begeman | ee62557 | 2006-01-27 21:09:22 +0000 | [diff] [blame] | 1959 | Ops.push_back(DAG.getValueType(ArgVT)); |
| 1960 | Copy = DAG.getNode(X86ISD::FLD, Tys, Ops); |
| 1961 | Tys.clear(); |
| 1962 | Tys.push_back(MVT::Other); |
| 1963 | Tys.push_back(MVT::Flag); |
| 1964 | Ops.clear(); |
| 1965 | Ops.push_back(Copy.getValue(1)); |
| 1966 | Ops.push_back(Copy); |
| 1967 | Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); |
| 1968 | } |
| 1969 | break; |
| 1970 | } |
| 1971 | case 3: |
| 1972 | Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2), |
| 1973 | SDOperand()); |
| 1974 | Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1)); |
| 1975 | break; |
| 1976 | } |
| 1977 | return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, |
| 1978 | Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), |
| 1979 | Copy.getValue(1)); |
| 1980 | } |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 1981 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1982 | } |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1983 | |
| 1984 | const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 1985 | switch (Opcode) { |
| 1986 | default: return NULL; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1987 | case X86ISD::SHLD: return "X86ISD::SHLD"; |
| 1988 | case X86ISD::SHRD: return "X86ISD::SHRD"; |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 1989 | case X86ISD::FAND: return "X86ISD::FAND"; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 1990 | case X86ISD::FXOR: return "X86ISD::FXOR"; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 1991 | case X86ISD::FILD: return "X86ISD::FILD"; |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 1992 | case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 1993 | case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; |
| 1994 | case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; |
| 1995 | case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1996 | case X86ISD::FLD: return "X86ISD::FLD"; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 1997 | case X86ISD::FST: return "X86ISD::FST"; |
| 1998 | case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 1999 | case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 2000 | case X86ISD::CALL: return "X86ISD::CALL"; |
| 2001 | case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; |
| 2002 | case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; |
| 2003 | case X86ISD::CMP: return "X86ISD::CMP"; |
| 2004 | case X86ISD::TEST: return "X86ISD::TEST"; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2005 | case X86ISD::SETCC: return "X86ISD::SETCC"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 2006 | case X86ISD::CMOV: return "X86ISD::CMOV"; |
| 2007 | case X86ISD::BRCOND: return "X86ISD::BRCOND"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 2008 | case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 2009 | case X86ISD::REP_STOS: return "X86ISD::RET_STOS"; |
| 2010 | case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS"; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 2011 | case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 2012 | case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 2013 | case X86ISD::Wrapper: return "X86ISD::Wrapper"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 2014 | } |
| 2015 | } |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 2016 | |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 2017 | void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, |
| 2018 | uint64_t Mask, |
| 2019 | uint64_t &KnownZero, |
| 2020 | uint64_t &KnownOne, |
| 2021 | unsigned Depth) const { |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 2022 | |
| 2023 | unsigned Opc = Op.getOpcode(); |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 2024 | KnownZero = KnownOne = 0; // Don't know anything. |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 2025 | |
| 2026 | switch (Opc) { |
| 2027 | default: |
| 2028 | assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node"); |
| 2029 | break; |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 2030 | case X86ISD::SETCC: |
| 2031 | KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); |
| 2032 | break; |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 2033 | } |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 2034 | } |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 2035 | |
| 2036 | std::vector<unsigned> X86TargetLowering:: |
Chris Lattner | 1efa40f | 2006-02-22 00:56:39 +0000 | [diff] [blame] | 2037 | getRegClassForInlineAsmConstraint(const std::string &Constraint, |
| 2038 | MVT::ValueType VT) const { |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 2039 | if (Constraint.size() == 1) { |
| 2040 | // FIXME: not handling fp-stack yet! |
| 2041 | // FIXME: not handling MMX registers yet ('y' constraint). |
| 2042 | switch (Constraint[0]) { // GCC X86 Constraint Letters |
| 2043 | default: break; // Unknown constriant letter |
| 2044 | case 'r': // GENERAL_REGS |
| 2045 | case 'R': // LEGACY_REGS |
| 2046 | return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, |
| 2047 | X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); |
| 2048 | case 'l': // INDEX_REGS |
| 2049 | return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, |
| 2050 | X86::ESI, X86::EDI, X86::EBP, 0); |
| 2051 | case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) |
| 2052 | case 'Q': // Q_REGS |
| 2053 | return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0); |
| 2054 | case 'x': // SSE_REGS if SSE1 allowed |
| 2055 | if (Subtarget->hasSSE1()) |
| 2056 | return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, |
| 2057 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, |
| 2058 | 0); |
| 2059 | return std::vector<unsigned>(); |
| 2060 | case 'Y': // SSE_REGS if SSE2 allowed |
| 2061 | if (Subtarget->hasSSE2()) |
| 2062 | return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, |
| 2063 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, |
| 2064 | 0); |
| 2065 | return std::vector<unsigned>(); |
| 2066 | } |
| 2067 | } |
| 2068 | |
Chris Lattner | 1efa40f | 2006-02-22 00:56:39 +0000 | [diff] [blame] | 2069 | return std::vector<unsigned>(); |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 2070 | } |