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gerrit-public.fairphone.software / platform / external / llvm / d77104182819d8f45b7128e609beae951b2b32a0 / . / test / CodeGen / ARM / long_shift.ll
blob: 1ec4d15f66723da32ad59f9a0c55320e86592e8c [file] [log] [blame]
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]1; RUN: llc < %s -march=arm | FileCheck %s
Evan Cheng02b985c2007-01-19 09:20:23 +0000[diff] [blame]2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]3define i64 @f0(i64 %A, i64 %B) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]4; CHECK: f0
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]5; CHECK: movs r3, r3, lsr #1
6; CHECK-NEXT: mov r2, r2, rrx
7; CHECK-NEXT: subs r0, r0, r2
8; CHECK-NEXT: sbc r1, r1, r3
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]9 %tmp = bitcast i64 %A to i64
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]10 %tmp2 = lshr i64 %B, 1
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]11 %tmp3 = sub i64 %tmp, %tmp2
12 ret i64 %tmp3
Evan Cheng02b985c2007-01-19 09:20:23 +0000[diff] [blame]13}
14
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]15define i32 @f1(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]16; CHECK: f1
Jim Grosbachc2b879f2009-10-31 19:38:01 +0000[diff] [blame]17; CHECK: mov r0, r0, lsl r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]18 %a = shl i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]19 %b = trunc i64 %a to i32
20 ret i32 %b
21}
22
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]23define i32 @f2(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]24; CHECK: f2
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]25; CHECK: mov r0, r0, lsr r2
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]26; CHECK-NEXT: rsb r3, r2, #32
Bill Wendlingd7710412010-08-11 01:05:02 +0000[diff] [blame^]27; CHECK-NEXT: subs r2, r2, #32
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]28; CHECK-NEXT: orr r0, r0, r1, lsl r3
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]29; CHECK-NEXT: movge r0, r1, asr r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]30 %a = ashr i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]31 %b = trunc i64 %a to i32
32 ret i32 %b
33}
34
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]35define i32 @f3(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]36; CHECK: f3
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]37; CHECK: mov r0, r0, lsr r2
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]38; CHECK-NEXT: rsb r3, r2, #32
Bill Wendlingd7710412010-08-11 01:05:02 +0000[diff] [blame^]39; CHECK-NEXT: subs r2, r2, #32
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]40; CHECK-NEXT: orr r0, r0, r1, lsl r3
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]41; CHECK-NEXT: movge r0, r1, lsr r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]42 %a = lshr i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]43 %b = trunc i64 %a to i32
44 ret i32 %b
45}