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gerrit-public.fairphone.software / platform / external / llvm / e906921480beacea2dea2d5ce8156bc246ee12a7 / . / test / CodeGen / ARM / machine-licm.ll
blob: 5d2f1fd31239c275890d8e818a69a566d80f54b3 [file] [log] [blame]
Evan Cheng9fe20092011-01-20 08:34:58 +0000[diff] [blame]1; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB
2; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM
Evan Chengab56e312011-01-20 08:38:21 +0000[diff] [blame]3; RUN: llc < %s -mtriple=armv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -arm-darwin-use-movt | FileCheck %s -check-prefix=MOVT
Evan Chengd457e6e2009-11-07 04:04:34 +0000[diff] [blame]4; rdar://7353541
5; rdar://7354376
Evan Chengab56e312011-01-20 08:38:21 +0000[diff] [blame]6; rdar://8887598
Evan Chengd457e6e2009-11-07 04:04:34 +0000[diff] [blame]7
8; The generated code is no where near ideal. It's not recognizing the two
9; constantpool entries being loaded can be merged into one.
10
11@GV = external global i32 ; <i32*> [#uses=2]
12
Rafael Espindola1e819662010-06-17 15:18:27 +0000[diff] [blame]13define void @t(i32* nocapture %vals, i32 %c) nounwind {
Evan Chengd457e6e2009-11-07 04:04:34 +0000[diff] [blame]14entry:
Evan Cheng9fe20092011-01-20 08:34:58 +0000[diff] [blame]15; ARM: t:
16; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
17; ARM-NOT: ldr r{{[0-9]+}}, LCPI0_1
18; ARM: LPC0_0:
19; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
20; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
21
Evan Chengab56e312011-01-20 08:38:21 +0000[diff] [blame]22; MOVT: t:
23; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
24; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
25; MOVT: LPC0_0:
26; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
27; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
28
Evan Cheng9fe20092011-01-20 08:34:58 +0000[diff] [blame]29; THUMB: t:
Evan Chengd457e6e2009-11-07 04:04:34 +0000[diff] [blame]30 %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
31 br i1 %0, label %return, label %bb.nph
32
33bb.nph: ; preds = %entry
Evan Cheng9fe20092011-01-20 08:34:58 +0000[diff] [blame]34; ARM: LCPI0_0:
35; ARM-NOT: LCPI0_1:
36; ARM: .section
37
38; THUMB: BB#1
39; THUMB: ldr.n r2, LCPI0_0
40; THUMB: add r2, pc
41; THUMB: ldr r{{[0-9]+}}, [r2]
42; THUMB: LBB0_2
43; THUMB: LCPI0_0:
44; THUMB-NOT: LCPI0_1:
45; THUMB: .section
Evan Chengd457e6e2009-11-07 04:04:34 +0000[diff] [blame]46 %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
47 br label %bb
48
49bb: ; preds = %bb, %bb.nph
50 %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
51 %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
52 %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
53 %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
54 %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
55 store i32 %3, i32* @GV, align 4
56 %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
57 %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
58 br i1 %exitcond, label %return, label %bb
59
60return: ; preds = %bb, %entry
61 ret void
62}