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gerrit-public.fairphone.software / platform / external / llvm / d901b6640e0f1d1757a2db9fb57a140ad828ea75 / . / test / CodeGen / X86 / atomic_op.ll
blob: 6871a08b29e6a5db8c8027eb302e66398edab169 [file] [log] [blame]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]1; RUN: llvm-as < %s | llc -march=x86 -o %t1 -f
Dale Johannesend20e4452008-08-19 18:47:28 +0000[diff] [blame]2; RUN: grep "lock" %t1 | count 17
3; RUN: grep "xaddl" %t1 | count 4
4; RUN: grep "cmpxchgl" %t1 | count 13
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]5; RUN: grep "xchgl" %t1 | count 14
6; RUN: grep "cmova" %t1 | count 2
7; RUN: grep "cmovb" %t1 | count 2
8; RUN: grep "cmovg" %t1 | count 2
9; RUN: grep "cmovl" %t1 | count 2
10
11target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
12
13define void @main(i32 %argc, i8** %argv) {
14entry:
15 %argc.addr = alloca i32 ; <i32*> [#uses=1]
16 %argv.addr = alloca i8** ; <i8***> [#uses=1]
17 %val1 = alloca i32 ; <i32*> [#uses=2]
18 %val2 = alloca i32 ; <i32*> [#uses=15]
19 %andt = alloca i32 ; <i32*> [#uses=2]
20 %ort = alloca i32 ; <i32*> [#uses=2]
21 %xort = alloca i32 ; <i32*> [#uses=2]
22 %old = alloca i32 ; <i32*> [#uses=18]
23 %temp = alloca i32 ; <i32*> [#uses=2]
24 store i32 %argc, i32* %argc.addr
25 store i8** %argv, i8*** %argv.addr
26 store i32 0, i32* %val1
27 store i32 31, i32* %val2
28 store i32 3855, i32* %andt
29 store i32 3855, i32* %ort
30 store i32 3855, i32* %xort
31 store i32 4, i32* %temp
32 %tmp = load i32* %temp ; <i32> [#uses=1]
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]33 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]34 store i32 %0, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]35 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]36 store i32 %1, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]37 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]38 store i32 %2, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]39 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]40 store i32 %3, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]41 call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]42 store i32 %4, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]43 call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]44 store i32 %5, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]45 call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]46 store i32 %6, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]47 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]48 store i32 %7, i32* %old
49 %neg = sub i32 0, 1 ; <i32> [#uses=1]
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]50 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]51 store i32 %8, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]52 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]53 store i32 %9, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]54 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]55 store i32 %10, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]56 call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 65535 ) ; <i32>:11 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]57 store i32 %11, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]58 call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:12 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]59 store i32 %12, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]60 call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:13 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]61 store i32 %13, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]62 call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:14 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]63 store i32 %14, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]64 call i32 @llvm.atomic.swap.i32.p0i32( i32* %val2, i32 1976 ) ; <i32>:15 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]65 store i32 %15, i32* %old
66 %neg1 = sub i32 0, 10 ; <i32> [#uses=1]
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]67 call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 %neg1, i32 1 ) ; <i32>:16 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]68 store i32 %16, i32* %old
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]69 call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 1976, i32 1 ) ; <i32>:17 [#uses=1]
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]70 store i32 %17, i32* %old
71 ret void
72}
73
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]74declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]75
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]76declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]77
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]78declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]79
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]80declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]81
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]82declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]83
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]84declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]85
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]86declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]87
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]88declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]89
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]90declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]91
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]92declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
Mon P Wang078a62d2008-05-05 19:05:59 +0000[diff] [blame]93
Mon P Wangce3ac892008-07-30 04:36:53 +0000[diff] [blame]94declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind