Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / llvm / 4eacb6723b76c6348f4fd4606df1165ccb2878c4 / . / lib / Target / ARM / ARMInstrNEON.td
blob: 3fd63f01b3494f6e98d5f8ace36d1fe9483f95fd [file] [log] [blame]
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// NEON-specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19
20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
26
27// Types for vector shift by immediates. The "SHX" version is for long and
28// narrow operations where the source and destination vectors have different
29// types. The "SHINS" version is for shift and insert operations.
30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>]>;
32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
33 SDTCisVT<2, i32>]>;
34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
36
37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
44
45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
48
49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
55
56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
59
60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
62
63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
64 SDTCisVT<2, i32>]>;
65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
67
68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
70
71//===----------------------------------------------------------------------===//
72// NEON operand definitions
73//===----------------------------------------------------------------------===//
74
75// addrmode_neonldstm := reg
76//
77/* TODO: Take advantage of vldm.
78def addrmode_neonldstm : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
80 let PrintMethod = "printAddrNeonLdStMOperand";
81 let MIOperandInfo = (ops GPR, i32imm);
82}
83*/
84
85//===----------------------------------------------------------------------===//
86// NEON load / store instructions
87//===----------------------------------------------------------------------===//
88
89/* TODO: Take advantage of vldm.
90let mayLoad = 1 in {
91def VLDMD : NI<(outs),
92 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
93 "vldm${addr:submode} ${addr:base}, $dst1",
94 []>;
95
96def VLDMS : NI<(outs),
97 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
98 "vldm${addr:submode} ${addr:base}, $dst1",
99 []>;
100}
101*/
102
103// Use vldmia to load a Q register as a D register pair.
104def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
105 "vldmia $addr, ${dst:dregpair}",
106 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]>;
107
108// Use vstmia to store a Q register as a D register pair.
109def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
110 "vstmia $addr, ${src:dregpair}",
111 [(store (v2f64 QPR:$src), GPR:$addr)]>;
112
113
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]114// VLD1 : Vector Load (multiple single elements)
115class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
116 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
117 !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
118 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr, 1)))]>;
119class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
120 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
121 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
122 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr, 1)))]>;
123
124def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vldi>;
125def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vldi>;
126def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vldi>;
127def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vldf>;
128def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vldi>;
129
130def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vldi>;
131def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vldi>;
132def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vldi>;
133def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vldf>;
134def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vldi>;
135
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]136// VST1 : Vector Store (multiple single elements)
137class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
138 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
139 !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
140 [(IntOp addrmode6:$addr, (Ty DPR:$src), 1)]>;
141class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
142 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
143 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
144 [(IntOp addrmode6:$addr, (Ty QPR:$src), 1)]>;
145
146def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vsti>;
147def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vsti>;
148def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vsti>;
149def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vstf>;
150def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vsti>;
151
152def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vsti>;
153def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vsti>;
154def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vsti>;
155def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vstf>;
156def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vsti>;
157
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]158
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]159//===----------------------------------------------------------------------===//
160// NEON pattern fragments
161//===----------------------------------------------------------------------===//
162
163// Extract D sub-registers of Q registers.
164// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
165def SubReg_i8_reg : SDNodeXForm<imm, [{
166 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
167}]>;
168def SubReg_i16_reg : SDNodeXForm<imm, [{
169 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
170}]>;
171def SubReg_i32_reg : SDNodeXForm<imm, [{
172 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
173}]>;
174def SubReg_f64_reg : SDNodeXForm<imm, [{
175 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
176}]>;
177
178// Translate lane numbers from Q registers to D subregs.
179def SubReg_i8_lane : SDNodeXForm<imm, [{
180 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
181}]>;
182def SubReg_i16_lane : SDNodeXForm<imm, [{
183 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
184}]>;
185def SubReg_i32_lane : SDNodeXForm<imm, [{
186 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
187}]>;
188
189//===----------------------------------------------------------------------===//
190// Instruction Classes
191//===----------------------------------------------------------------------===//
192
193// Basic 2-register operations, both double- and quad-register.
194class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
195 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
196 ValueType ResTy, ValueType OpTy, SDNode OpNode>
197 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
198 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
199 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
200class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
201 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
202 ValueType ResTy, ValueType OpTy, SDNode OpNode>
203 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
204 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
205 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
206
207// Basic 2-register intrinsics, both double- and quad-register.
208class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
209 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
210 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
211 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
212 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
213 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
214class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
215 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
216 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
217 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
218 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
219 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
220
221// Narrow 2-register intrinsics.
222class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
223 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
224 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
225 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
226 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
227 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
228
229// Long 2-register intrinsics. (This is currently only used for VMOVL and is
230// derived from N2VImm instead of N2V because of the way the size is encoded.)
231class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
232 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
233 Intrinsic IntOp>
234 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
235 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
236 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
237
238// Basic 3-register operations, both double- and quad-register.
239class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
240 string OpcodeStr, ValueType ResTy, ValueType OpTy,
241 SDNode OpNode, bit Commutable>
242 : N3V<op24, op23, op21_20, op11_8, 0, op4,
243 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
244 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
245 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
246 let isCommutable = Commutable;
247}
248class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
249 string OpcodeStr, ValueType ResTy, ValueType OpTy,
250 SDNode OpNode, bit Commutable>
251 : N3V<op24, op23, op21_20, op11_8, 1, op4,
252 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
253 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
254 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
255 let isCommutable = Commutable;
256}
257
258// Basic 3-register intrinsics, both double- and quad-register.
259class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
260 string OpcodeStr, ValueType ResTy, ValueType OpTy,
261 Intrinsic IntOp, bit Commutable>
262 : N3V<op24, op23, op21_20, op11_8, 0, op4,
263 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
264 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
265 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
266 let isCommutable = Commutable;
267}
268class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
269 string OpcodeStr, ValueType ResTy, ValueType OpTy,
270 Intrinsic IntOp, bit Commutable>
271 : N3V<op24, op23, op21_20, op11_8, 1, op4,
272 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
273 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
274 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
275 let isCommutable = Commutable;
276}
277
278// Multiply-Add/Sub operations, both double- and quad-register.
279class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
280 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
281 : N3V<op24, op23, op21_20, op11_8, 0, op4,
282 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
283 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
284 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
285 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
286class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
287 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
288 : N3V<op24, op23, op21_20, op11_8, 1, op4,
289 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
290 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
291 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
292 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
293
294// Neon 3-argument intrinsics, both double- and quad-register.
295// The destination register is also used as the first source operand register.
296class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
297 string OpcodeStr, ValueType ResTy, ValueType OpTy,
298 Intrinsic IntOp>
299 : N3V<op24, op23, op21_20, op11_8, 0, op4,
300 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
301 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
302 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
303 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
304class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
305 string OpcodeStr, ValueType ResTy, ValueType OpTy,
306 Intrinsic IntOp>
307 : N3V<op24, op23, op21_20, op11_8, 1, op4,
308 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
309 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
310 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
311 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
312
313// Neon Long 3-argument intrinsic. The destination register is
314// a quad-register and is also used as the first source operand register.
315class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
316 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
317 : N3V<op24, op23, op21_20, op11_8, 0, op4,
318 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
319 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
320 [(set QPR:$dst,
321 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
322
323// Narrowing 3-register intrinsics.
324class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
325 string OpcodeStr, ValueType TyD, ValueType TyQ,
326 Intrinsic IntOp, bit Commutable>
327 : N3V<op24, op23, op21_20, op11_8, 0, op4,
328 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
329 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
330 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
331 let isCommutable = Commutable;
332}
333
334// Long 3-register intrinsics.
335class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
336 string OpcodeStr, ValueType TyQ, ValueType TyD,
337 Intrinsic IntOp, bit Commutable>
338 : N3V<op24, op23, op21_20, op11_8, 0, op4,
339 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
340 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
341 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
342 let isCommutable = Commutable;
343}
344
345// Wide 3-register intrinsics.
346class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
347 string OpcodeStr, ValueType TyQ, ValueType TyD,
348 Intrinsic IntOp, bit Commutable>
349 : N3V<op24, op23, op21_20, op11_8, 0, op4,
350 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
351 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
352 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
353 let isCommutable = Commutable;
354}
355
356// Pairwise long 2-register intrinsics, both double- and quad-register.
357class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
358 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
359 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
360 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
361 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
362 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
363class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
364 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
365 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
366 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
367 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
368 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
369
370// Pairwise long 2-register accumulate intrinsics,
371// both double- and quad-register.
372// The destination register is also used as the first source operand register.
373class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
374 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
375 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
376 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
377 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
378 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
379 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
380class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
381 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
382 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
383 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
384 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
385 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
386 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
387
388// Shift by immediate,
389// both double- and quad-register.
390class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
391 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
392 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
393 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
394 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
395 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
396class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
397 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
398 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
399 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
400 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
401 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
402
403// Long shift by immediate.
404class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
405 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
406 ValueType OpTy, SDNode OpNode>
407 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
408 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
409 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
410 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
411 (i32 imm:$SIMM))))]>;
412
413// Narrow shift by immediate.
414class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
415 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
416 ValueType OpTy, SDNode OpNode>
417 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
418 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
419 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
420 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
421 (i32 imm:$SIMM))))]>;
422
423// Shift right by immediate and accumulate,
424// both double- and quad-register.
425class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
426 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
427 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
428 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
429 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
430 [(set DPR:$dst, (Ty (add DPR:$src1,
431 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
432class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
433 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
434 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
435 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
436 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
437 [(set QPR:$dst, (Ty (add QPR:$src1,
438 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
439
440// Shift by immediate and insert,
441// both double- and quad-register.
442class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
443 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
444 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
445 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
446 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
447 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
448class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
449 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
450 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
451 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
452 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
453 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
454
455// Convert, with fractional bits immediate,
456// both double- and quad-register.
457class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
458 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
459 Intrinsic IntOp>
460 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
461 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
462 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
463 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
464class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
465 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
466 Intrinsic IntOp>
467 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
468 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
469 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
470 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
471
472//===----------------------------------------------------------------------===//
473// Multiclasses
474//===----------------------------------------------------------------------===//
475
476// Neon 3-register vector operations.
477
478// First with only element sizes of 8, 16 and 32 bits:
479multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
480 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
481 // 64-bit vector types.
482 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
483 v8i8, v8i8, OpNode, Commutable>;
484 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
485 v4i16, v4i16, OpNode, Commutable>;
486 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
487 v2i32, v2i32, OpNode, Commutable>;
488
489 // 128-bit vector types.
490 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
491 v16i8, v16i8, OpNode, Commutable>;
492 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
493 v8i16, v8i16, OpNode, Commutable>;
494 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
495 v4i32, v4i32, OpNode, Commutable>;
496}
497
498// ....then also with element size 64 bits:
499multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
500 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
501 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
502 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
503 v1i64, v1i64, OpNode, Commutable>;
504 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
505 v2i64, v2i64, OpNode, Commutable>;
506}
507
508
509// Neon Narrowing 2-register vector intrinsics,
510// source operand element sizes of 16, 32 and 64 bits:
511multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
512 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
513 Intrinsic IntOp> {
514 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
515 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
516 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
517 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
518 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
519 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
520}
521
522
523// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
524// source operand element sizes of 16, 32 and 64 bits:
525multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
526 bit op4, string OpcodeStr, Intrinsic IntOp> {
527 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
528 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
529 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
530 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
531 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
532 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
533}
534
535
536// Neon 3-register vector intrinsics.
537
538// First with only element sizes of 16 and 32 bits:
539multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
540 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
541 // 64-bit vector types.
542 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
543 v4i16, v4i16, IntOp, Commutable>;
544 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
545 v2i32, v2i32, IntOp, Commutable>;
546
547 // 128-bit vector types.
548 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
549 v8i16, v8i16, IntOp, Commutable>;
550 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
551 v4i32, v4i32, IntOp, Commutable>;
552}
553
554// ....then also with element size of 8 bits:
555multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
556 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
557 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
558 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
559 v8i8, v8i8, IntOp, Commutable>;
560 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
561 v16i8, v16i8, IntOp, Commutable>;
562}
563
564// ....then also with element size of 64 bits:
565multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
566 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
567 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
568 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
569 v1i64, v1i64, IntOp, Commutable>;
570 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
571 v2i64, v2i64, IntOp, Commutable>;
572}
573
574
575// Neon Narrowing 3-register vector intrinsics,
576// source operand element sizes of 16, 32 and 64 bits:
577multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
578 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
579 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
580 v8i8, v8i16, IntOp, Commutable>;
581 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
582 v4i16, v4i32, IntOp, Commutable>;
583 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
584 v2i32, v2i64, IntOp, Commutable>;
585}
586
587
588// Neon Long 3-register vector intrinsics.
589
590// First with only element sizes of 16 and 32 bits:
591multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
592 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
593 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
594 v4i32, v4i16, IntOp, Commutable>;
595 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
596 v2i64, v2i32, IntOp, Commutable>;
597}
598
599// ....then also with element size of 8 bits:
600multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
601 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
602 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
603 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
604 v8i16, v8i8, IntOp, Commutable>;
605}
606
607
608// Neon Wide 3-register vector intrinsics,
609// source operand element sizes of 8, 16 and 32 bits:
610multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
611 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
612 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
613 v8i16, v8i8, IntOp, Commutable>;
614 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
615 v4i32, v4i16, IntOp, Commutable>;
616 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
617 v2i64, v2i32, IntOp, Commutable>;
618}
619
620
621// Neon Multiply-Op vector operations,
622// element sizes of 8, 16 and 32 bits:
623multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
624 string OpcodeStr, SDNode OpNode> {
625 // 64-bit vector types.
626 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
627 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
628 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
629 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
630 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
631 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
632
633 // 128-bit vector types.
634 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
635 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
636 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
637 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
638 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
639 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
640}
641
642
643// Neon 3-argument intrinsics,
644// element sizes of 8, 16 and 32 bits:
645multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
646 string OpcodeStr, Intrinsic IntOp> {
647 // 64-bit vector types.
648 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
649 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
650 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
651 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
652 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
653 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
654
655 // 128-bit vector types.
656 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
657 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
658 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
659 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
660 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
661 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
662}
663
664
665// Neon Long 3-argument intrinsics.
666
667// First with only element sizes of 16 and 32 bits:
668multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
669 string OpcodeStr, Intrinsic IntOp> {
670 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
671 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
672 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
673 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
674}
675
676// ....then also with element size of 8 bits:
677multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
678 string OpcodeStr, Intrinsic IntOp>
679 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
680 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
681 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
682}
683
684
685// Neon 2-register vector intrinsics,
686// element sizes of 8, 16 and 32 bits:
687multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
688 bits<5> op11_7, bit op4, string OpcodeStr,
689 Intrinsic IntOp> {
690 // 64-bit vector types.
691 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
692 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
693 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
694 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
695 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
696 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
697
698 // 128-bit vector types.
699 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
700 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
701 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
702 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
703 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
704 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
705}
706
707
708// Neon Pairwise long 2-register intrinsics,
709// element sizes of 8, 16 and 32 bits:
710multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
711 bits<5> op11_7, bit op4,
712 string OpcodeStr, Intrinsic IntOp> {
713 // 64-bit vector types.
714 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
715 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
716 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
717 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
718 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
719 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
720
721 // 128-bit vector types.
722 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
723 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
724 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
725 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
726 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
727 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
728}
729
730
731// Neon Pairwise long 2-register accumulate intrinsics,
732// element sizes of 8, 16 and 32 bits:
733multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
734 bits<5> op11_7, bit op4,
735 string OpcodeStr, Intrinsic IntOp> {
736 // 64-bit vector types.
737 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
738 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
739 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
740 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
741 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
742 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
743
744 // 128-bit vector types.
745 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
746 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
747 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
748 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
749 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
750 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
751}
752
753
754// Neon 2-register vector shift by immediate,
755// element sizes of 8, 16, 32 and 64 bits:
756multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
757 string OpcodeStr, SDNode OpNode> {
758 // 64-bit vector types.
759 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
760 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
761 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
762 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
763 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
764 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
765 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
766 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
767
768 // 128-bit vector types.
769 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
770 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
771 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
772 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
773 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
774 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
775 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
776 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
777}
778
779
780// Neon Shift-Accumulate vector operations,
781// element sizes of 8, 16, 32 and 64 bits:
782multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
783 string OpcodeStr, SDNode ShOp> {
784 // 64-bit vector types.
785 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
786 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
787 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
788 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
789 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
790 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
791 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
792 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
793
794 // 128-bit vector types.
795 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
796 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
797 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
798 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
799 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
800 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
801 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
802 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
803}
804
805
806// Neon Shift-Insert vector operations,
807// element sizes of 8, 16, 32 and 64 bits:
808multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
809 string OpcodeStr, SDNode ShOp> {
810 // 64-bit vector types.
811 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
812 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
813 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
814 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
815 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
816 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
817 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
818 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
819
820 // 128-bit vector types.
821 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
822 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
823 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
824 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
825 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
826 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
827 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
828 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
829}
830
831//===----------------------------------------------------------------------===//
832// Instruction Definitions.
833//===----------------------------------------------------------------------===//
834
835// Vector Add Operations.
836
837// VADD : Vector Add (integer and floating-point)
838defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
839def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
840def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
841// VADDL : Vector Add Long (Q = D + D)
842defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
843defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
844// VADDW : Vector Add Wide (Q = Q + D)
845defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
846defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
847// VHADD : Vector Halving Add
848defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
849defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
850// VRHADD : Vector Rounding Halving Add
851defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
852defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
853// VQADD : Vector Saturating Add
854defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
855defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
856// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
857defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
858// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
859defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
860
861// Vector Multiply Operations.
862
863// VMUL : Vector Multiply (integer, polynomial and floating-point)
864defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
865def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
866 int_arm_neon_vmulp, 1>;
867def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
868 int_arm_neon_vmulp, 1>;
869def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
870def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
871// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
872defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
873// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
874defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
875// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
876defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
877defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
878def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
879 int_arm_neon_vmullp, 1>;
880// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
881defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
882
883// Vector Multiply-Accumulate and Multiply-Subtract Operations.
884
885// VMLA : Vector Multiply Accumulate (integer and floating-point)
886defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
887def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
888def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
889// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
890defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
891defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
892// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
893defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
894// VMLS : Vector Multiply Subtract (integer and floating-point)
895defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
896def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
897def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
898// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
899defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
900defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
901// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
902defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
903
904// Vector Subtract Operations.
905
906// VSUB : Vector Subtract (integer and floating-point)
907defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
908def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
909def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
910// VSUBL : Vector Subtract Long (Q = D - D)
911defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
912defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
913// VSUBW : Vector Subtract Wide (Q = Q - D)
914defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
915defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
916// VHSUB : Vector Halving Subtract
917defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
918defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
919// VQSUB : Vector Saturing Subtract
920defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
921defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
922// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
923defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
924// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
925defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
926
927// Vector Comparisons.
928
929// VCEQ : Vector Compare Equal
930defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
931def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
932def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
933// VCGE : Vector Compare Greater Than or Equal
934defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
935defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
936def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
937def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
938// VCGT : Vector Compare Greater Than
939defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
940defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
941def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
942def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
943// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
944def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
945 int_arm_neon_vacged, 0>;
946def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
947 int_arm_neon_vacgeq, 0>;
948// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
949def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
950 int_arm_neon_vacgtd, 0>;
951def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
952 int_arm_neon_vacgtq, 0>;
953// VTST : Vector Test Bits
954defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
955
956// Vector Bitwise Operations.
957
958// VAND : Vector Bitwise AND
959def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
960def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
961
962// VEOR : Vector Bitwise Exclusive OR
963def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
964def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
965
966// VORR : Vector Bitwise OR
967def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
968def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
969
970// VBIC : Vector Bitwise Bit Clear (AND NOT)
971def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
972 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
973 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
974def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
975 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
976 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
977
978// VORN : Vector Bitwise OR NOT
979def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
980 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
981 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
982def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
983 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
984 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
985
986// VMVN : Vector Bitwise NOT
987def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
988 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
989 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
990def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
991 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
992 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
993def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
994def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
995
996// VBSL : Vector Bitwise Select
997def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
998 (ins DPR:$src1, DPR:$src2, DPR:$src3),
999 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1000 [(set DPR:$dst,
1001 (v2i32 (or (and DPR:$src2, DPR:$src1),
1002 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1003def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1004 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1005 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1006 [(set QPR:$dst,
1007 (v4i32 (or (and QPR:$src2, QPR:$src1),
1008 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1009
1010// VBIF : Vector Bitwise Insert if False
1011// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1012// VBIT : Vector Bitwise Insert if True
1013// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1014// These are not yet implemented. The TwoAddress pass will not go looking
1015// for equivalent operations with different register constraints; it just
1016// inserts copies.
1017
1018// Vector Absolute Differences.
1019
1020// VABD : Vector Absolute Difference
1021defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1022defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1023def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1024 int_arm_neon_vabdf, 0>;
1025def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1026 int_arm_neon_vabdf, 0>;
1027
1028// VABDL : Vector Absolute Difference Long (Q = | D - D |)
1029defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1030defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1031
1032// VABA : Vector Absolute Difference and Accumulate
1033defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1034defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1035
1036// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1037defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1038defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1039
1040// Vector Maximum and Minimum.
1041
1042// VMAX : Vector Maximum
1043defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1044defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1045def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1046 int_arm_neon_vmaxf, 1>;
1047def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1048 int_arm_neon_vmaxf, 1>;
1049
1050// VMIN : Vector Minimum
1051defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1052defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1053def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1054 int_arm_neon_vminf, 1>;
1055def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1056 int_arm_neon_vminf, 1>;
1057
1058// Vector Pairwise Operations.
1059
1060// VPADD : Vector Pairwise Add
1061def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1062 int_arm_neon_vpaddi, 0>;
1063def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1064 int_arm_neon_vpaddi, 0>;
1065def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1066 int_arm_neon_vpaddi, 0>;
1067def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1068 int_arm_neon_vpaddf, 0>;
1069
1070// VPADDL : Vector Pairwise Add Long
1071defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1072 int_arm_neon_vpaddls>;
1073defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1074 int_arm_neon_vpaddlu>;
1075
1076// VPADAL : Vector Pairwise Add and Accumulate Long
1077defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1078 int_arm_neon_vpadals>;
1079defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1080 int_arm_neon_vpadalu>;
1081
1082// VPMAX : Vector Pairwise Maximum
1083def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1084 int_arm_neon_vpmaxs, 0>;
1085def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1086 int_arm_neon_vpmaxs, 0>;
1087def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1088 int_arm_neon_vpmaxs, 0>;
1089def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1090 int_arm_neon_vpmaxu, 0>;
1091def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1092 int_arm_neon_vpmaxu, 0>;
1093def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1094 int_arm_neon_vpmaxu, 0>;
1095def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1096 int_arm_neon_vpmaxf, 0>;
1097
1098// VPMIN : Vector Pairwise Minimum
1099def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1100 int_arm_neon_vpmins, 0>;
1101def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1102 int_arm_neon_vpmins, 0>;
1103def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1104 int_arm_neon_vpmins, 0>;
1105def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1106 int_arm_neon_vpminu, 0>;
1107def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1108 int_arm_neon_vpminu, 0>;
1109def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1110 int_arm_neon_vpminu, 0>;
1111def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1112 int_arm_neon_vpminf, 0>;
1113
1114// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1115
1116// VRECPE : Vector Reciprocal Estimate
1117def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1118 v2i32, v2i32, int_arm_neon_vrecpe>;
1119def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1120 v4i32, v4i32, int_arm_neon_vrecpe>;
1121def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1122 v2f32, v2f32, int_arm_neon_vrecpef>;
1123def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1124 v4f32, v4f32, int_arm_neon_vrecpef>;
1125
1126// VRECPS : Vector Reciprocal Step
1127def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1128 int_arm_neon_vrecps, 1>;
1129def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1130 int_arm_neon_vrecps, 1>;
1131
1132// VRSQRTE : Vector Reciprocal Square Root Estimate
1133def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1134 v2i32, v2i32, int_arm_neon_vrsqrte>;
1135def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1136 v4i32, v4i32, int_arm_neon_vrsqrte>;
1137def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1138 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1139def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1140 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1141
1142// VRSQRTS : Vector Reciprocal Square Root Step
1143def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1144 int_arm_neon_vrsqrts, 1>;
1145def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1146 int_arm_neon_vrsqrts, 1>;
1147
1148// Vector Shifts.
1149
1150// VSHL : Vector Shift
1151defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1152defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1153// VSHL : Vector Shift Left (Immediate)
1154defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1155// VSHR : Vector Shift Right (Immediate)
1156defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1157defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1158
1159// VSHLL : Vector Shift Left Long
1160def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1161 v8i16, v8i8, NEONvshlls>;
1162def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1163 v4i32, v4i16, NEONvshlls>;
1164def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1165 v2i64, v2i32, NEONvshlls>;
1166def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1167 v8i16, v8i8, NEONvshllu>;
1168def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1169 v4i32, v4i16, NEONvshllu>;
1170def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1171 v2i64, v2i32, NEONvshllu>;
1172
1173// VSHLL : Vector Shift Left Long (with maximum shift count)
1174def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1175 v8i16, v8i8, NEONvshlli>;
1176def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1177 v4i32, v4i16, NEONvshlli>;
1178def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1179 v2i64, v2i32, NEONvshlli>;
1180
1181// VSHRN : Vector Shift Right and Narrow
1182def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1183 v8i8, v8i16, NEONvshrn>;
1184def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1185 v4i16, v4i32, NEONvshrn>;
1186def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1187 v2i32, v2i64, NEONvshrn>;
1188
1189// VRSHL : Vector Rounding Shift
1190defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1191defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1192// VRSHR : Vector Rounding Shift Right
1193defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1194defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1195
1196// VRSHRN : Vector Rounding Shift Right and Narrow
1197def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1198 v8i8, v8i16, NEONvrshrn>;
1199def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1200 v4i16, v4i32, NEONvrshrn>;
1201def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1202 v2i32, v2i64, NEONvrshrn>;
1203
1204// VQSHL : Vector Saturating Shift
1205defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1206defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1207// VQSHL : Vector Saturating Shift Left (Immediate)
1208defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1209defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1210// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1211defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1212
1213// VQSHRN : Vector Saturating Shift Right and Narrow
1214def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1215 v8i8, v8i16, NEONvqshrns>;
1216def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1217 v4i16, v4i32, NEONvqshrns>;
1218def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1219 v2i32, v2i64, NEONvqshrns>;
1220def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1221 v8i8, v8i16, NEONvqshrnu>;
1222def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1223 v4i16, v4i32, NEONvqshrnu>;
1224def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1225 v2i32, v2i64, NEONvqshrnu>;
1226
1227// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1228def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1229 v8i8, v8i16, NEONvqshrnsu>;
1230def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1231 v4i16, v4i32, NEONvqshrnsu>;
1232def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1233 v2i32, v2i64, NEONvqshrnsu>;
1234
1235// VQRSHL : Vector Saturating Rounding Shift
1236defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1237 int_arm_neon_vqrshifts, 0>;
1238defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1239 int_arm_neon_vqrshiftu, 0>;
1240
1241// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1242def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1243 v8i8, v8i16, NEONvqrshrns>;
1244def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1245 v4i16, v4i32, NEONvqrshrns>;
1246def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1247 v2i32, v2i64, NEONvqrshrns>;
1248def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1249 v8i8, v8i16, NEONvqrshrnu>;
1250def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1251 v4i16, v4i32, NEONvqrshrnu>;
1252def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1253 v2i32, v2i64, NEONvqrshrnu>;
1254
1255// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1256def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1257 v8i8, v8i16, NEONvqrshrnsu>;
1258def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1259 v4i16, v4i32, NEONvqrshrnsu>;
1260def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1261 v2i32, v2i64, NEONvqrshrnsu>;
1262
1263// VSRA : Vector Shift Right and Accumulate
1264defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1265defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1266// VRSRA : Vector Rounding Shift Right and Accumulate
1267defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1268defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1269
1270// VSLI : Vector Shift Left and Insert
1271defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1272// VSRI : Vector Shift Right and Insert
1273defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1274
1275// Vector Absolute and Saturating Absolute.
1276
1277// VABS : Vector Absolute Value
1278defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1279 int_arm_neon_vabs>;
1280def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1281 v2f32, v2f32, int_arm_neon_vabsf>;
1282def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1283 v4f32, v4f32, int_arm_neon_vabsf>;
1284
1285// VQABS : Vector Saturating Absolute Value
1286defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1287 int_arm_neon_vqabs>;
1288
1289// Vector Negate.
1290
1291def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1292def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1293
1294class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1295 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1296 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1297 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1298class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1299 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1300 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1301 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1302
1303// VNEG : Vector Negate
1304def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1305def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1306def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1307def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1308def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1309def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1310
1311// VNEG : Vector Negate (floating-point)
1312def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1313 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1314 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1315def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1316 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1317 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1318
1319def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1320def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1321def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1322def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1323def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1324def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1325
1326// VQNEG : Vector Saturating Negate
1327defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1328 int_arm_neon_vqneg>;
1329
1330// Vector Bit Counting Operations.
1331
1332// VCLS : Vector Count Leading Sign Bits
1333defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1334 int_arm_neon_vcls>;
1335// VCLZ : Vector Count Leading Zeros
1336defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1337 int_arm_neon_vclz>;
1338// VCNT : Vector Count One Bits
1339def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1340 v8i8, v8i8, int_arm_neon_vcnt>;
1341def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1342 v16i8, v16i8, int_arm_neon_vcnt>;
1343
1344// Vector Move Operations.
1345
1346// VMOV : Vector Move (Register)
1347
1348def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1349 "vmov\t$dst, $src", "", []>;
1350def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1351 "vmov\t$dst, $src", "", []>;
1352
1353// VMOV : Vector Move (Immediate)
1354
1355// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1356def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1357 return ARM::getVMOVImm(N, 1, *CurDAG);
1358}]>;
1359def vmovImm8 : PatLeaf<(build_vector), [{
1360 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1361}], VMOV_get_imm8>;
1362
1363// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1364def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1365 return ARM::getVMOVImm(N, 2, *CurDAG);
1366}]>;
1367def vmovImm16 : PatLeaf<(build_vector), [{
1368 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1369}], VMOV_get_imm16>;
1370
1371// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1372def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1373 return ARM::getVMOVImm(N, 4, *CurDAG);
1374}]>;
1375def vmovImm32 : PatLeaf<(build_vector), [{
1376 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1377}], VMOV_get_imm32>;
1378
1379// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1380def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1381 return ARM::getVMOVImm(N, 8, *CurDAG);
1382}]>;
1383def vmovImm64 : PatLeaf<(build_vector), [{
1384 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1385}], VMOV_get_imm64>;
1386
1387// Note: Some of the cmode bits in the following VMOV instructions need to
1388// be encoded based on the immed values.
1389
1390def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1391 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1392 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1393def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1394 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1395 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1396
1397def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1398 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1399 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1400def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1401 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1402 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1403
1404def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1405 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1406 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1407def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1408 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1409 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1410
1411def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1412 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1413 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1414def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1415 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1416 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1417
1418// VMOV : Vector Get Lane (move scalar to ARM core register)
1419
1420def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1421 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1422 "vmov", ".s8\t$dst, $src[$lane]",
1423 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1424 imm:$lane))]>;
1425def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1426 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1427 "vmov", ".s16\t$dst, $src[$lane]",
1428 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1429 imm:$lane))]>;
1430def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1431 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1432 "vmov", ".u8\t$dst, $src[$lane]",
1433 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1434 imm:$lane))]>;
1435def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1436 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1437 "vmov", ".u16\t$dst, $src[$lane]",
1438 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1439 imm:$lane))]>;
1440def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1441 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1442 "vmov", ".32\t$dst, $src[$lane]",
1443 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1444 imm:$lane))]>;
1445// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1446def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1447 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1448 (SubReg_i8_reg imm:$lane))),
1449 (SubReg_i8_lane imm:$lane))>;
1450def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1451 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1452 (SubReg_i16_reg imm:$lane))),
1453 (SubReg_i16_lane imm:$lane))>;
1454def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1455 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1456 (SubReg_i8_reg imm:$lane))),
1457 (SubReg_i8_lane imm:$lane))>;
1458def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1459 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1460 (SubReg_i16_reg imm:$lane))),
1461 (SubReg_i16_lane imm:$lane))>;
1462def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1463 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1464 (SubReg_i32_reg imm:$lane))),
1465 (SubReg_i32_lane imm:$lane))>;
1466//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1467// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1468def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1469 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1470
1471
1472// VMOV : Vector Set Lane (move ARM core register to scalar)
1473
1474let Constraints = "$src1 = $dst" in {
1475def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1476 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1477 "vmov", ".8\t$dst[$lane], $src2",
1478 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1479 GPR:$src2, imm:$lane))]>;
1480def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1481 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1482 "vmov", ".16\t$dst[$lane], $src2",
1483 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1484 GPR:$src2, imm:$lane))]>;
1485def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1486 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1487 "vmov", ".32\t$dst[$lane], $src2",
1488 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1489 GPR:$src2, imm:$lane))]>;
1490}
1491def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1492 (v16i8 (INSERT_SUBREG QPR:$src1,
1493 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1494 (SubReg_i8_reg imm:$lane))),
1495 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1496 (SubReg_i8_reg imm:$lane)))>;
1497def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1498 (v8i16 (INSERT_SUBREG QPR:$src1,
1499 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1500 (SubReg_i16_reg imm:$lane))),
1501 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1502 (SubReg_i16_reg imm:$lane)))>;
1503def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1504 (v4i32 (INSERT_SUBREG QPR:$src1,
1505 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1506 (SubReg_i32_reg imm:$lane))),
1507 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1508 (SubReg_i32_reg imm:$lane)))>;
1509
1510//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1511// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1512def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1513 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1514
1515// VDUP : Vector Duplicate (from ARM core register to all elements)
1516
1517def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1518 (vector_shuffle node:$lhs, node:$rhs), [{
1519 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1520 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1521}]>;
1522
1523class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1524 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1525 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1526 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1527class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1528 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1529 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1530 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1531
1532def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1533def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1534def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1535def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1536def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1537def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1538
1539def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1540 "vdup", ".32\t$dst, $src",
1541 [(set DPR:$dst, (v2f32 (splat_lo
1542 (scalar_to_vector
1543 (f32 (bitconvert GPR:$src))),
1544 undef)))]>;
1545def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1546 "vdup", ".32\t$dst, $src",
1547 [(set QPR:$dst, (v4f32 (splat_lo
1548 (scalar_to_vector
1549 (f32 (bitconvert GPR:$src))),
1550 undef)))]>;
1551
1552// VDUP : Vector Duplicate Lane (from scalar to all elements)
1553
1554def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1555 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1556 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1557}]>;
1558
1559def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1560 (vector_shuffle node:$lhs, node:$rhs), [{
1561 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1562 return SVOp->isSplat();
1563}], SHUFFLE_get_splat_lane>;
1564
1565class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1566 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1567 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1568 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1569 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1570
1571// vector_shuffle requires that the source and destination types match, so
1572// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1573class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1574 ValueType ResTy, ValueType OpTy>
1575 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1576 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1577 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1578 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1579
1580def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1581def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1582def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1583def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1584def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1585def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1586def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1587def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1588
1589// VMOVN : Vector Narrowing Move
1590defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1591 int_arm_neon_vmovn>;
1592// VQMOVN : Vector Saturating Narrowing Move
1593defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1594 int_arm_neon_vqmovns>;
1595defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1596 int_arm_neon_vqmovnu>;
1597defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1598 int_arm_neon_vqmovnsu>;
1599// VMOVL : Vector Lengthening Move
1600defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1601defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1602
1603// Vector Conversions.
1604
1605// VCVT : Vector Convert Between Floating-Point and Integers
1606def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1607 v2i32, v2f32, fp_to_sint>;
1608def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1609 v2i32, v2f32, fp_to_uint>;
1610def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1611 v2f32, v2i32, sint_to_fp>;
1612def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1613 v2f32, v2i32, uint_to_fp>;
1614
1615def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1616 v4i32, v4f32, fp_to_sint>;
1617def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1618 v4i32, v4f32, fp_to_uint>;
1619def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1620 v4f32, v4i32, sint_to_fp>;
1621def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1622 v4f32, v4i32, uint_to_fp>;
1623
1624// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1625// Note: Some of the opcode bits in the following VCVT instructions need to
1626// be encoded based on the immed values.
1627def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1628 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1629def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1630 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1631def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1632 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1633def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1634 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1635
1636def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1637 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1638def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1639 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1640def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1641 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1642def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1643 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1644
1645//===----------------------------------------------------------------------===//
1646// Non-Instruction Patterns
1647//===----------------------------------------------------------------------===//
1648
1649// bit_convert
1650def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1651def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1652def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1653def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1654def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1655def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1656def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1657def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1658def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1659def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1660def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1661def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1662def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1663def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1664def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1665def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1666def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1667def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1668def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1669def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1670def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1671def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1672def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1673def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1674def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1675def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1676def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1677def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1678def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1679def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1680
1681def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1682def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1683def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1684def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1685def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1686def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1687def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1688def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1689def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1690def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1691def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1692def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1693def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1694def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1695def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1696def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1697def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1698def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1699def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1700def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1701def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1702def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1703def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1704def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1705def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1706def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1707def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1708def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1709def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1710def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;