Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 081ce94 | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements a virtual register map. This maps virtual registers to |
| 11 | // physical registers and virtual registers to stack slots. It is created and |
| 12 | // updated by a register allocator and then used by a machine code rewriter that |
| 13 | // adds spill code and rewrites virtual into physical register references. |
| 14 | // |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| 17 | #ifndef LLVM_CODEGEN_VIRTREGMAP_H |
| 18 | #define LLVM_CODEGEN_VIRTREGMAP_H |
| 19 | |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 20 | #include "llvm/CodeGen/MachineFunctionPass.h" |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetRegisterInfo.h" |
Evan Cheng | 7b88cbc | 2008-04-11 17:53:36 +0000 | [diff] [blame] | 22 | #include "llvm/ADT/BitVector.h" |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 23 | #include "llvm/ADT/IndexedMap.h" |
Evan Cheng | da87253 | 2008-02-27 03:04:06 +0000 | [diff] [blame] | 24 | #include "llvm/ADT/SmallPtrSet.h" |
Dan Gohman | c24a3f8 | 2009-01-05 17:59:02 +0000 | [diff] [blame] | 25 | #include "llvm/ADT/SmallVector.h" |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 26 | #include "llvm/Support/Streams.h" |
| 27 | #include <map> |
| 28 | |
| 29 | namespace llvm { |
| 30 | class MachineInstr; |
David Greene | 44a3bfb | 2007-08-07 16:34:05 +0000 | [diff] [blame] | 31 | class MachineFunction; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 32 | class TargetInstrInfo; |
| 33 | |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 34 | class VirtRegMap : public MachineFunctionPass { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 35 | public: |
| 36 | enum { |
| 37 | NO_PHYS_REG = 0, |
| 38 | NO_STACK_SLOT = (1L << 30)-1, |
| 39 | MAX_STACK_SLOT = (1L << 18)-1 |
| 40 | }; |
| 41 | |
| 42 | enum ModRef { isRef = 1, isMod = 2, isModRef = 3 }; |
| 43 | typedef std::multimap<MachineInstr*, |
| 44 | std::pair<unsigned, ModRef> > MI2VirtMapTy; |
| 45 | |
| 46 | private: |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 47 | const TargetInstrInfo *TII; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 48 | |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 49 | MachineFunction *MF; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 50 | /// Virt2PhysMap - This is a virtual to physical register |
| 51 | /// mapping. Each virtual register is required to have an entry in |
| 52 | /// it; even spilled virtual registers (the register mapped to a |
| 53 | /// spilled register is the temporary used to load it from the |
| 54 | /// stack). |
| 55 | IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap; |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 56 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 57 | /// Virt2StackSlotMap - This is virtual register to stack slot |
| 58 | /// mapping. Each spilled virtual register has an entry in it |
| 59 | /// which corresponds to the stack slot this register is spilled |
| 60 | /// at. |
| 61 | IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap; |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 62 | |
Dan Gohman | 7d45f4d | 2008-03-12 20:50:04 +0000 | [diff] [blame] | 63 | /// Virt2ReMatIdMap - This is virtual register to rematerialization id |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 64 | /// mapping. Each spilled virtual register that should be remat'd has an |
| 65 | /// entry in it which corresponds to the remat id. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 66 | IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap; |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 67 | |
| 68 | /// Virt2SplitMap - This is virtual register to splitted virtual register |
| 69 | /// mapping. |
| 70 | IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap; |
| 71 | |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 72 | /// Virt2SplitKillMap - This is splitted virtual register to its last use |
Evan Cheng | d973104 | 2007-12-05 10:24:35 +0000 | [diff] [blame] | 73 | /// (kill) index mapping. |
| 74 | IndexedMap<unsigned> Virt2SplitKillMap; |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 75 | |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 76 | /// ReMatMap - This is virtual register to re-materialized instruction |
| 77 | /// mapping. Each virtual register whose definition is going to be |
| 78 | /// re-materialized has an entry in it. |
| 79 | IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap; |
| 80 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 81 | /// MI2VirtMap - This is MachineInstr to virtual register |
| 82 | /// mapping. In the case of memory spill code being folded into |
| 83 | /// instructions, we need to know which virtual register was |
| 84 | /// read/written by this instruction. |
| 85 | MI2VirtMapTy MI2VirtMap; |
| 86 | |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 87 | /// SpillPt2VirtMap - This records the virtual registers which should |
| 88 | /// be spilled right after the MachineInstr due to live interval |
| 89 | /// splitting. |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 90 | std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > > |
| 91 | SpillPt2VirtMap; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 92 | |
Evan Cheng | 96c6131 | 2007-11-29 01:06:25 +0000 | [diff] [blame] | 93 | /// RestorePt2VirtMap - This records the virtual registers which should |
| 94 | /// be restored right before the MachineInstr due to live interval |
| 95 | /// splitting. |
| 96 | std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap; |
| 97 | |
Evan Cheng | 14cc83f | 2008-03-11 07:19:34 +0000 | [diff] [blame] | 98 | /// EmergencySpillMap - This records the physical registers that should |
| 99 | /// be spilled / restored around the MachineInstr since the register |
| 100 | /// allocator has run out of registers. |
| 101 | std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap; |
| 102 | |
| 103 | /// EmergencySpillSlots - This records emergency spill slots used to |
| 104 | /// spill physical registers when the register allocator runs out of |
| 105 | /// registers. Ideally only one stack slot is used per function per |
| 106 | /// register class. |
| 107 | std::map<const TargetRegisterClass*, int> EmergencySpillSlots; |
| 108 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 109 | /// ReMatId - Instead of assigning a stack slot to a to be rematerialized |
| 110 | /// virtual register, an unique id is being assigned. This keeps track of |
| 111 | /// the highest id used so far. Note, this starts at (1<<18) to avoid |
| 112 | /// conflicts with stack slot numbers. |
| 113 | int ReMatId; |
| 114 | |
Evan Cheng | da87253 | 2008-02-27 03:04:06 +0000 | [diff] [blame] | 115 | /// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes. |
| 116 | int LowSpillSlot, HighSpillSlot; |
| 117 | |
| 118 | /// SpillSlotToUsesMap - Records uses for each register spill slot. |
| 119 | SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap; |
| 120 | |
Evan Cheng | 7b88cbc | 2008-04-11 17:53:36 +0000 | [diff] [blame] | 121 | /// ImplicitDefed - One bit for each virtual register. If set it indicates |
| 122 | /// the register is implicitly defined. |
| 123 | BitVector ImplicitDefed; |
| 124 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 125 | VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT |
| 126 | void operator=(const VirtRegMap&); // DO NOT IMPLEMENT |
| 127 | |
| 128 | public: |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 129 | static char ID; |
| 130 | VirtRegMap() : MachineFunctionPass(&ID), Virt2PhysMap(NO_PHYS_REG), |
| 131 | Virt2StackSlotMap(NO_STACK_SLOT), |
| 132 | Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), |
| 133 | Virt2SplitKillMap(0), ReMatMap(NULL), |
| 134 | ReMatId(MAX_STACK_SLOT+1), |
| 135 | LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { } |
| 136 | virtual bool runOnMachineFunction(MachineFunction &MF); |
| 137 | |
| 138 | virtual void getAnalysisUsage(AnalysisUsage &AU) const { |
| 139 | AU.setPreservesAll(); |
| 140 | MachineFunctionPass::getAnalysisUsage(AU); |
| 141 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 142 | |
| 143 | void grow(); |
| 144 | |
| 145 | /// @brief returns true if the specified virtual register is |
| 146 | /// mapped to a physical register |
| 147 | bool hasPhys(unsigned virtReg) const { |
| 148 | return getPhys(virtReg) != NO_PHYS_REG; |
| 149 | } |
| 150 | |
| 151 | /// @brief returns the physical register mapped to the specified |
| 152 | /// virtual register |
| 153 | unsigned getPhys(unsigned virtReg) const { |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 154 | assert(TargetRegisterInfo::isVirtualRegister(virtReg)); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 155 | return Virt2PhysMap[virtReg]; |
| 156 | } |
| 157 | |
| 158 | /// @brief creates a mapping for the specified virtual register to |
| 159 | /// the specified physical register |
| 160 | void assignVirt2Phys(unsigned virtReg, unsigned physReg) { |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 161 | assert(TargetRegisterInfo::isVirtualRegister(virtReg) && |
| 162 | TargetRegisterInfo::isPhysicalRegister(physReg)); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 163 | assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && |
| 164 | "attempt to assign physical register to already mapped " |
| 165 | "virtual register"); |
| 166 | Virt2PhysMap[virtReg] = physReg; |
| 167 | } |
| 168 | |
| 169 | /// @brief clears the specified virtual register's, physical |
| 170 | /// register mapping |
| 171 | void clearVirt(unsigned virtReg) { |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 172 | assert(TargetRegisterInfo::isVirtualRegister(virtReg)); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 173 | assert(Virt2PhysMap[virtReg] != NO_PHYS_REG && |
| 174 | "attempt to clear a not assigned virtual register"); |
| 175 | Virt2PhysMap[virtReg] = NO_PHYS_REG; |
| 176 | } |
| 177 | |
| 178 | /// @brief clears all virtual to physical register mappings |
| 179 | void clearAllVirt() { |
| 180 | Virt2PhysMap.clear(); |
| 181 | grow(); |
| 182 | } |
| 183 | |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 184 | /// @brief records virtReg is a split live interval from SReg. |
| 185 | void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { |
| 186 | Virt2SplitMap[virtReg] = SReg; |
| 187 | } |
| 188 | |
| 189 | /// @brief returns the live interval virtReg is split from. |
| 190 | unsigned getPreSplitReg(unsigned virtReg) { |
| 191 | return Virt2SplitMap[virtReg]; |
| 192 | } |
| 193 | |
Dan Gohman | 7d45f4d | 2008-03-12 20:50:04 +0000 | [diff] [blame] | 194 | /// @brief returns true if the specified virtual register is not |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 195 | /// mapped to a stack slot or rematerialized. |
| 196 | bool isAssignedReg(unsigned virtReg) const { |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 197 | if (getStackSlot(virtReg) == NO_STACK_SLOT && |
| 198 | getReMatId(virtReg) == NO_STACK_SLOT) |
| 199 | return true; |
| 200 | // Split register can be assigned a physical register as well as a |
| 201 | // stack slot or remat id. |
| 202 | return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | /// @brief returns the stack slot mapped to the specified virtual |
| 206 | /// register |
| 207 | int getStackSlot(unsigned virtReg) const { |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 208 | assert(TargetRegisterInfo::isVirtualRegister(virtReg)); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 209 | return Virt2StackSlotMap[virtReg]; |
| 210 | } |
| 211 | |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 212 | /// @brief returns the rematerialization id mapped to the specified virtual |
| 213 | /// register |
| 214 | int getReMatId(unsigned virtReg) const { |
Dan Gohman | 1e57df3 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 215 | assert(TargetRegisterInfo::isVirtualRegister(virtReg)); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 216 | return Virt2ReMatIdMap[virtReg]; |
| 217 | } |
| 218 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 219 | /// @brief create a mapping for the specifed virtual register to |
| 220 | /// the next available stack slot |
| 221 | int assignVirt2StackSlot(unsigned virtReg); |
| 222 | /// @brief create a mapping for the specified virtual register to |
| 223 | /// the specified stack slot |
| 224 | void assignVirt2StackSlot(unsigned virtReg, int frameIndex); |
| 225 | |
| 226 | /// @brief assign an unique re-materialization id to the specified |
| 227 | /// virtual register. |
| 228 | int assignVirtReMatId(unsigned virtReg); |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 229 | /// @brief assign an unique re-materialization id to the specified |
| 230 | /// virtual register. |
| 231 | void assignVirtReMatId(unsigned virtReg, int id); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 232 | |
| 233 | /// @brief returns true if the specified virtual register is being |
| 234 | /// re-materialized. |
| 235 | bool isReMaterialized(unsigned virtReg) const { |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 236 | return ReMatMap[virtReg] != NULL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | /// @brief returns the original machine instruction being re-issued |
| 240 | /// to re-materialize the specified virtual register. |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 241 | MachineInstr *getReMaterializedMI(unsigned virtReg) const { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 242 | return ReMatMap[virtReg]; |
| 243 | } |
| 244 | |
| 245 | /// @brief records the specified virtual register will be |
| 246 | /// re-materialized and the original instruction which will be re-issed |
Evan Cheng | 1204d17 | 2007-08-13 23:45:17 +0000 | [diff] [blame] | 247 | /// for this purpose. If parameter all is true, then all uses of the |
| 248 | /// registers are rematerialized and it's safe to delete the definition. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 249 | void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) { |
| 250 | ReMatMap[virtReg] = def; |
| 251 | } |
| 252 | |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 253 | /// @brief record the last use (kill) of a split virtual register. |
Evan Cheng | d973104 | 2007-12-05 10:24:35 +0000 | [diff] [blame] | 254 | void addKillPoint(unsigned virtReg, unsigned index) { |
| 255 | Virt2SplitKillMap[virtReg] = index; |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 256 | } |
| 257 | |
Evan Cheng | d973104 | 2007-12-05 10:24:35 +0000 | [diff] [blame] | 258 | unsigned getKillPoint(unsigned virtReg) const { |
| 259 | return Virt2SplitKillMap[virtReg]; |
| 260 | } |
| 261 | |
| 262 | /// @brief remove the last use (kill) of a split virtual register. |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 263 | void removeKillPoint(unsigned virtReg) { |
Evan Cheng | d973104 | 2007-12-05 10:24:35 +0000 | [diff] [blame] | 264 | Virt2SplitKillMap[virtReg] = 0; |
Evan Cheng | 6f52267 | 2007-12-05 09:51:10 +0000 | [diff] [blame] | 265 | } |
| 266 | |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 267 | /// @brief returns true if the specified MachineInstr is a spill point. |
| 268 | bool isSpillPt(MachineInstr *Pt) const { |
| 269 | return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end(); |
| 270 | } |
| 271 | |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 272 | /// @brief returns the virtual registers that should be spilled due to |
| 273 | /// splitting right after the specified MachineInstr. |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 274 | std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) { |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 275 | return SpillPt2VirtMap[Pt]; |
| 276 | } |
| 277 | |
| 278 | /// @brief records the specified MachineInstr as a spill point for virtReg. |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 279 | void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) { |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 280 | if (SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end()) |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 281 | SpillPt2VirtMap[Pt].push_back(std::make_pair(virtReg, isKill)); |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 282 | else { |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 283 | std::vector<std::pair<unsigned,bool> > Virts; |
| 284 | Virts.push_back(std::make_pair(virtReg, isKill)); |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 285 | SpillPt2VirtMap.insert(std::make_pair(Pt, Virts)); |
| 286 | } |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 287 | } |
| 288 | |
Evan Cheng | 1eeb2ef | 2008-03-11 21:34:46 +0000 | [diff] [blame] | 289 | /// @brief - transfer spill point information from one instruction to |
| 290 | /// another. |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 291 | void transferSpillPts(MachineInstr *Old, MachineInstr *New) { |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 292 | std::map<MachineInstr*,std::vector<std::pair<unsigned,bool> > >::iterator |
| 293 | I = SpillPt2VirtMap.find(Old); |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 294 | if (I == SpillPt2VirtMap.end()) |
| 295 | return; |
| 296 | while (!I->second.empty()) { |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 297 | unsigned virtReg = I->second.back().first; |
| 298 | bool isKill = I->second.back().second; |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 299 | I->second.pop_back(); |
Evan Cheng | ed17a89 | 2007-12-05 08:16:32 +0000 | [diff] [blame] | 300 | addSpillPoint(virtReg, isKill, New); |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 301 | } |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 302 | SpillPt2VirtMap.erase(I); |
Evan Cheng | cecc822 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 303 | } |
| 304 | |
Evan Cheng | 96c6131 | 2007-11-29 01:06:25 +0000 | [diff] [blame] | 305 | /// @brief returns true if the specified MachineInstr is a restore point. |
| 306 | bool isRestorePt(MachineInstr *Pt) const { |
| 307 | return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end(); |
| 308 | } |
| 309 | |
| 310 | /// @brief returns the virtual registers that should be restoreed due to |
| 311 | /// splitting right after the specified MachineInstr. |
| 312 | std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) { |
| 313 | return RestorePt2VirtMap[Pt]; |
| 314 | } |
| 315 | |
| 316 | /// @brief records the specified MachineInstr as a restore point for virtReg. |
| 317 | void addRestorePoint(unsigned virtReg, MachineInstr *Pt) { |
| 318 | if (RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end()) |
| 319 | RestorePt2VirtMap[Pt].push_back(virtReg); |
| 320 | else { |
| 321 | std::vector<unsigned> Virts; |
| 322 | Virts.push_back(virtReg); |
| 323 | RestorePt2VirtMap.insert(std::make_pair(Pt, Virts)); |
| 324 | } |
| 325 | } |
| 326 | |
Evan Cheng | 14cc83f | 2008-03-11 07:19:34 +0000 | [diff] [blame] | 327 | /// @brief - transfer restore point information from one instruction to |
| 328 | /// another. |
Evan Cheng | 96c6131 | 2007-11-29 01:06:25 +0000 | [diff] [blame] | 329 | void transferRestorePts(MachineInstr *Old, MachineInstr *New) { |
| 330 | std::map<MachineInstr*,std::vector<unsigned> >::iterator I = |
| 331 | RestorePt2VirtMap.find(Old); |
| 332 | if (I == RestorePt2VirtMap.end()) |
| 333 | return; |
| 334 | while (!I->second.empty()) { |
| 335 | unsigned virtReg = I->second.back(); |
| 336 | I->second.pop_back(); |
| 337 | addRestorePoint(virtReg, New); |
| 338 | } |
| 339 | RestorePt2VirtMap.erase(I); |
| 340 | } |
| 341 | |
Evan Cheng | 14cc83f | 2008-03-11 07:19:34 +0000 | [diff] [blame] | 342 | /// @brief records that the specified physical register must be spilled |
| 343 | /// around the specified machine instr. |
| 344 | void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) { |
| 345 | if (EmergencySpillMap.find(MI) != EmergencySpillMap.end()) |
| 346 | EmergencySpillMap[MI].push_back(PhysReg); |
| 347 | else { |
| 348 | std::vector<unsigned> PhysRegs; |
| 349 | PhysRegs.push_back(PhysReg); |
| 350 | EmergencySpillMap.insert(std::make_pair(MI, PhysRegs)); |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | /// @brief returns true if one or more physical registers must be spilled |
| 355 | /// around the specified instruction. |
| 356 | bool hasEmergencySpills(MachineInstr *MI) const { |
| 357 | return EmergencySpillMap.find(MI) != EmergencySpillMap.end(); |
| 358 | } |
| 359 | |
| 360 | /// @brief returns the physical registers to be spilled and restored around |
| 361 | /// the instruction. |
| 362 | std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) { |
| 363 | return EmergencySpillMap[MI]; |
| 364 | } |
| 365 | |
Evan Cheng | 1eeb2ef | 2008-03-11 21:34:46 +0000 | [diff] [blame] | 366 | /// @brief - transfer emergency spill information from one instruction to |
| 367 | /// another. |
| 368 | void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) { |
| 369 | std::map<MachineInstr*,std::vector<unsigned> >::iterator I = |
| 370 | EmergencySpillMap.find(Old); |
| 371 | if (I == EmergencySpillMap.end()) |
| 372 | return; |
| 373 | while (!I->second.empty()) { |
| 374 | unsigned virtReg = I->second.back(); |
| 375 | I->second.pop_back(); |
| 376 | addEmergencySpill(virtReg, New); |
| 377 | } |
| 378 | EmergencySpillMap.erase(I); |
| 379 | } |
| 380 | |
Evan Cheng | 14cc83f | 2008-03-11 07:19:34 +0000 | [diff] [blame] | 381 | /// @brief return or get a emergency spill slot for the register class. |
| 382 | int getEmergencySpillSlot(const TargetRegisterClass *RC); |
| 383 | |
Evan Cheng | da87253 | 2008-02-27 03:04:06 +0000 | [diff] [blame] | 384 | /// @brief Return lowest spill slot index. |
| 385 | int getLowSpillSlot() const { |
| 386 | return LowSpillSlot; |
| 387 | } |
| 388 | |
| 389 | /// @brief Return highest spill slot index. |
| 390 | int getHighSpillSlot() const { |
| 391 | return HighSpillSlot; |
| 392 | } |
| 393 | |
| 394 | /// @brief Records a spill slot use. |
| 395 | void addSpillSlotUse(int FrameIndex, MachineInstr *MI); |
| 396 | |
| 397 | /// @brief Returns true if spill slot has been used. |
| 398 | bool isSpillSlotUsed(int FrameIndex) const { |
| 399 | assert(FrameIndex >= 0 && "Spill slot index should not be negative!"); |
| 400 | return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty(); |
| 401 | } |
| 402 | |
Evan Cheng | 7b88cbc | 2008-04-11 17:53:36 +0000 | [diff] [blame] | 403 | /// @brief Mark the specified register as being implicitly defined. |
| 404 | void setIsImplicitlyDefined(unsigned VirtReg) { |
| 405 | ImplicitDefed.set(VirtReg-TargetRegisterInfo::FirstVirtualRegister); |
| 406 | } |
| 407 | |
| 408 | /// @brief Returns true if the virtual register is implicitly defined. |
| 409 | bool isImplicitlyDefined(unsigned VirtReg) const { |
| 410 | return ImplicitDefed[VirtReg-TargetRegisterInfo::FirstVirtualRegister]; |
| 411 | } |
| 412 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 413 | /// @brief Updates information about the specified virtual register's value |
Evan Cheng | fd0bd3c | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 414 | /// folded into newMI machine instruction. |
| 415 | void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI, |
| 416 | ModRef MRInfo); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 417 | |
Evan Cheng | f325584 | 2007-10-13 02:50:24 +0000 | [diff] [blame] | 418 | /// @brief Updates information about the specified virtual register's value |
| 419 | /// folded into the specified machine instruction. |
| 420 | void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo); |
| 421 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 422 | /// @brief returns the virtual registers' values folded in memory |
| 423 | /// operands of this instruction |
| 424 | std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator> |
| 425 | getFoldedVirts(MachineInstr* MI) const { |
| 426 | return MI2VirtMap.equal_range(MI); |
| 427 | } |
| 428 | |
Evan Cheng | 91e32d0 | 2007-11-28 01:28:46 +0000 | [diff] [blame] | 429 | /// RemoveMachineInstrFromMaps - MI is being erased, remove it from the |
| 430 | /// the folded instruction map and spill point map. |
Evan Cheng | da87253 | 2008-02-27 03:04:06 +0000 | [diff] [blame] | 431 | void RemoveMachineInstrFromMaps(MachineInstr *MI); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 432 | |
Owen Anderson | dd56ab7 | 2009-03-13 05:55:11 +0000 | [diff] [blame^] | 433 | void print(std::ostream &OS, const Module* M = 0) const; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 434 | void print(std::ostream *OS) const { if (OS) print(*OS); } |
| 435 | void dump() const; |
| 436 | }; |
| 437 | |
| 438 | inline std::ostream *operator<<(std::ostream *OS, const VirtRegMap &VRM) { |
| 439 | VRM.print(OS); |
| 440 | return OS; |
| 441 | } |
| 442 | inline std::ostream &operator<<(std::ostream &OS, const VirtRegMap &VRM) { |
| 443 | VRM.print(OS); |
| 444 | return OS; |
| 445 | } |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 446 | } // End llvm namespace |
| 447 | |
| 448 | #endif |