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gerrit-public.fairphone.software / platform / external / llvm / e31b42a6f5598691498808673648211916bf4d0f / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 8dab153132108317eec2f669bbe97e13a1b20547 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]252static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]278 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]279static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]293static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]294 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]295static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]305static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]306 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]307static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
309static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
310 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]311static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]313static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]315static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
316 uint64_t Address, const void *Decoder);
317
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]318
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319
320#include "ARMGenDisassemblerTables.inc"
321#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]322#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]323
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]324static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
325 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]326}
327
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]328static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
329 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]330}
331
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]332EDInstInfo *ARMDisassembler::getEDInfo() const {
333 return instInfoARM;
334}
335
336EDInstInfo *ThumbDisassembler::getEDInfo() const {
337 return instInfoARM;
338}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]340DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]341 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]342 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]343 raw_ostream &os,
344 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]345 CommentStream = &cs;
346
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint8_t bytes[4];
348
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]349 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
350 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
351
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]353 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
354 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]355 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]356 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357
358 // Encoded as a small-endian 32-bit word in the stream.
359 uint32_t insn = (bytes[3] << 24) |
360 (bytes[2] << 16) |
361 (bytes[1] << 8) |
362 (bytes[0] << 0);
363
364 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]365 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]366 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]368 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 }
370
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]371 // VFP and NEON instructions, similarly, are shared between ARM
372 // and Thumb modes.
373 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]374 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]375 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]377 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]378 }
379
380 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]381 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]382 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]383 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]384 // Add a fake predicate operand, because we share these instruction
385 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]386 if (!DecodePredicateOperand(MI, 0xE, Address, this))
387 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]388 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]389 }
390
391 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]392 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]393 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]394 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]395 // Add a fake predicate operand, because we share these instruction
396 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]397 if (!DecodePredicateOperand(MI, 0xE, Address, this))
398 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]399 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]400 }
401
402 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]403 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]404 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]405 Size = 4;
406 // Add a fake predicate operand, because we share these instruction
407 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]408 if (!DecodePredicateOperand(MI, 0xE, Address, this))
409 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]410 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]411 }
412
413 MI.clear();
414
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]415 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]416 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]417}
418
419namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]420extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421}
422
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]423/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
424/// immediate Value in the MCInst. The immediate Value has had any PC
425/// adjustment made by the caller. If the instruction is a branch instruction
426/// then isBranch is true, else false. If the getOpInfo() function was set as
427/// part of the setupForSymbolicDisassembly() call then that function is called
428/// to get any symbolic information at the Address for this instruction. If
429/// that returns non-zero then the symbolic information it returns is used to
430/// create an MCExpr and that is added as an operand to the MCInst. If
431/// getOpInfo() returns zero and isBranch is true then a symbol look up for
432/// Value is done and if a symbol is found an MCExpr is created with that, else
433/// an MCExpr with Value is created. This function returns true if it adds an
434/// operand to the MCInst and false otherwise.
435static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
436 bool isBranch, uint64_t InstSize,
437 MCInst &MI, const void *Decoder) {
438 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
439 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
440 if (!getOpInfo)
441 return false;
442
443 struct LLVMOpInfo1 SymbolicOp;
444 SymbolicOp.Value = Value;
445 void *DisInfo = Dis->getDisInfoBlock();
446 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
447 if (isBranch) {
448 LLVMSymbolLookupCallback SymbolLookUp =
449 Dis->getLLVMSymbolLookupCallback();
450 if (SymbolLookUp) {
451 uint64_t ReferenceType;
452 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
453 const char *ReferenceName;
454 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
455 &ReferenceName);
456 if (Name) {
457 SymbolicOp.AddSymbol.Name = Name;
458 SymbolicOp.AddSymbol.Present = true;
459 SymbolicOp.Value = 0;
460 }
461 else {
462 SymbolicOp.Value = Value;
463 }
464 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
465 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
466 }
467 else {
468 return false;
469 }
470 }
471 else {
472 return false;
473 }
474 }
475
476 MCContext *Ctx = Dis->getMCContext();
477 const MCExpr *Add = NULL;
478 if (SymbolicOp.AddSymbol.Present) {
479 if (SymbolicOp.AddSymbol.Name) {
480 StringRef Name(SymbolicOp.AddSymbol.Name);
481 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
482 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
483 } else {
484 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
485 }
486 }
487
488 const MCExpr *Sub = NULL;
489 if (SymbolicOp.SubtractSymbol.Present) {
490 if (SymbolicOp.SubtractSymbol.Name) {
491 StringRef Name(SymbolicOp.SubtractSymbol.Name);
492 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
493 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
494 } else {
495 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
496 }
497 }
498
499 const MCExpr *Off = NULL;
500 if (SymbolicOp.Value != 0)
501 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
502
503 const MCExpr *Expr;
504 if (Sub) {
505 const MCExpr *LHS;
506 if (Add)
507 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
508 else
509 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
510 if (Off != 0)
511 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
512 else
513 Expr = LHS;
514 } else if (Add) {
515 if (Off != 0)
516 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
517 else
518 Expr = Add;
519 } else {
520 if (Off != 0)
521 Expr = Off;
522 else
523 Expr = MCConstantExpr::Create(0, *Ctx);
524 }
525
526 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
529 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
530 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
531 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]532 else
Richard Trieu8223e452011-10-14 20:50:26 +0000[diff] [blame]533 assert(0 && "bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]534
535 return true;
536}
537
538/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
539/// referenced by a load instruction with the base register that is the Pc.
540/// These can often be values in a literal pool near the Address of the
541/// instruction. The Address of the instruction and its immediate Value are
542/// used as a possible literal pool entry. The SymbolLookUp call back will
543/// return the name of a symbol referenced by the the literal pool's entry if
544/// the referenced address is that of a symbol. Or it will return a pointer to
545/// a literal 'C' string if the referenced address of the literal pool's entry
546/// is an address into a section with 'C' string literals.
547static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
548 const void *Decoder) {
549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
550 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
551 if (SymbolLookUp) {
552 void *DisInfo = Dis->getDisInfoBlock();
553 uint64_t ReferenceType;
554 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
555 const char *ReferenceName;
556 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
557 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
558 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
559 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
560 }
561}
562
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]563// Thumb1 instructions don't have explicit S bits. Rather, they
564// implicitly set CPSR. Since it's not represented in the encoding, the
565// auto-generated decoder won't inject the CPSR operand. We need to fix
566// that as a post-pass.
567static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
568 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]570 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]571 for (unsigned i = 0; i < NumOps; ++i, ++I) {
572 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]574 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
576 return;
577 }
578 }
579
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]581}
582
583// Most Thumb instructions don't have explicit predicates in the
584// encoding, but rather get their predicates from IT context. We need
585// to fix up the predicate operands using this context information as a
586// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]587MCDisassembler::DecodeStatus
588ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]589 MCDisassembler::DecodeStatus S = Success;
590
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]591 // A few instructions actually have predicates encoded in them. Don't
592 // try to overwrite it if we're seeing one of those.
593 switch (MI.getOpcode()) {
594 case ARM::tBcc:
595 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]596 case ARM::tCBZ:
597 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]598 case ARM::tCPS:
599 case ARM::t2CPS3p:
600 case ARM::t2CPS2p:
601 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]602 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]603 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]604 // Some instructions (mostly conditional branches) are not
605 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]606 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]607 S = SoftFail;
608 else
609 return Success;
610 break;
611 case ARM::tB:
612 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]613 case ARM::t2TBB:
614 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]615 // Some instructions (mostly unconditional branches) can
616 // only appears at the end of, or outside of, an IT.
617 if (ITBlock.size() > 1)
618 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]619 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]620 default:
621 break;
622 }
623
624 // If we're in an IT block, base the predicate on that. Otherwise,
625 // assume a predicate of AL.
626 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]627 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]629 if (CC == 0xF)
630 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]631 ITBlock.pop_back();
632 } else
633 CC = ARMCC::AL;
634
635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]638 for (unsigned i = 0; i < NumOps; ++i, ++I) {
639 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]640 if (OpInfo[i].isPredicate()) {
641 I = MI.insert(I, MCOperand::CreateImm(CC));
642 ++I;
643 if (CC == ARMCC::AL)
644 MI.insert(I, MCOperand::CreateReg(0));
645 else
646 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]647 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]648 }
649 }
650
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]651 I = MI.insert(I, MCOperand::CreateImm(CC));
652 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]654 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]655 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]656 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]657
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]658 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]659}
660
661// Thumb VFP instructions are a special case. Because we share their
662// encodings between ARM and Thumb modes, and they are predicable in ARM
663// mode, the auto-generated decoder will give them an (incorrect)
664// predicate operand. We need to rewrite these operands based on the IT
665// context as a post-pass.
666void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
667 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]668 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]669 CC = ITBlock.back();
670 ITBlock.pop_back();
671 } else
672 CC = ARMCC::AL;
673
674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
675 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
677 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]678 if (OpInfo[i].isPredicate() ) {
679 I->setImm(CC);
680 ++I;
681 if (CC == ARMCC::AL)
682 I->setReg(0);
683 else
684 I->setReg(ARM::CPSR);
685 return;
686 }
687 }
688}
689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]690DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]691 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]692 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]693 raw_ostream &os,
694 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]695 CommentStream = &cs;
696
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]697 uint8_t bytes[4];
698
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]699 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
701
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]703 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
704 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]705 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]706 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707
708 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]709 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]710 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]711 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]712 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]713 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]714 }
715
716 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]717 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]718 if (result) {
719 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]720 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]721 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]723 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]724 }
725
726 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]727 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]728 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]730
731 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
732 // the Thumb predicate.
733 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
734 result = MCDisassembler::SoftFail;
735
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]736 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]737
738 // If we find an IT instruction, we need to parse its condition
739 // code and mask operands so that we can apply them correctly
740 // to the subsequent instructions.
741 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]742
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]743 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]744 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]745 unsigned Mask = MI.getOperand(1).getImm();
746 unsigned CondBit0 = Mask >> 4 & 1;
747 unsigned NumTZ = CountTrailingZeros_32(Mask);
748 assert(NumTZ <= 3 && "Invalid IT mask!");
749 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
750 bool T = ((Mask >> Pos) & 1) == CondBit0;
751 if (T)
752 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]754 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]756
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]757 ITBlock.push_back(firstcond);
758 }
759
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]760 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 }
762
763 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]764 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
765 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]766 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]767 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]768
769 uint32_t insn32 = (bytes[3] << 8) |
770 (bytes[2] << 0) |
771 (bytes[1] << 24) |
772 (bytes[0] << 16);
773 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]774 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]775 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776 Size = 4;
777 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]778 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]779 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]780 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 }
782
783 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]784 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]785 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]787 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]788 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 }
790
791 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]792 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 Size = 4;
795 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]796 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797 }
798
799 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]800 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]802 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]803 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]804 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]805 }
806
807 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
808 MI.clear();
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]812 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]815 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]816 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]817 }
818 }
819
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]820 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]821 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]822 uint32_t NEONDataInsn = insn32;
823 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
824 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
825 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]826 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]827 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]829 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]830 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]831 }
832 }
833
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]834 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]835 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836}
837
838
839extern "C" void LLVMInitializeARMDisassembler() {
840 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
841 createARMDisassembler);
842 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
843 createThumbDisassembler);
844}
845
846static const unsigned GPRDecoderTable[] = {
847 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
848 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
849 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
850 ARM::R12, ARM::SP, ARM::LR, ARM::PC
851};
852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]853static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854 uint64_t Address, const void *Decoder) {
855 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]856 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857
858 unsigned Register = GPRDecoderTable[RegNo];
859 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]861}
862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]863static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]864DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
865 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]866 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]867 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
868}
869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]870static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]871 uint64_t Address, const void *Decoder) {
872 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]873 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]874 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
875}
876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]877static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]878 uint64_t Address, const void *Decoder) {
879 unsigned Register = 0;
880 switch (RegNo) {
881 case 0:
882 Register = ARM::R0;
883 break;
884 case 1:
885 Register = ARM::R1;
886 break;
887 case 2:
888 Register = ARM::R2;
889 break;
890 case 3:
891 Register = ARM::R3;
892 break;
893 case 9:
894 Register = ARM::R9;
895 break;
896 case 12:
897 Register = ARM::R12;
898 break;
899 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]900 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 }
902
903 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]904 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]905}
906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]907static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]909 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]910 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
911}
912
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]913static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]914 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
915 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
916 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
917 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
918 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
919 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
920 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
921 ARM::S28, ARM::S29, ARM::S30, ARM::S31
922};
923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925 uint64_t Address, const void *Decoder) {
926 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]927 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]928
929 unsigned Register = SPRDecoderTable[RegNo];
930 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]931 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932}
933
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]934static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]935 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
936 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
937 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
938 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
939 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
940 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
941 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
942 ARM::D28, ARM::D29, ARM::D30, ARM::D31
943};
944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]945static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946 uint64_t Address, const void *Decoder) {
947 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]948 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]949
950 unsigned Register = DPRDecoderTable[RegNo];
951 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]952 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953}
954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]955static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 uint64_t Address, const void *Decoder) {
957 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]958 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]959 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
960}
961
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]962static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]963DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
964 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]966 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
968}
969
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]970static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]971 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
972 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
973 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
974 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
975};
976
977
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]978static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 uint64_t Address, const void *Decoder) {
980 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]981 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]982 RegNo >>= 1;
983
984 unsigned Register = QPRDecoderTable[RegNo];
985 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]986 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987}
988
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]989static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]990 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]991 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]992 // AL predicate is not allowed on Thumb1 branches.
993 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995 Inst.addOperand(MCOperand::CreateImm(Val));
996 if (Val == ARMCC::AL) {
997 Inst.addOperand(MCOperand::CreateReg(0));
998 } else
999 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1000 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001}
1002
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1003static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1004 uint64_t Address, const void *Decoder) {
1005 if (Val)
1006 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1007 else
1008 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1009 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1010}
1011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1012static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013 uint64_t Address, const void *Decoder) {
1014 uint32_t imm = Val & 0xFF;
1015 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1016 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1017 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1018 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019}
1020
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1021static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1023 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024
1025 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1026 unsigned type = fieldFromInstruction32(Val, 5, 2);
1027 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1028
1029 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1031 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032
1033 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1034 switch (type) {
1035 case 0:
1036 Shift = ARM_AM::lsl;
1037 break;
1038 case 1:
1039 Shift = ARM_AM::lsr;
1040 break;
1041 case 2:
1042 Shift = ARM_AM::asr;
1043 break;
1044 case 3:
1045 Shift = ARM_AM::ror;
1046 break;
1047 }
1048
1049 if (Shift == ARM_AM::ror && imm == 0)
1050 Shift = ARM_AM::rrx;
1051
1052 unsigned Op = Shift | (imm << 3);
1053 Inst.addOperand(MCOperand::CreateImm(Op));
1054
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1055 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056}
1057
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1058static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1060 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1061
1062 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1063 unsigned type = fieldFromInstruction32(Val, 5, 2);
1064 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1065
1066 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1068 return MCDisassembler::Fail;
1069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1070 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1071
1072 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1073 switch (type) {
1074 case 0:
1075 Shift = ARM_AM::lsl;
1076 break;
1077 case 1:
1078 Shift = ARM_AM::lsr;
1079 break;
1080 case 2:
1081 Shift = ARM_AM::asr;
1082 break;
1083 case 3:
1084 Shift = ARM_AM::ror;
1085 break;
1086 }
1087
1088 Inst.addOperand(MCOperand::CreateImm(Shift));
1089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1090 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091}
1092
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1093static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1094 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1095 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1096
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1097 bool writebackLoad = false;
1098 unsigned writebackReg = 0;
1099 switch (Inst.getOpcode()) {
1100 default:
1101 break;
1102 case ARM::LDMIA_UPD:
1103 case ARM::LDMDB_UPD:
1104 case ARM::LDMIB_UPD:
1105 case ARM::LDMDA_UPD:
1106 case ARM::t2LDMIA_UPD:
1107 case ARM::t2LDMDB_UPD:
1108 writebackLoad = true;
1109 writebackReg = Inst.getOperand(0).getReg();
1110 break;
1111 }
1112
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1113 // Empty register lists are not allowed.
Owen Andersone31b42a2011-11-02 17:41:23 +0000[diff] [blame^]1114 uint32_t popcnt = CountPopulation_32(Val);
1115 if (popcnt == 0) return MCDisassembler::Fail;
1116 // and one-register lists are unpredictable.
1117 else if (popcnt == 1) Check(S, MCDisassembler::SoftFail);
1118
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1120 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1121 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1122 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1123 // Writeback not allowed if Rn is in the target list.
1124 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1125 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1126 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127 }
1128
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1129 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1130}
1131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1133 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1134 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1135
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1136 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1137 unsigned regs = Val & 0xFF;
1138
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1139 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1140 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1141 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1142 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1143 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1144 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1145
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1146 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1147}
1148
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1149static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1150 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1151 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1152
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1153 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1154 unsigned regs = (Val & 0xFF) / 2;
1155
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1156 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1157 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1158 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1159 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1160 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1161 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1162
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1163 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1164}
1165
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1166static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1167 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1168 // This operand encodes a mask of contiguous zeros between a specified MSB
1169 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1170 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1171 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1172 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1173 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1174 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1175
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1176 DecodeStatus S = MCDisassembler::Success;
1177 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1178
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1179 uint32_t msb_mask = 0xFFFFFFFF;
1180 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1181 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1182
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1184 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1185}
1186
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1187static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1188 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1189 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1190
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1191 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1192 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1193 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1194 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1195 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1196 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1197
1198 switch (Inst.getOpcode()) {
1199 case ARM::LDC_OFFSET:
1200 case ARM::LDC_PRE:
1201 case ARM::LDC_POST:
1202 case ARM::LDC_OPTION:
1203 case ARM::LDCL_OFFSET:
1204 case ARM::LDCL_PRE:
1205 case ARM::LDCL_POST:
1206 case ARM::LDCL_OPTION:
1207 case ARM::STC_OFFSET:
1208 case ARM::STC_PRE:
1209 case ARM::STC_POST:
1210 case ARM::STC_OPTION:
1211 case ARM::STCL_OFFSET:
1212 case ARM::STCL_PRE:
1213 case ARM::STCL_POST:
1214 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1215 case ARM::t2LDC_OFFSET:
1216 case ARM::t2LDC_PRE:
1217 case ARM::t2LDC_POST:
1218 case ARM::t2LDC_OPTION:
1219 case ARM::t2LDCL_OFFSET:
1220 case ARM::t2LDCL_PRE:
1221 case ARM::t2LDCL_POST:
1222 case ARM::t2LDCL_OPTION:
1223 case ARM::t2STC_OFFSET:
1224 case ARM::t2STC_PRE:
1225 case ARM::t2STC_POST:
1226 case ARM::t2STC_OPTION:
1227 case ARM::t2STCL_OFFSET:
1228 case ARM::t2STCL_PRE:
1229 case ARM::t2STCL_POST:
1230 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1231 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1232 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1233 break;
1234 default:
1235 break;
1236 }
1237
1238 Inst.addOperand(MCOperand::CreateImm(coproc));
1239 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1241 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1242
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1243 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1244 case ARM::t2LDC2_OFFSET:
1245 case ARM::t2LDC2L_OFFSET:
1246 case ARM::t2LDC2_PRE:
1247 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1248 case ARM::t2STC2_OFFSET:
1249 case ARM::t2STC2L_OFFSET:
1250 case ARM::t2STC2_PRE:
1251 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1252 case ARM::LDC2_OFFSET:
1253 case ARM::LDC2L_OFFSET:
1254 case ARM::LDC2_PRE:
1255 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1256 case ARM::STC2_OFFSET:
1257 case ARM::STC2L_OFFSET:
1258 case ARM::STC2_PRE:
1259 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1260 case ARM::t2LDC_OFFSET:
1261 case ARM::t2LDCL_OFFSET:
1262 case ARM::t2LDC_PRE:
1263 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1264 case ARM::t2STC_OFFSET:
1265 case ARM::t2STCL_OFFSET:
1266 case ARM::t2STC_PRE:
1267 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1268 case ARM::LDC_OFFSET:
1269 case ARM::LDCL_OFFSET:
1270 case ARM::LDC_PRE:
1271 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1272 case ARM::STC_OFFSET:
1273 case ARM::STCL_OFFSET:
1274 case ARM::STC_PRE:
1275 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1276 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1277 Inst.addOperand(MCOperand::CreateImm(imm));
1278 break;
1279 case ARM::t2LDC2_POST:
1280 case ARM::t2LDC2L_POST:
1281 case ARM::t2STC2_POST:
1282 case ARM::t2STC2L_POST:
1283 case ARM::LDC2_POST:
1284 case ARM::LDC2L_POST:
1285 case ARM::STC2_POST:
1286 case ARM::STC2L_POST:
1287 case ARM::t2LDC_POST:
1288 case ARM::t2LDCL_POST:
1289 case ARM::t2STC_POST:
1290 case ARM::t2STCL_POST:
1291 case ARM::LDC_POST:
1292 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1293 case ARM::STC_POST:
1294 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1296 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1297 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1298 // The 'option' variant doesn't encode 'U' in the immediate since
1299 // the immediate is unsigned [0,255].
1300 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1301 break;
1302 }
1303
1304 switch (Inst.getOpcode()) {
1305 case ARM::LDC_OFFSET:
1306 case ARM::LDC_PRE:
1307 case ARM::LDC_POST:
1308 case ARM::LDC_OPTION:
1309 case ARM::LDCL_OFFSET:
1310 case ARM::LDCL_PRE:
1311 case ARM::LDCL_POST:
1312 case ARM::LDCL_OPTION:
1313 case ARM::STC_OFFSET:
1314 case ARM::STC_PRE:
1315 case ARM::STC_POST:
1316 case ARM::STC_OPTION:
1317 case ARM::STCL_OFFSET:
1318 case ARM::STCL_PRE:
1319 case ARM::STCL_POST:
1320 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1322 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1323 break;
1324 default:
1325 break;
1326 }
1327
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1328 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1329}
1330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1331static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1332DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1333 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1334 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1335
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1336 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1337 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1338 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1339 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1340 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1341 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1342 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1343 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1344
1345 // On stores, the writeback operand precedes Rt.
1346 switch (Inst.getOpcode()) {
1347 case ARM::STR_POST_IMM:
1348 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1349 case ARM::STRB_POST_IMM:
1350 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1351 case ARM::STRT_POST_REG:
1352 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1353 case ARM::STRBT_POST_REG:
1354 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1356 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1357 break;
1358 default:
1359 break;
1360 }
1361
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1363 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1364
1365 // On loads, the writeback operand comes after Rt.
1366 switch (Inst.getOpcode()) {
1367 case ARM::LDR_POST_IMM:
1368 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1369 case ARM::LDRB_POST_IMM:
1370 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1371 case ARM::LDRBT_POST_REG:
1372 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1373 case ARM::LDRT_POST_REG:
1374 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1376 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1377 break;
1378 default:
1379 break;
1380 }
1381
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1383 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1384
1385 ARM_AM::AddrOpc Op = ARM_AM::add;
1386 if (!fieldFromInstruction32(Insn, 23, 1))
1387 Op = ARM_AM::sub;
1388
1389 bool writeback = (P == 0) || (W == 1);
1390 unsigned idx_mode = 0;
1391 if (P && writeback)
1392 idx_mode = ARMII::IndexModePre;
1393 else if (!P && writeback)
1394 idx_mode = ARMII::IndexModePost;
1395
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1396 if (writeback && (Rn == 15 || Rn == Rt))
1397 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1398
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1399 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1403 switch( fieldFromInstruction32(Insn, 5, 2)) {
1404 case 0:
1405 Opc = ARM_AM::lsl;
1406 break;
1407 case 1:
1408 Opc = ARM_AM::lsr;
1409 break;
1410 case 2:
1411 Opc = ARM_AM::asr;
1412 break;
1413 case 3:
1414 Opc = ARM_AM::ror;
1415 break;
1416 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1417 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1418 }
1419 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1420 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1421
1422 Inst.addOperand(MCOperand::CreateImm(imm));
1423 } else {
1424 Inst.addOperand(MCOperand::CreateReg(0));
1425 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1426 Inst.addOperand(MCOperand::CreateImm(tmp));
1427 }
1428
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1430 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1431
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1432 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1433}
1434
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1437 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1438
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1439 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1440 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1441 unsigned type = fieldFromInstruction32(Val, 5, 2);
1442 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1443 unsigned U = fieldFromInstruction32(Val, 12, 1);
1444
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1445 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1446 switch (type) {
1447 case 0:
1448 ShOp = ARM_AM::lsl;
1449 break;
1450 case 1:
1451 ShOp = ARM_AM::lsr;
1452 break;
1453 case 2:
1454 ShOp = ARM_AM::asr;
1455 break;
1456 case 3:
1457 ShOp = ARM_AM::ror;
1458 break;
1459 }
1460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1462 return MCDisassembler::Fail;
1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1464 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1465 unsigned shift;
1466 if (U)
1467 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1468 else
1469 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1470 Inst.addOperand(MCOperand::CreateImm(shift));
1471
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1472 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1473}
1474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1475static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1476DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1477 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1478 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1479
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1480 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1481 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1482 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1483 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1484 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1485 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1486 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1487 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1488 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1489
1490 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1491
1492 // For {LD,ST}RD, Rt must be even, else undefined.
1493 switch (Inst.getOpcode()) {
1494 case ARM::STRD:
1495 case ARM::STRD_PRE:
1496 case ARM::STRD_POST:
1497 case ARM::LDRD:
1498 case ARM::LDRD_PRE:
1499 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1500 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1501 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1502 default:
1503 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1504 }
1505
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1506 if (writeback) { // Writeback
1507 if (P)
1508 U |= ARMII::IndexModePre << 9;
1509 else
1510 U |= ARMII::IndexModePost << 9;
1511
1512 // On stores, the writeback operand precedes Rt.
1513 switch (Inst.getOpcode()) {
1514 case ARM::STRD:
1515 case ARM::STRD_PRE:
1516 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1517 case ARM::STRH:
1518 case ARM::STRH_PRE:
1519 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1521 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1522 break;
1523 default:
1524 break;
1525 }
1526 }
1527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1529 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530 switch (Inst.getOpcode()) {
1531 case ARM::STRD:
1532 case ARM::STRD_PRE:
1533 case ARM::STRD_POST:
1534 case ARM::LDRD:
1535 case ARM::LDRD_PRE:
1536 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1538 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1539 break;
1540 default:
1541 break;
1542 }
1543
1544 if (writeback) {
1545 // On loads, the writeback operand comes after Rt.
1546 switch (Inst.getOpcode()) {
1547 case ARM::LDRD:
1548 case ARM::LDRD_PRE:
1549 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1550 case ARM::LDRH:
1551 case ARM::LDRH_PRE:
1552 case ARM::LDRH_POST:
1553 case ARM::LDRSH:
1554 case ARM::LDRSH_PRE:
1555 case ARM::LDRSH_POST:
1556 case ARM::LDRSB:
1557 case ARM::LDRSB_PRE:
1558 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1559 case ARM::LDRHTr:
1560 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1562 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1563 break;
1564 default:
1565 break;
1566 }
1567 }
1568
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1570 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1571
1572 if (type) {
1573 Inst.addOperand(MCOperand::CreateReg(0));
1574 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1575 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1577 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1578 Inst.addOperand(MCOperand::CreateImm(U));
1579 }
1580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1582 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585}
1586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1588 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1589 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1590
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1591 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1592 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1593
1594 switch (mode) {
1595 case 0:
1596 mode = ARM_AM::da;
1597 break;
1598 case 1:
1599 mode = ARM_AM::ia;
1600 break;
1601 case 2:
1602 mode = ARM_AM::db;
1603 break;
1604 case 3:
1605 mode = ARM_AM::ib;
1606 break;
1607 }
1608
1609 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1611 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1613 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1614}
1615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1616static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1617 unsigned Insn,
1618 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1619 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1620
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1621 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1622 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1623 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1624
1625 if (pred == 0xF) {
1626 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1627 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1628 Inst.setOpcode(ARM::RFEDA);
1629 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1630 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1631 Inst.setOpcode(ARM::RFEDA_UPD);
1632 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1633 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634 Inst.setOpcode(ARM::RFEDB);
1635 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1636 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 Inst.setOpcode(ARM::RFEDB_UPD);
1638 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1639 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 Inst.setOpcode(ARM::RFEIA);
1641 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1642 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1643 Inst.setOpcode(ARM::RFEIA_UPD);
1644 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1645 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646 Inst.setOpcode(ARM::RFEIB);
1647 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1648 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1649 Inst.setOpcode(ARM::RFEIB_UPD);
1650 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1651 case ARM::STMDA:
1652 Inst.setOpcode(ARM::SRSDA);
1653 break;
1654 case ARM::STMDA_UPD:
1655 Inst.setOpcode(ARM::SRSDA_UPD);
1656 break;
1657 case ARM::STMDB:
1658 Inst.setOpcode(ARM::SRSDB);
1659 break;
1660 case ARM::STMDB_UPD:
1661 Inst.setOpcode(ARM::SRSDB_UPD);
1662 break;
1663 case ARM::STMIA:
1664 Inst.setOpcode(ARM::SRSIA);
1665 break;
1666 case ARM::STMIA_UPD:
1667 Inst.setOpcode(ARM::SRSIA_UPD);
1668 break;
1669 case ARM::STMIB:
1670 Inst.setOpcode(ARM::SRSIB);
1671 break;
1672 case ARM::STMIB_UPD:
1673 Inst.setOpcode(ARM::SRSIB_UPD);
1674 break;
1675 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1676 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1677 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1678
1679 // For stores (which become SRS's, the only operand is the mode.
1680 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1681 Inst.addOperand(
1682 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1683 return S;
1684 }
1685
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1686 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1687 }
1688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1690 return MCDisassembler::Fail;
1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1692 return MCDisassembler::Fail; // Tied
1693 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1694 return MCDisassembler::Fail;
1695 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1696 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1697
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1698 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1699}
1700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1702 uint64_t Address, const void *Decoder) {
1703 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1704 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1705 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1706 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1708 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1709
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1710 // imod == '01' --> UNPREDICTABLE
1711 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1712 // return failure here. The '01' imod value is unprintable, so there's
1713 // nothing useful we could do even if we returned UNPREDICTABLE.
1714
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1715 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1716
1717 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718 Inst.setOpcode(ARM::CPS3p);
1719 Inst.addOperand(MCOperand::CreateImm(imod));
1720 Inst.addOperand(MCOperand::CreateImm(iflags));
1721 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1722 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723 Inst.setOpcode(ARM::CPS2p);
1724 Inst.addOperand(MCOperand::CreateImm(imod));
1725 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1726 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1727 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1728 Inst.setOpcode(ARM::CPS1p);
1729 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1730 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1731 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1732 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1733 Inst.setOpcode(ARM::CPS1p);
1734 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1735 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1736 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1737
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1738 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1739}
1740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1741static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1742 uint64_t Address, const void *Decoder) {
1743 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1744 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1745 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1746 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1747
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1748 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1749
1750 // imod == '01' --> UNPREDICTABLE
1751 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1752 // return failure here. The '01' imod value is unprintable, so there's
1753 // nothing useful we could do even if we returned UNPREDICTABLE.
1754
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1755 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1756
1757 if (imod && M) {
1758 Inst.setOpcode(ARM::t2CPS3p);
1759 Inst.addOperand(MCOperand::CreateImm(imod));
1760 Inst.addOperand(MCOperand::CreateImm(iflags));
1761 Inst.addOperand(MCOperand::CreateImm(mode));
1762 } else if (imod && !M) {
1763 Inst.setOpcode(ARM::t2CPS2p);
1764 Inst.addOperand(MCOperand::CreateImm(imod));
1765 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1766 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1767 } else if (!imod && M) {
1768 Inst.setOpcode(ARM::t2CPS1p);
1769 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1770 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1771 } else {
1772 // imod == '00' && M == '0' --> UNPREDICTABLE
1773 Inst.setOpcode(ARM::t2CPS1p);
1774 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1775 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1776 }
1777
1778 return S;
1779}
1780
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1781static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1782 uint64_t Address, const void *Decoder) {
1783 DecodeStatus S = MCDisassembler::Success;
1784
1785 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1786 unsigned imm = 0;
1787
1788 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1789 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1790 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1791 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1792
1793 if (Inst.getOpcode() == ARM::t2MOVTi16)
1794 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1795 return MCDisassembler::Fail;
1796 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1797 return MCDisassembler::Fail;
1798
1799 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1800 Inst.addOperand(MCOperand::CreateImm(imm));
1801
1802 return S;
1803}
1804
1805static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1806 uint64_t Address, const void *Decoder) {
1807 DecodeStatus S = MCDisassembler::Success;
1808
1809 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1810 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1811 unsigned imm = 0;
1812
1813 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1814 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1815
1816 if (Inst.getOpcode() == ARM::MOVTi16)
1817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1818 return MCDisassembler::Fail;
1819 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1820 return MCDisassembler::Fail;
1821
1822 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1823 Inst.addOperand(MCOperand::CreateImm(imm));
1824
1825 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1826 return MCDisassembler::Fail;
1827
1828 return S;
1829}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1830
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1831static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1833 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1834
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1836 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1837 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1838 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1839 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1840
1841 if (pred == 0xF)
1842 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1843
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1851 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1853 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1854 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1855
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1856 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1857}
1858
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1859static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1860 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1861 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1862
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1863 unsigned add = fieldFromInstruction32(Val, 12, 1);
1864 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1865 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1868 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869
1870 if (!add) imm *= -1;
1871 if (imm == 0 && !add) imm = INT32_MIN;
1872 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1873 if (Rn == 15)
1874 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1875
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1876 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1877}
1878
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1880 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1882
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1883 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1884 unsigned U = fieldFromInstruction32(Val, 8, 1);
1885 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889
1890 if (U)
1891 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1892 else
1893 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1894
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1895 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1896}
1897
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1898static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899 uint64_t Address, const void *Decoder) {
1900 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1901}
1902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1903static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1904DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1905 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1906 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1907
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1908 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1909 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1910
1911 if (pred == 0xF) {
1912 Inst.setOpcode(ARM::BLXi);
1913 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1915 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1916 }
1917
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1918 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1919 4, Inst, Decoder))
1920 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1921 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1922 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1924 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925}
1926
1927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1928static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929 uint64_t Address, const void *Decoder) {
1930 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1931 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1932}
1933
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1934static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1935 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1936 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1937
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1938 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1939 unsigned align = fieldFromInstruction32(Val, 4, 2);
1940
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1942 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1943 if (!align)
1944 Inst.addOperand(MCOperand::CreateImm(0));
1945 else
1946 Inst.addOperand(MCOperand::CreateImm(4 << align));
1947
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1948 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949}
1950
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1951static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1952 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1953 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1954
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1955 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1956 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1957 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1958 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1959 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1960 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1961
1962 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1963 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1964 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1965
1966 // Second output register
1967 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1968 case ARM::VLD3d8:
1969 case ARM::VLD3d16:
1970 case ARM::VLD3d32:
1971 case ARM::VLD3d8_UPD:
1972 case ARM::VLD3d16_UPD:
1973 case ARM::VLD3d32_UPD:
1974 case ARM::VLD4d8:
1975 case ARM::VLD4d16:
1976 case ARM::VLD4d32:
1977 case ARM::VLD4d8_UPD:
1978 case ARM::VLD4d16_UPD:
1979 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1980 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1981 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1982 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1983 case ARM::VLD3q8:
1984 case ARM::VLD3q16:
1985 case ARM::VLD3q32:
1986 case ARM::VLD3q8_UPD:
1987 case ARM::VLD3q16_UPD:
1988 case ARM::VLD3q32_UPD:
1989 case ARM::VLD4q8:
1990 case ARM::VLD4q16:
1991 case ARM::VLD4q32:
1992 case ARM::VLD4q8_UPD:
1993 case ARM::VLD4q16_UPD:
1994 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1995 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1996 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1997 default:
1998 break;
1999 }
2000
2001 // Third output register
2002 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2003 case ARM::VLD3d8:
2004 case ARM::VLD3d16:
2005 case ARM::VLD3d32:
2006 case ARM::VLD3d8_UPD:
2007 case ARM::VLD3d16_UPD:
2008 case ARM::VLD3d32_UPD:
2009 case ARM::VLD4d8:
2010 case ARM::VLD4d16:
2011 case ARM::VLD4d32:
2012 case ARM::VLD4d8_UPD:
2013 case ARM::VLD4d16_UPD:
2014 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2015 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2016 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2017 break;
2018 case ARM::VLD3q8:
2019 case ARM::VLD3q16:
2020 case ARM::VLD3q32:
2021 case ARM::VLD3q8_UPD:
2022 case ARM::VLD3q16_UPD:
2023 case ARM::VLD3q32_UPD:
2024 case ARM::VLD4q8:
2025 case ARM::VLD4q16:
2026 case ARM::VLD4q32:
2027 case ARM::VLD4q8_UPD:
2028 case ARM::VLD4q16_UPD:
2029 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2030 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2031 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2032 break;
2033 default:
2034 break;
2035 }
2036
2037 // Fourth output register
2038 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2039 case ARM::VLD4d8:
2040 case ARM::VLD4d16:
2041 case ARM::VLD4d32:
2042 case ARM::VLD4d8_UPD:
2043 case ARM::VLD4d16_UPD:
2044 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2045 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2046 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2047 break;
2048 case ARM::VLD4q8:
2049 case ARM::VLD4q16:
2050 case ARM::VLD4q32:
2051 case ARM::VLD4q8_UPD:
2052 case ARM::VLD4q16_UPD:
2053 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2054 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2055 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056 break;
2057 default:
2058 break;
2059 }
2060
2061 // Writeback operand
2062 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2063 case ARM::VLD1d8wb_fixed:
2064 case ARM::VLD1d16wb_fixed:
2065 case ARM::VLD1d32wb_fixed:
2066 case ARM::VLD1d64wb_fixed:
2067 case ARM::VLD1d8wb_register:
2068 case ARM::VLD1d16wb_register:
2069 case ARM::VLD1d32wb_register:
2070 case ARM::VLD1d64wb_register:
2071 case ARM::VLD1q8wb_fixed:
2072 case ARM::VLD1q16wb_fixed:
2073 case ARM::VLD1q32wb_fixed:
2074 case ARM::VLD1q64wb_fixed:
2075 case ARM::VLD1q8wb_register:
2076 case ARM::VLD1q16wb_register:
2077 case ARM::VLD1q32wb_register:
2078 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2079 case ARM::VLD1d8Twb_fixed:
2080 case ARM::VLD1d8Twb_register:
2081 case ARM::VLD1d16Twb_fixed:
2082 case ARM::VLD1d16Twb_register:
2083 case ARM::VLD1d32Twb_fixed:
2084 case ARM::VLD1d32Twb_register:
2085 case ARM::VLD1d64Twb_fixed:
2086 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2087 case ARM::VLD1d8Qwb_fixed:
2088 case ARM::VLD1d8Qwb_register:
2089 case ARM::VLD1d16Qwb_fixed:
2090 case ARM::VLD1d16Qwb_register:
2091 case ARM::VLD1d32Qwb_fixed:
2092 case ARM::VLD1d32Qwb_register:
2093 case ARM::VLD1d64Qwb_fixed:
2094 case ARM::VLD1d64Qwb_register:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2095 case ARM::VLD2d8_UPD:
2096 case ARM::VLD2d16_UPD:
2097 case ARM::VLD2d32_UPD:
2098 case ARM::VLD2q8_UPD:
2099 case ARM::VLD2q16_UPD:
2100 case ARM::VLD2q32_UPD:
2101 case ARM::VLD2b8_UPD:
2102 case ARM::VLD2b16_UPD:
2103 case ARM::VLD2b32_UPD:
2104 case ARM::VLD3d8_UPD:
2105 case ARM::VLD3d16_UPD:
2106 case ARM::VLD3d32_UPD:
2107 case ARM::VLD3q8_UPD:
2108 case ARM::VLD3q16_UPD:
2109 case ARM::VLD3q32_UPD:
2110 case ARM::VLD4d8_UPD:
2111 case ARM::VLD4d16_UPD:
2112 case ARM::VLD4d32_UPD:
2113 case ARM::VLD4q8_UPD:
2114 case ARM::VLD4q16_UPD:
2115 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2116 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2117 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2118 break;
2119 default:
2120 break;
2121 }
2122
2123 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2124 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2125 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2126
2127 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2128 switch (Inst.getOpcode()) {
2129 default:
2130 // The below have been updated to have explicit am6offset split
2131 // between fixed and register offset. For those instructions not
2132 // yet updated, we need to add an additional reg0 operand for the
2133 // fixed variant.
2134 //
2135 // The fixed offset encodes as Rm == 0xd, so we check for that.
2136 if (Rm == 0xd) {
2137 Inst.addOperand(MCOperand::CreateReg(0));
2138 break;
2139 }
2140 // Fall through to handle the register offset variant.
2141 case ARM::VLD1d8wb_fixed:
2142 case ARM::VLD1d16wb_fixed:
2143 case ARM::VLD1d32wb_fixed:
2144 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2145 case ARM::VLD1d8Twb_fixed:
2146 case ARM::VLD1d16Twb_fixed:
2147 case ARM::VLD1d32Twb_fixed:
2148 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2149 case ARM::VLD1d8Qwb_fixed:
2150 case ARM::VLD1d16Qwb_fixed:
2151 case ARM::VLD1d32Qwb_fixed:
2152 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2153 case ARM::VLD1d8wb_register:
2154 case ARM::VLD1d16wb_register:
2155 case ARM::VLD1d32wb_register:
2156 case ARM::VLD1d64wb_register:
2157 case ARM::VLD1q8wb_fixed:
2158 case ARM::VLD1q16wb_fixed:
2159 case ARM::VLD1q32wb_fixed:
2160 case ARM::VLD1q64wb_fixed:
2161 case ARM::VLD1q8wb_register:
2162 case ARM::VLD1q16wb_register:
2163 case ARM::VLD1q32wb_register:
2164 case ARM::VLD1q64wb_register:
2165 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2166 // variant encodes Rm == 0xf. Anything else is a register offset post-
2167 // increment and we need to add the register operand to the instruction.
2168 if (Rm != 0xD && Rm != 0xF &&
2169 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2170 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2171 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2172 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2173
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2174 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2175}
2176
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2177static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2178 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2179 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2180
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2181 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2182 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2183 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2184 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2185 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2186 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2187
2188 // Writeback Operand
2189 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2190 case ARM::VST1d8wb_fixed:
2191 case ARM::VST1d16wb_fixed:
2192 case ARM::VST1d32wb_fixed:
2193 case ARM::VST1d64wb_fixed:
2194 case ARM::VST1d8wb_register:
2195 case ARM::VST1d16wb_register:
2196 case ARM::VST1d32wb_register:
2197 case ARM::VST1d64wb_register:
2198 case ARM::VST1q8wb_fixed:
2199 case ARM::VST1q16wb_fixed:
2200 case ARM::VST1q32wb_fixed:
2201 case ARM::VST1q64wb_fixed:
2202 case ARM::VST1q8wb_register:
2203 case ARM::VST1q16wb_register:
2204 case ARM::VST1q32wb_register:
2205 case ARM::VST1q64wb_register:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2206 case ARM::VST1d8T_UPD:
2207 case ARM::VST1d16T_UPD:
2208 case ARM::VST1d32T_UPD:
2209 case ARM::VST1d64T_UPD:
2210 case ARM::VST1d8Q_UPD:
2211 case ARM::VST1d16Q_UPD:
2212 case ARM::VST1d32Q_UPD:
2213 case ARM::VST1d64Q_UPD:
2214 case ARM::VST2d8_UPD:
2215 case ARM::VST2d16_UPD:
2216 case ARM::VST2d32_UPD:
2217 case ARM::VST2q8_UPD:
2218 case ARM::VST2q16_UPD:
2219 case ARM::VST2q32_UPD:
2220 case ARM::VST2b8_UPD:
2221 case ARM::VST2b16_UPD:
2222 case ARM::VST2b32_UPD:
2223 case ARM::VST3d8_UPD:
2224 case ARM::VST3d16_UPD:
2225 case ARM::VST3d32_UPD:
2226 case ARM::VST3q8_UPD:
2227 case ARM::VST3q16_UPD:
2228 case ARM::VST3q32_UPD:
2229 case ARM::VST4d8_UPD:
2230 case ARM::VST4d16_UPD:
2231 case ARM::VST4d32_UPD:
2232 case ARM::VST4q8_UPD:
2233 case ARM::VST4q16_UPD:
2234 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2235 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2236 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2237 break;
2238 default:
2239 break;
2240 }
2241
2242 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2243 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2244 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2245
2246 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2247 switch (Inst.getOpcode()) {
2248 default:
2249 if (Rm == 0xD)
2250 Inst.addOperand(MCOperand::CreateReg(0));
2251 else if (Rm != 0xF) {
2252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2253 return MCDisassembler::Fail;
2254 }
2255 break;
2256 case ARM::VST1d8wb_fixed:
2257 case ARM::VST1d16wb_fixed:
2258 case ARM::VST1d32wb_fixed:
2259 case ARM::VST1d64wb_fixed:
2260 case ARM::VST1q8wb_fixed:
2261 case ARM::VST1q16wb_fixed:
2262 case ARM::VST1q32wb_fixed:
2263 case ARM::VST1q64wb_fixed:
2264 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2265 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2267
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2268 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2270 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2271
2272 // Second input register
2273 switch (Inst.getOpcode()) {
2274 case ARM::VST1q8:
2275 case ARM::VST1q16:
2276 case ARM::VST1q32:
2277 case ARM::VST1q64:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2278 case ARM::VST1d8T:
2279 case ARM::VST1d16T:
2280 case ARM::VST1d32T:
2281 case ARM::VST1d64T:
2282 case ARM::VST1d8T_UPD:
2283 case ARM::VST1d16T_UPD:
2284 case ARM::VST1d32T_UPD:
2285 case ARM::VST1d64T_UPD:
2286 case ARM::VST1d8Q:
2287 case ARM::VST1d16Q:
2288 case ARM::VST1d32Q:
2289 case ARM::VST1d64Q:
2290 case ARM::VST1d8Q_UPD:
2291 case ARM::VST1d16Q_UPD:
2292 case ARM::VST1d32Q_UPD:
2293 case ARM::VST1d64Q_UPD:
2294 case ARM::VST2d8:
2295 case ARM::VST2d16:
2296 case ARM::VST2d32:
2297 case ARM::VST2d8_UPD:
2298 case ARM::VST2d16_UPD:
2299 case ARM::VST2d32_UPD:
2300 case ARM::VST2q8:
2301 case ARM::VST2q16:
2302 case ARM::VST2q32:
2303 case ARM::VST2q8_UPD:
2304 case ARM::VST2q16_UPD:
2305 case ARM::VST2q32_UPD:
2306 case ARM::VST3d8:
2307 case ARM::VST3d16:
2308 case ARM::VST3d32:
2309 case ARM::VST3d8_UPD:
2310 case ARM::VST3d16_UPD:
2311 case ARM::VST3d32_UPD:
2312 case ARM::VST4d8:
2313 case ARM::VST4d16:
2314 case ARM::VST4d32:
2315 case ARM::VST4d8_UPD:
2316 case ARM::VST4d16_UPD:
2317 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2319 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2320 break;
2321 case ARM::VST2b8:
2322 case ARM::VST2b16:
2323 case ARM::VST2b32:
2324 case ARM::VST2b8_UPD:
2325 case ARM::VST2b16_UPD:
2326 case ARM::VST2b32_UPD:
2327 case ARM::VST3q8:
2328 case ARM::VST3q16:
2329 case ARM::VST3q32:
2330 case ARM::VST3q8_UPD:
2331 case ARM::VST3q16_UPD:
2332 case ARM::VST3q32_UPD:
2333 case ARM::VST4q8:
2334 case ARM::VST4q16:
2335 case ARM::VST4q32:
2336 case ARM::VST4q8_UPD:
2337 case ARM::VST4q16_UPD:
2338 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2339 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2340 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2341 break;
2342 default:
2343 break;
2344 }
2345
2346 // Third input register
2347 switch (Inst.getOpcode()) {
2348 case ARM::VST1d8T:
2349 case ARM::VST1d16T:
2350 case ARM::VST1d32T:
2351 case ARM::VST1d64T:
2352 case ARM::VST1d8T_UPD:
2353 case ARM::VST1d16T_UPD:
2354 case ARM::VST1d32T_UPD:
2355 case ARM::VST1d64T_UPD:
2356 case ARM::VST1d8Q:
2357 case ARM::VST1d16Q:
2358 case ARM::VST1d32Q:
2359 case ARM::VST1d64Q:
2360 case ARM::VST1d8Q_UPD:
2361 case ARM::VST1d16Q_UPD:
2362 case ARM::VST1d32Q_UPD:
2363 case ARM::VST1d64Q_UPD:
2364 case ARM::VST2q8:
2365 case ARM::VST2q16:
2366 case ARM::VST2q32:
2367 case ARM::VST2q8_UPD:
2368 case ARM::VST2q16_UPD:
2369 case ARM::VST2q32_UPD:
2370 case ARM::VST3d8:
2371 case ARM::VST3d16:
2372 case ARM::VST3d32:
2373 case ARM::VST3d8_UPD:
2374 case ARM::VST3d16_UPD:
2375 case ARM::VST3d32_UPD:
2376 case ARM::VST4d8:
2377 case ARM::VST4d16:
2378 case ARM::VST4d32:
2379 case ARM::VST4d8_UPD:
2380 case ARM::VST4d16_UPD:
2381 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2383 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2384 break;
2385 case ARM::VST3q8:
2386 case ARM::VST3q16:
2387 case ARM::VST3q32:
2388 case ARM::VST3q8_UPD:
2389 case ARM::VST3q16_UPD:
2390 case ARM::VST3q32_UPD:
2391 case ARM::VST4q8:
2392 case ARM::VST4q16:
2393 case ARM::VST4q32:
2394 case ARM::VST4q8_UPD:
2395 case ARM::VST4q16_UPD:
2396 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2397 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2398 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2399 break;
2400 default:
2401 break;
2402 }
2403
2404 // Fourth input register
2405 switch (Inst.getOpcode()) {
2406 case ARM::VST1d8Q:
2407 case ARM::VST1d16Q:
2408 case ARM::VST1d32Q:
2409 case ARM::VST1d64Q:
2410 case ARM::VST1d8Q_UPD:
2411 case ARM::VST1d16Q_UPD:
2412 case ARM::VST1d32Q_UPD:
2413 case ARM::VST1d64Q_UPD:
2414 case ARM::VST2q8:
2415 case ARM::VST2q16:
2416 case ARM::VST2q32:
2417 case ARM::VST2q8_UPD:
2418 case ARM::VST2q16_UPD:
2419 case ARM::VST2q32_UPD:
2420 case ARM::VST4d8:
2421 case ARM::VST4d16:
2422 case ARM::VST4d32:
2423 case ARM::VST4d8_UPD:
2424 case ARM::VST4d16_UPD:
2425 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2426 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2427 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428 break;
2429 case ARM::VST4q8:
2430 case ARM::VST4q16:
2431 case ARM::VST4q32:
2432 case ARM::VST4q8_UPD:
2433 case ARM::VST4q16_UPD:
2434 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2435 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2436 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2437 break;
2438 default:
2439 break;
2440 }
2441
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2442 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2443}
2444
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2445static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2446 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2447 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2448
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2449 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2450 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2451 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2452 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2453 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2454 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2455 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2456
2457 align *= (1 << size);
2458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2460 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2461 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2463 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2464 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2465 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2467 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2468 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2469
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2470 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2471 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2472 Inst.addOperand(MCOperand::CreateImm(align));
2473
2474 if (Rm == 0xD)
2475 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2476 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2478 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2479 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2480
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2481 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2482}
2483
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2484static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2487
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2488 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2489 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2490 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2491 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2492 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2493 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2494 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2495 align *= 2*size;
2496
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2498 return MCDisassembler::Fail;
2499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2500 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2501 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2503 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2504 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2505
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2507 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2508 Inst.addOperand(MCOperand::CreateImm(align));
2509
2510 if (Rm == 0xD)
2511 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2512 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2514 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2515 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2516
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2517 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2518}
2519
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2520static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2522 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2523
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2525 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2526 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2527 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2528 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2531 return MCDisassembler::Fail;
2532 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2533 return MCDisassembler::Fail;
2534 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2535 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2536 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2538 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2539 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2540
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2542 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2543 Inst.addOperand(MCOperand::CreateImm(0));
2544
2545 if (Rm == 0xD)
2546 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2547 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2549 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2550 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2551
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2552 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2553}
2554
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2555static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2557 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2558
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2560 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2561 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2562 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2563 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2564 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2565 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2566
2567 if (size == 0x3) {
2568 size = 4;
2569 align = 16;
2570 } else {
2571 if (size == 2) {
2572 size = 1 << size;
2573 align *= 8;
2574 } else {
2575 size = 1 << size;
2576 align *= 4*size;
2577 }
2578 }
2579
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2580 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2581 return MCDisassembler::Fail;
2582 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2583 return MCDisassembler::Fail;
2584 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2585 return MCDisassembler::Fail;
2586 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2587 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2588 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2590 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2591 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2592
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2594 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595 Inst.addOperand(MCOperand::CreateImm(align));
2596
2597 if (Rm == 0xD)
2598 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2599 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2601 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2602 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2604 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2605}
2606
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2607static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2608DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2611
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2613 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2614 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2615 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2616 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2617 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2618 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2619 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2620
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2621 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2622 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2623 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2624 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2626 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2627 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2628
2629 Inst.addOperand(MCOperand::CreateImm(imm));
2630
2631 switch (Inst.getOpcode()) {
2632 case ARM::VORRiv4i16:
2633 case ARM::VORRiv2i32:
2634 case ARM::VBICiv4i16:
2635 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2637 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638 break;
2639 case ARM::VORRiv8i16:
2640 case ARM::VORRiv4i32:
2641 case ARM::VBICiv8i16:
2642 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2643 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2644 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2645 break;
2646 default:
2647 break;
2648 }
2649
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2650 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2651}
2652
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2653static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2655 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2656
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2657 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2658 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2659 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2660 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2661 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2662
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2663 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2664 return MCDisassembler::Fail;
2665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2666 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2667 Inst.addOperand(MCOperand::CreateImm(8 << size));
2668
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2669 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670}
2671
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2672static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673 uint64_t Address, const void *Decoder) {
2674 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2675 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2676}
2677
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2678static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679 uint64_t Address, const void *Decoder) {
2680 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2681 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682}
2683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2684static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2685 uint64_t Address, const void *Decoder) {
2686 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2687 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688}
2689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2690static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691 uint64_t Address, const void *Decoder) {
2692 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2693 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694}
2695
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2696static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2698 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2699
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2702 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2703 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2704 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2705 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2706 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2707 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2708
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2710 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2711 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2713 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2714 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2715
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2716 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2718 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2719 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2722 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2723
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2724 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2725}
2726
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2727static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2728 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2729 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2730
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2731 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2732 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2733
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2734 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2735 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2736
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2737 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2738 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2739 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2740 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2741 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2742 case ARM::tADDrSPi:
2743 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2744 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2745 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2746
2747 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2748 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2749}
2750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2751static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2752 uint64_t Address, const void *Decoder) {
2753 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2754 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2755}
2756
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2757static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2758 uint64_t Address, const void *Decoder) {
2759 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2760 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761}
2762
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2763static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764 uint64_t Address, const void *Decoder) {
2765 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2766 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767}
2768
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2769static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2770 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2771 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2772
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2773 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2774 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2775
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2776 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2777 return MCDisassembler::Fail;
2778 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2779 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2780
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2781 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2782}
2783
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2784static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2786 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2787
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2788 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2789 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2790
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2791 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2792 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2793 Inst.addOperand(MCOperand::CreateImm(imm));
2794
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2795 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796}
2797
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2798static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2799 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2800 unsigned imm = Val << 2;
2801
2802 Inst.addOperand(MCOperand::CreateImm(imm));
2803 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2805 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2806}
2807
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2808static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809 uint64_t Address, const void *Decoder) {
2810 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2811 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2813 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814}
2815
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2816static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2818 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2819
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2821 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2822 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2823
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2825 return MCDisassembler::Fail;
2826 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2827 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2828 Inst.addOperand(MCOperand::CreateImm(imm));
2829
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2830 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2831}
2832
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2833static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2834 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2835 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2836
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2837 switch (Inst.getOpcode()) {
2838 case ARM::t2PLDs:
2839 case ARM::t2PLDWs:
2840 case ARM::t2PLIs:
2841 break;
2842 default: {
2843 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2845 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2846 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2847 }
2848
2849 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2850 if (Rn == 0xF) {
2851 switch (Inst.getOpcode()) {
2852 case ARM::t2LDRBs:
2853 Inst.setOpcode(ARM::t2LDRBpci);
2854 break;
2855 case ARM::t2LDRHs:
2856 Inst.setOpcode(ARM::t2LDRHpci);
2857 break;
2858 case ARM::t2LDRSHs:
2859 Inst.setOpcode(ARM::t2LDRSHpci);
2860 break;
2861 case ARM::t2LDRSBs:
2862 Inst.setOpcode(ARM::t2LDRSBpci);
2863 break;
2864 case ARM::t2PLDs:
2865 Inst.setOpcode(ARM::t2PLDi12);
2866 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2867 break;
2868 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2869 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870 }
2871
2872 int imm = fieldFromInstruction32(Insn, 0, 12);
2873 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2874 Inst.addOperand(MCOperand::CreateImm(imm));
2875
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2876 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2877 }
2878
2879 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2880 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2881 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2882 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2883 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2885 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886}
2887
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2888static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2889 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890 int imm = Val & 0xFF;
2891 if (!(Val & 0x100)) imm *= -1;
2892 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2893
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2894 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2895}
2896
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2897static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2899 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2900
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2902 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2903
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2905 return MCDisassembler::Fail;
2906 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2907 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2909 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910}
2911
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2912static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2913 uint64_t Address, const void *Decoder) {
2914 DecodeStatus S = MCDisassembler::Success;
2915
2916 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2917 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2918
2919 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2920 return MCDisassembler::Fail;
2921
2922 Inst.addOperand(MCOperand::CreateImm(imm));
2923
2924 return S;
2925}
2926
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2927static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2928 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2929 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2930 if (Val == 0)
2931 imm = INT32_MIN;
2932 else if (!(Val & 0x100))
2933 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934 Inst.addOperand(MCOperand::CreateImm(imm));
2935
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2936 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937}
2938
2939
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2940static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2941 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2942 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2943
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2944 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2945 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2946
2947 // Some instructions always use an additive offset.
2948 switch (Inst.getOpcode()) {
2949 case ARM::t2LDRT:
2950 case ARM::t2LDRBT:
2951 case ARM::t2LDRHT:
2952 case ARM::t2LDRSBT:
2953 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2954 case ARM::t2STRT:
2955 case ARM::t2STRBT:
2956 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2957 imm |= 0x100;
2958 break;
2959 default:
2960 break;
2961 }
2962
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2964 return MCDisassembler::Fail;
2965 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2966 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2968 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2969}
2970
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2971static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2972 uint64_t Address, const void *Decoder) {
2973 DecodeStatus S = MCDisassembler::Success;
2974
2975 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2976 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2977 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2978 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2979 addr |= Rn << 9;
2980 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2981
2982 if (!load) {
2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2984 return MCDisassembler::Fail;
2985 }
2986
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2987 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2988 return MCDisassembler::Fail;
2989
2990 if (load) {
2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993 }
2994
2995 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997
2998 return S;
2999}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3000
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3001static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3002 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3003 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3004
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3005 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3006 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3007
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3009 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010 Inst.addOperand(MCOperand::CreateImm(imm));
3011
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3012 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013}
3014
3015
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3016static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3017 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3019
3020 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3021 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3022 Inst.addOperand(MCOperand::CreateImm(imm));
3023
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3024 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3025}
3026
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3027static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3028 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3029 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3030
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3031 if (Inst.getOpcode() == ARM::tADDrSP) {
3032 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3033 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3034
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3036 return MCDisassembler::Fail;
3037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3038 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3039 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3040 } else if (Inst.getOpcode() == ARM::tADDspr) {
3041 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3042
3043 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3044 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3046 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3047 }
3048
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3049 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050}
3051
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3052static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3053 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3054 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3055 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3056
3057 Inst.addOperand(MCOperand::CreateImm(imod));
3058 Inst.addOperand(MCOperand::CreateImm(flags));
3059
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3060 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3061}
3062
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3063static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3064 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3065 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3067 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3068
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3070 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3071 Inst.addOperand(MCOperand::CreateImm(add));
3072
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3073 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074}
3075
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3076static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3077 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3078 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3079 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3080 true, 4, Inst, Decoder))
3081 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3082 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3083}
3084
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3085static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3086 uint64_t Address, const void *Decoder) {
3087 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3088 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3089
3090 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3091 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3092}
3093
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3094static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3095DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3096 uint64_t Address, const void *Decoder) {
3097 DecodeStatus S = MCDisassembler::Success;
3098
3099 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3101
3102 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3104 return MCDisassembler::Fail;
3105 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3106 return MCDisassembler::Fail;
3107 return S;
3108}
3109
3110static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3111DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3112 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3113 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3114
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3115 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3116 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3117 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3118 switch (opc) {
3119 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3120 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3121 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3122 Inst.setOpcode(ARM::t2DSB);
3123 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3124 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3125 Inst.setOpcode(ARM::t2DMB);
3126 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3127 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3128 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3129 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 }
3131
3132 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3133 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 }
3135
3136 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3137 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3138 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3139 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3140 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3142 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3143 return MCDisassembler::Fail;
3144 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3145 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3146
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3147 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3148}
3149
3150// Decode a shifted immediate operand. These basically consist
3151// of an 8-bit value, and a 4-bit directive that specifies either
3152// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3153static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3154 uint64_t Address, const void *Decoder) {
3155 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3156 if (ctrl == 0) {
3157 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3158 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3159 switch (byte) {
3160 case 0:
3161 Inst.addOperand(MCOperand::CreateImm(imm));
3162 break;
3163 case 1:
3164 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3165 break;
3166 case 2:
3167 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3168 break;
3169 case 3:
3170 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3171 (imm << 8) | imm));
3172 break;
3173 }
3174 } else {
3175 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3176 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3177 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3178 Inst.addOperand(MCOperand::CreateImm(imm));
3179 }
3180
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3181 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3182}
3183
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3184static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3185DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3186 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3187 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3188 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3189}
3190
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3191static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3192 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3193 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3194 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3195}
3196
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3197static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3198 uint64_t Address, const void *Decoder) {
3199 switch (Val) {
3200 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3201 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3202 case 0xF: // SY
3203 case 0xE: // ST
3204 case 0xB: // ISH
3205 case 0xA: // ISHST
3206 case 0x7: // NSH
3207 case 0x6: // NSHST
3208 case 0x3: // OSH
3209 case 0x2: // OSHST
3210 break;
3211 }
3212
3213 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3214 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3215}
3216
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3217static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3218 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3219 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3220 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3221 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3222}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3223
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3224static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3225 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3226 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3227
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3228 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3229 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3230 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3231
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3232 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3233
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3235 return MCDisassembler::Fail;
3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3237 return MCDisassembler::Fail;
3238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3239 return MCDisassembler::Fail;
3240 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3241 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3242
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3243 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3244}
3245
3246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3247static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3248 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3249 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3250
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3251 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3252 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3254 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3255
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3256 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3257 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3258
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3259 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3260 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3261
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3263 return MCDisassembler::Fail;
3264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3265 return MCDisassembler::Fail;
3266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3267 return MCDisassembler::Fail;
3268 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3269 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3270
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3271 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3272}
3273
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3274static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3275 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3276 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3277
3278 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3279 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3280 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3281 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3282 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3283 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3284
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3285 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3286
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3288 return MCDisassembler::Fail;
3289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3290 return MCDisassembler::Fail;
3291 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3292 return MCDisassembler::Fail;
3293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3294 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3295
3296 return S;
3297}
3298
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3299static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3300 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3301 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3302
3303 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3304 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3305 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3306 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3307 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3308 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3309 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3310
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3311 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3312 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3313
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3315 return MCDisassembler::Fail;
3316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3317 return MCDisassembler::Fail;
3318 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3321 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3322
3323 return S;
3324}
3325
3326
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3327static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3328 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3329 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3330
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3331 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3332 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3333 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3334 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3335 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3336 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3337
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3338 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3339
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3341 return MCDisassembler::Fail;
3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3343 return MCDisassembler::Fail;
3344 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3345 return MCDisassembler::Fail;
3346 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3347 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3348
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3349 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3350}
3351
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3352static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3353 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3354 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3355
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3356 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3357 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3358 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3359 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3360 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3361 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3362
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3363 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3364
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3366 return MCDisassembler::Fail;
3367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3368 return MCDisassembler::Fail;
3369 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3370 return MCDisassembler::Fail;
3371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3372 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3373
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3374 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3375}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3376
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3377static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3378 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3379 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3380
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3381 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3383 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3384 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3385 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3386
3387 unsigned align = 0;
3388 unsigned index = 0;
3389 switch (size) {
3390 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3391 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3392 case 0:
3393 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3394 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3395 index = fieldFromInstruction32(Insn, 5, 3);
3396 break;
3397 case 1:
3398 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3400 index = fieldFromInstruction32(Insn, 6, 2);
3401 if (fieldFromInstruction32(Insn, 4, 1))
3402 align = 2;
3403 break;
3404 case 2:
3405 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3406 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3407 index = fieldFromInstruction32(Insn, 7, 1);
3408 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3409 align = 4;
3410 }
3411
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3412 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3413 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3414 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3416 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3417 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3419 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3420 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3421 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3422 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3424 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3425 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3426 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3427 }
3428
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3429 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3430 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3431 Inst.addOperand(MCOperand::CreateImm(index));
3432
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3433 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3434}
3435
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3436static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3437 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3438 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3439
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3441 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3442 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3443 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3444 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3445
3446 unsigned align = 0;
3447 unsigned index = 0;
3448 switch (size) {
3449 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3450 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3451 case 0:
3452 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3453 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3454 index = fieldFromInstruction32(Insn, 5, 3);
3455 break;
3456 case 1:
3457 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3458 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3459 index = fieldFromInstruction32(Insn, 6, 2);
3460 if (fieldFromInstruction32(Insn, 4, 1))
3461 align = 2;
3462 break;
3463 case 2:
3464 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3465 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3466 index = fieldFromInstruction32(Insn, 7, 1);
3467 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3468 align = 4;
3469 }
3470
3471 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3473 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3476 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3477 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3478 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3479 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3481 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3482 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3483 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484 }
3485
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3487 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3488 Inst.addOperand(MCOperand::CreateImm(index));
3489
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3490 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491}
3492
3493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3494static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3495 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3496 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3497
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3498 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3499 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3500 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3501 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3502 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3503
3504 unsigned align = 0;
3505 unsigned index = 0;
3506 unsigned inc = 1;
3507 switch (size) {
3508 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3509 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3510 case 0:
3511 index = fieldFromInstruction32(Insn, 5, 3);
3512 if (fieldFromInstruction32(Insn, 4, 1))
3513 align = 2;
3514 break;
3515 case 1:
3516 index = fieldFromInstruction32(Insn, 6, 2);
3517 if (fieldFromInstruction32(Insn, 4, 1))
3518 align = 4;
3519 if (fieldFromInstruction32(Insn, 5, 1))
3520 inc = 2;
3521 break;
3522 case 2:
3523 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3524 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3525 index = fieldFromInstruction32(Insn, 7, 1);
3526 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3527 align = 8;
3528 if (fieldFromInstruction32(Insn, 6, 1))
3529 inc = 2;
3530 break;
3531 }
3532
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3534 return MCDisassembler::Fail;
3535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3536 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3537 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3539 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3540 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3542 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3543 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3544 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3545 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3547 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3548 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3549 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3550 }
3551
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3553 return MCDisassembler::Fail;
3554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3555 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3556 Inst.addOperand(MCOperand::CreateImm(index));
3557
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3558 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3559}
3560
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3561static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3562 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3563 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3564
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3565 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3566 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3567 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3568 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3569 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3570
3571 unsigned align = 0;
3572 unsigned index = 0;
3573 unsigned inc = 1;
3574 switch (size) {
3575 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3576 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3577 case 0:
3578 index = fieldFromInstruction32(Insn, 5, 3);
3579 if (fieldFromInstruction32(Insn, 4, 1))
3580 align = 2;
3581 break;
3582 case 1:
3583 index = fieldFromInstruction32(Insn, 6, 2);
3584 if (fieldFromInstruction32(Insn, 4, 1))
3585 align = 4;
3586 if (fieldFromInstruction32(Insn, 5, 1))
3587 inc = 2;
3588 break;
3589 case 2:
3590 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3591 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3592 index = fieldFromInstruction32(Insn, 7, 1);
3593 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3594 align = 8;
3595 if (fieldFromInstruction32(Insn, 6, 1))
3596 inc = 2;
3597 break;
3598 }
3599
3600 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3602 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3603 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3605 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3606 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3607 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3608 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3610 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3611 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3612 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3613 }
3614
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3616 return MCDisassembler::Fail;
3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3618 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3619 Inst.addOperand(MCOperand::CreateImm(index));
3620
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3621 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622}
3623
3624
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3625static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3626 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3627 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3628
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3629 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3630 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3631 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3632 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3633 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3634
3635 unsigned align = 0;
3636 unsigned index = 0;
3637 unsigned inc = 1;
3638 switch (size) {
3639 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3640 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3641 case 0:
3642 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3643 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3644 index = fieldFromInstruction32(Insn, 5, 3);
3645 break;
3646 case 1:
3647 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3648 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3649 index = fieldFromInstruction32(Insn, 6, 2);
3650 if (fieldFromInstruction32(Insn, 5, 1))
3651 inc = 2;
3652 break;
3653 case 2:
3654 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3655 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3656 index = fieldFromInstruction32(Insn, 7, 1);
3657 if (fieldFromInstruction32(Insn, 6, 1))
3658 inc = 2;
3659 break;
3660 }
3661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3663 return MCDisassembler::Fail;
3664 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3665 return MCDisassembler::Fail;
3666 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3667 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668
3669 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3671 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3672 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3674 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3675 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3676 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3677 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3679 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3680 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3681 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3682 }
3683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3684 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3685 return MCDisassembler::Fail;
3686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3687 return MCDisassembler::Fail;
3688 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3689 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3690 Inst.addOperand(MCOperand::CreateImm(index));
3691
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3692 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3693}
3694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3695static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3696 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3697 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3698
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3699 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3700 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3701 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3702 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3703 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3704
3705 unsigned align = 0;
3706 unsigned index = 0;
3707 unsigned inc = 1;
3708 switch (size) {
3709 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3710 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3711 case 0:
3712 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3713 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3714 index = fieldFromInstruction32(Insn, 5, 3);
3715 break;
3716 case 1:
3717 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3719 index = fieldFromInstruction32(Insn, 6, 2);
3720 if (fieldFromInstruction32(Insn, 5, 1))
3721 inc = 2;
3722 break;
3723 case 2:
3724 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3725 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3726 index = fieldFromInstruction32(Insn, 7, 1);
3727 if (fieldFromInstruction32(Insn, 6, 1))
3728 inc = 2;
3729 break;
3730 }
3731
3732 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3734 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3735 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3737 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3738 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3739 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3740 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3742 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3743 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3744 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3745 }
3746
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3748 return MCDisassembler::Fail;
3749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3750 return MCDisassembler::Fail;
3751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3752 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3753 Inst.addOperand(MCOperand::CreateImm(index));
3754
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3755 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3756}
3757
3758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3759static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3760 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3761 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3762
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3763 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3764 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3765 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3766 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3767 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3768
3769 unsigned align = 0;
3770 unsigned index = 0;
3771 unsigned inc = 1;
3772 switch (size) {
3773 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3774 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3775 case 0:
3776 if (fieldFromInstruction32(Insn, 4, 1))
3777 align = 4;
3778 index = fieldFromInstruction32(Insn, 5, 3);
3779 break;
3780 case 1:
3781 if (fieldFromInstruction32(Insn, 4, 1))
3782 align = 8;
3783 index = fieldFromInstruction32(Insn, 6, 2);
3784 if (fieldFromInstruction32(Insn, 5, 1))
3785 inc = 2;
3786 break;
3787 case 2:
3788 if (fieldFromInstruction32(Insn, 4, 2))
3789 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3790 index = fieldFromInstruction32(Insn, 7, 1);
3791 if (fieldFromInstruction32(Insn, 6, 1))
3792 inc = 2;
3793 break;
3794 }
3795
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3797 return MCDisassembler::Fail;
3798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3799 return MCDisassembler::Fail;
3800 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3803 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3804
3805 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3807 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3808 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3810 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3811 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3812 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3813 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3815 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3816 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3817 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3818 }
3819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3821 return MCDisassembler::Fail;
3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3823 return MCDisassembler::Fail;
3824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3825 return MCDisassembler::Fail;
3826 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3827 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3828 Inst.addOperand(MCOperand::CreateImm(index));
3829
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3830 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831}
3832
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3833static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3834 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3835 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3836
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3837 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3838 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3839 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3840 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3841 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3842
3843 unsigned align = 0;
3844 unsigned index = 0;
3845 unsigned inc = 1;
3846 switch (size) {
3847 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3848 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3849 case 0:
3850 if (fieldFromInstruction32(Insn, 4, 1))
3851 align = 4;
3852 index = fieldFromInstruction32(Insn, 5, 3);
3853 break;
3854 case 1:
3855 if (fieldFromInstruction32(Insn, 4, 1))
3856 align = 8;
3857 index = fieldFromInstruction32(Insn, 6, 2);
3858 if (fieldFromInstruction32(Insn, 5, 1))
3859 inc = 2;
3860 break;
3861 case 2:
3862 if (fieldFromInstruction32(Insn, 4, 2))
3863 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3864 index = fieldFromInstruction32(Insn, 7, 1);
3865 if (fieldFromInstruction32(Insn, 6, 1))
3866 inc = 2;
3867 break;
3868 }
3869
3870 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3872 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3873 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3875 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3876 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3877 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3878 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3880 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3881 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3882 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3883 }
3884
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3886 return MCDisassembler::Fail;
3887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3888 return MCDisassembler::Fail;
3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3890 return MCDisassembler::Fail;
3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3892 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3893 Inst.addOperand(MCOperand::CreateImm(index));
3894
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3895 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3896}
3897
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3898static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3899 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3900 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3901 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3902 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3903 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3904 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3905 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3906
3907 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3908 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3910 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3911 return MCDisassembler::Fail;
3912 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3915 return MCDisassembler::Fail;
3916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3917 return MCDisassembler::Fail;
3918 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3919 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3920
3921 return S;
3922}
3923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3924static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3925 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3926 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3927 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3928 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3929 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3930 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3931 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3932
3933 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3934 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3937 return MCDisassembler::Fail;
3938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3939 return MCDisassembler::Fail;
3940 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3941 return MCDisassembler::Fail;
3942 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3943 return MCDisassembler::Fail;
3944 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3945 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3946
3947 return S;
3948}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3949
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3950static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3951 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3952 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3953 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3954 // The InstPrinter needs to have the low bit of the predicate in
3955 // the mask operand to be able to print it properly.
3956 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3957
3958 if (pred == 0xF) {
3959 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3960 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3961 }
3962
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3963 if ((mask & 0xF) == 0) {
3964 // Preserve the high bit of the mask, which is the low bit of
3965 // the predicate.
3966 mask &= 0x10;
3967 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3968 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3969 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3970
3971 Inst.addOperand(MCOperand::CreateImm(pred));
3972 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3973 return S;
3974}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3975
3976static DecodeStatus
3977DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3978 uint64_t Address, const void *Decoder) {
3979 DecodeStatus S = MCDisassembler::Success;
3980
3981 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3982 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3983 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3984 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3985 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3986 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3987 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3988 bool writeback = (W == 1) | (P == 0);
3989
3990 addr |= (U << 8) | (Rn << 9);
3991
3992 if (writeback && (Rn == Rt || Rn == Rt2))
3993 Check(S, MCDisassembler::SoftFail);
3994 if (Rt == Rt2)
3995 Check(S, MCDisassembler::SoftFail);
3996
3997 // Rt
3998 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3999 return MCDisassembler::Fail;
4000 // Rt2
4001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4002 return MCDisassembler::Fail;
4003 // Writeback operand
4004 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4005 return MCDisassembler::Fail;
4006 // addr
4007 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009
4010 return S;
4011}
4012
4013static DecodeStatus
4014DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4015 uint64_t Address, const void *Decoder) {
4016 DecodeStatus S = MCDisassembler::Success;
4017
4018 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4019 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4020 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4021 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4022 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4023 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4024 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4025 bool writeback = (W == 1) | (P == 0);
4026
4027 addr |= (U << 8) | (Rn << 9);
4028
4029 if (writeback && (Rn == Rt || Rn == Rt2))
4030 Check(S, MCDisassembler::SoftFail);
4031
4032 // Writeback operand
4033 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4034 return MCDisassembler::Fail;
4035 // Rt
4036 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4037 return MCDisassembler::Fail;
4038 // Rt2
4039 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4040 return MCDisassembler::Fail;
4041 // addr
4042 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4043 return MCDisassembler::Fail;
4044
4045 return S;
4046}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4047
4048static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4049 uint64_t Address, const void *Decoder) {
4050 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4051 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4052 if (sign1 != sign2) return MCDisassembler::Fail;
4053
4054 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4055 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4056 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4057 Val |= sign1 << 12;
4058 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4059
4060 return MCDisassembler::Success;
4061}
4062
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4063static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4064 uint64_t Address,
4065 const void *Decoder) {
4066 DecodeStatus S = MCDisassembler::Success;
4067
4068 // Shift of "asr #32" is not allowed in Thumb2 mode.
4069 if (Val == 0x20) S = MCDisassembler::SoftFail;
4070 Inst.addOperand(MCOperand::CreateImm(Val));
4071 return S;
4072}
4073
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4074static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4075 uint64_t Address, const void *Decoder) {
4076 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4077 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4078 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4079 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4080
4081 if (pred == 0xF)
4082 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4083
4084 DecodeStatus S = MCDisassembler::Success;
4085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4086 return MCDisassembler::Fail;
4087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4088 return MCDisassembler::Fail;
4089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4090 return MCDisassembler::Fail;
4091 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4092 return MCDisassembler::Fail;
4093
4094 return S;
4095}