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gerrit-public.fairphone.software / platform / external / llvm / e3ee49fb2728dcb9702b5be0c3c80f472ffccefc / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 77aa0073e7027e07832222549549eebec093cfe2 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame^]28#include "llvm/ADT/BitVector.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]29#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]30#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]31#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]32#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]33#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]34using namespace llvm;
35
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]36/// We are in the process of implementing a new TypeLegalization action
37/// - the promotion of vector elements. This feature is disabled by default
38/// and only enabled using this flag.
39static cl::opt<bool>
Nadav Rotem8fb06b32011-10-16 20:31:33 +0000[diff] [blame]40AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]41 cl::desc("Allow promotion of integer vector element types"));
42
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]43/// InitLibcallNames - Set default libcall names.
44///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]45static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]46 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]47 Names[RTLIB::SHL_I32] = "__ashlsi3";
48 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]49 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]50 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]51 Names[RTLIB::SRL_I32] = "__lshrsi3";
52 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]53 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]54 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]55 Names[RTLIB::SRA_I32] = "__ashrsi3";
56 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]57 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]58 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]59 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]60 Names[RTLIB::MUL_I32] = "__mulsi3";
61 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]62 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]63 Names[RTLIB::MULO_I32] = "__mulosi4";
64 Names[RTLIB::MULO_I64] = "__mulodi4";
65 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]66 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]67 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]68 Names[RTLIB::SDIV_I32] = "__divsi3";
69 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]70 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]71 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]72 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]73 Names[RTLIB::UDIV_I32] = "__udivsi3";
74 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]75 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]76 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]77 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]78 Names[RTLIB::SREM_I32] = "__modsi3";
79 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]80 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]81 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]82 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]83 Names[RTLIB::UREM_I32] = "__umodsi3";
84 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]85 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]86
87 // These are generally not available.
88 Names[RTLIB::SDIVREM_I8] = 0;
89 Names[RTLIB::SDIVREM_I16] = 0;
90 Names[RTLIB::SDIVREM_I32] = 0;
91 Names[RTLIB::SDIVREM_I64] = 0;
92 Names[RTLIB::SDIVREM_I128] = 0;
93 Names[RTLIB::UDIVREM_I8] = 0;
94 Names[RTLIB::UDIVREM_I16] = 0;
95 Names[RTLIB::UDIVREM_I32] = 0;
96 Names[RTLIB::UDIVREM_I64] = 0;
97 Names[RTLIB::UDIVREM_I128] = 0;
98
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]99 Names[RTLIB::NEG_I32] = "__negsi2";
100 Names[RTLIB::NEG_I64] = "__negdi2";
101 Names[RTLIB::ADD_F32] = "__addsf3";
102 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]103 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]104 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]105 Names[RTLIB::SUB_F32] = "__subsf3";
106 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]107 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::MUL_F32] = "__mulsf3";
110 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]113 Names[RTLIB::DIV_F32] = "__divsf3";
114 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]115 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]116 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]117 Names[RTLIB::REM_F32] = "fmodf";
118 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]119 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]120 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]121 Names[RTLIB::FMA_F32] = "fmaf";
122 Names[RTLIB::FMA_F64] = "fma";
123 Names[RTLIB::FMA_F80] = "fmal";
124 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]125 Names[RTLIB::POWI_F32] = "__powisf2";
126 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]127 Names[RTLIB::POWI_F80] = "__powixf2";
128 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]129 Names[RTLIB::SQRT_F32] = "sqrtf";
130 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]131 Names[RTLIB::SQRT_F80] = "sqrtl";
132 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]133 Names[RTLIB::LOG_F32] = "logf";
134 Names[RTLIB::LOG_F64] = "log";
135 Names[RTLIB::LOG_F80] = "logl";
136 Names[RTLIB::LOG_PPCF128] = "logl";
137 Names[RTLIB::LOG2_F32] = "log2f";
138 Names[RTLIB::LOG2_F64] = "log2";
139 Names[RTLIB::LOG2_F80] = "log2l";
140 Names[RTLIB::LOG2_PPCF128] = "log2l";
141 Names[RTLIB::LOG10_F32] = "log10f";
142 Names[RTLIB::LOG10_F64] = "log10";
143 Names[RTLIB::LOG10_F80] = "log10l";
144 Names[RTLIB::LOG10_PPCF128] = "log10l";
145 Names[RTLIB::EXP_F32] = "expf";
146 Names[RTLIB::EXP_F64] = "exp";
147 Names[RTLIB::EXP_F80] = "expl";
148 Names[RTLIB::EXP_PPCF128] = "expl";
149 Names[RTLIB::EXP2_F32] = "exp2f";
150 Names[RTLIB::EXP2_F64] = "exp2";
151 Names[RTLIB::EXP2_F80] = "exp2l";
152 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]153 Names[RTLIB::SIN_F32] = "sinf";
154 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]155 Names[RTLIB::SIN_F80] = "sinl";
156 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]157 Names[RTLIB::COS_F32] = "cosf";
158 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]159 Names[RTLIB::COS_F80] = "cosl";
160 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]161 Names[RTLIB::POW_F32] = "powf";
162 Names[RTLIB::POW_F64] = "pow";
163 Names[RTLIB::POW_F80] = "powl";
164 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]165 Names[RTLIB::CEIL_F32] = "ceilf";
166 Names[RTLIB::CEIL_F64] = "ceil";
167 Names[RTLIB::CEIL_F80] = "ceill";
168 Names[RTLIB::CEIL_PPCF128] = "ceill";
169 Names[RTLIB::TRUNC_F32] = "truncf";
170 Names[RTLIB::TRUNC_F64] = "trunc";
171 Names[RTLIB::TRUNC_F80] = "truncl";
172 Names[RTLIB::TRUNC_PPCF128] = "truncl";
173 Names[RTLIB::RINT_F32] = "rintf";
174 Names[RTLIB::RINT_F64] = "rint";
175 Names[RTLIB::RINT_F80] = "rintl";
176 Names[RTLIB::RINT_PPCF128] = "rintl";
177 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
178 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
179 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
180 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
181 Names[RTLIB::FLOOR_F32] = "floorf";
182 Names[RTLIB::FLOOR_F64] = "floor";
183 Names[RTLIB::FLOOR_F80] = "floorl";
184 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]185 Names[RTLIB::COPYSIGN_F32] = "copysignf";
186 Names[RTLIB::COPYSIGN_F64] = "copysign";
187 Names[RTLIB::COPYSIGN_F80] = "copysignl";
188 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]189 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]190 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
191 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]192 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]193 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
194 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
195 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
196 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]197 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
198 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
200 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
203 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
205 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]206 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]207 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]208 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]209 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]210 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]211 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]212 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]213 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
214 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
216 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
219 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
221 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]222 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]223 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
224 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]225 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]226 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]228 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]229 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
230 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]231 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
232 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]233 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
234 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]235 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
236 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]237 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
238 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
239 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
240 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]241 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
242 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]243 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
244 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]245 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
246 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]247 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
248 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
249 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
250 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
251 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
252 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]253 Names[RTLIB::OEQ_F32] = "__eqsf2";
254 Names[RTLIB::OEQ_F64] = "__eqdf2";
255 Names[RTLIB::UNE_F32] = "__nesf2";
256 Names[RTLIB::UNE_F64] = "__nedf2";
257 Names[RTLIB::OGE_F32] = "__gesf2";
258 Names[RTLIB::OGE_F64] = "__gedf2";
259 Names[RTLIB::OLT_F32] = "__ltsf2";
260 Names[RTLIB::OLT_F64] = "__ltdf2";
261 Names[RTLIB::OLE_F32] = "__lesf2";
262 Names[RTLIB::OLE_F64] = "__ledf2";
263 Names[RTLIB::OGT_F32] = "__gtsf2";
264 Names[RTLIB::OGT_F64] = "__gtdf2";
265 Names[RTLIB::UO_F32] = "__unordsf2";
266 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]267 Names[RTLIB::O_F32] = "__unordsf2";
268 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]269 Names[RTLIB::MEMCPY] = "memcpy";
270 Names[RTLIB::MEMMOVE] = "memmove";
271 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]272 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
276 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
280 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]281 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
282 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
283 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
284 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
285 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
286 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
287 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
288 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
289 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
290 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
291 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
292 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
293 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
294 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
295 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
296 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
297 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
298 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]299 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]300 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
301 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
302 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
303 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
304 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]305}
306
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]307/// InitLibcallCallingConvs - Set default libcall CallingConvs.
308///
309static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
310 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
311 CCs[i] = CallingConv::C;
312 }
313}
314
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]315/// getFPEXT - Return the FPEXT_*_* value for the given types, or
316/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]317RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]318 if (OpVT == MVT::f32) {
319 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]320 return FPEXT_F32_F64;
321 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]322
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]323 return UNKNOWN_LIBCALL;
324}
325
326/// getFPROUND - Return the FPROUND_*_* value for the given types, or
327/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]328RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]329 if (RetVT == MVT::f32) {
330 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]331 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]332 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]333 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]334 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]335 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]336 } else if (RetVT == MVT::f64) {
337 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]338 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]339 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]340 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]341 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]342
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]343 return UNKNOWN_LIBCALL;
344}
345
346/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
347/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]348RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]349 if (OpVT == MVT::f32) {
350 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]351 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]352 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]353 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]354 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]355 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]356 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]357 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]358 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]359 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]361 if (RetVT == MVT::i8)
362 return FPTOSINT_F64_I8;
363 if (RetVT == MVT::i16)
364 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]365 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]366 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]367 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]368 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]369 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]370 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]371 } else if (OpVT == MVT::f80) {
372 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]373 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]374 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]375 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]376 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]377 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]378 } else if (OpVT == MVT::ppcf128) {
379 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]380 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]381 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]382 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]383 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]384 return FPTOSINT_PPCF128_I128;
385 }
386 return UNKNOWN_LIBCALL;
387}
388
389/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
390/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]391RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 if (OpVT == MVT::f32) {
393 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]394 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]396 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]397 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]398 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]399 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]400 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]401 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]402 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]403 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]404 if (RetVT == MVT::i8)
405 return FPTOUINT_F64_I8;
406 if (RetVT == MVT::i16)
407 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]408 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]409 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]410 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]411 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]412 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]413 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]416 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]417 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]418 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]419 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]420 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]421 } else if (OpVT == MVT::ppcf128) {
422 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]423 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]424 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]425 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]426 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]427 return FPTOUINT_PPCF128_I128;
428 }
429 return UNKNOWN_LIBCALL;
430}
431
432/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
433/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]434RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 if (OpVT == MVT::i32) {
436 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]443 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]444 } else if (OpVT == MVT::i64) {
445 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]449 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]450 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]451 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]452 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]453 } else if (OpVT == MVT::i128) {
454 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]455 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]456 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]457 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]458 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]459 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]460 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]461 return SINTTOFP_I128_PPCF128;
462 }
463 return UNKNOWN_LIBCALL;
464}
465
466/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
467/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]468RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]469 if (OpVT == MVT::i32) {
470 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]475 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]476 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]477 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]478 } else if (OpVT == MVT::i64) {
479 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]480 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]481 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]483 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]484 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]485 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]486 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]487 } else if (OpVT == MVT::i128) {
488 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]489 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]490 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]491 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]492 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]493 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]494 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]495 return UINTTOFP_I128_PPCF128;
496 }
497 return UNKNOWN_LIBCALL;
498}
499
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]500/// InitCmpLibcallCCs - Set default comparison libcall CC.
501///
502static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
503 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
504 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
505 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
506 CCs[RTLIB::UNE_F32] = ISD::SETNE;
507 CCs[RTLIB::UNE_F64] = ISD::SETNE;
508 CCs[RTLIB::OGE_F32] = ISD::SETGE;
509 CCs[RTLIB::OGE_F64] = ISD::SETGE;
510 CCs[RTLIB::OLT_F32] = ISD::SETLT;
511 CCs[RTLIB::OLT_F64] = ISD::SETLT;
512 CCs[RTLIB::OLE_F32] = ISD::SETLE;
513 CCs[RTLIB::OLE_F64] = ISD::SETLE;
514 CCs[RTLIB::OGT_F32] = ISD::SETGT;
515 CCs[RTLIB::OGT_F64] = ISD::SETGT;
516 CCs[RTLIB::UO_F32] = ISD::SETNE;
517 CCs[RTLIB::UO_F64] = ISD::SETNE;
518 CCs[RTLIB::O_F32] = ISD::SETEQ;
519 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]520}
521
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]522/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]523TargetLowering::TargetLowering(const TargetMachine &tm,
524 const TargetLoweringObjectFile *tlof)
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]525 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
526 mayPromoteElements(AllowPromoteIntElem) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]527 // All operations default to being supported.
528 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]529 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]530 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]531 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]532 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]533
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]534 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]535 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]536 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]537 for (unsigned IM = (unsigned)ISD::PRE_INC;
538 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]539 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
540 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]541 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]542
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]543 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]544 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]546 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]547
548 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]549 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]550
551 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]552 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]553 // to optimize expansions for certain constants.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]554 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]555 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
556 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
557 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]558
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]559 // These library functions default to expand.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]560 setOperationAction(ISD::FLOG , MVT::f16, Expand);
561 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
562 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
563 setOperationAction(ISD::FEXP , MVT::f16, Expand);
564 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
565 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
566 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
567 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
568 setOperationAction(ISD::FRINT, MVT::f16, Expand);
569 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]570 setOperationAction(ISD::FLOG , MVT::f32, Expand);
571 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
572 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
573 setOperationAction(ISD::FEXP , MVT::f32, Expand);
574 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
575 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
576 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
577 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
578 setOperationAction(ISD::FRINT, MVT::f32, Expand);
579 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]580 setOperationAction(ISD::FLOG , MVT::f64, Expand);
581 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
582 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
583 setOperationAction(ISD::FEXP , MVT::f64, Expand);
584 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
585 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
586 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
587 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
588 setOperationAction(ISD::FRINT, MVT::f64, Expand);
589 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]590
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]591 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]592 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]593
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]594 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]595 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]596 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]597 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]598 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]599 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
600 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]601 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]602 UseUnderscoreSetJmp = false;
603 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]604 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]605 IntDivIsCheap = false;
606 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]607 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]608 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]609 ExceptionPointerRegister = 0;
610 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]611 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]612 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]613 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]614 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]615 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]616 MinFunctionAlignment = 0;
617 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]618 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]619 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]620 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]621 InsertFencesForAtomic = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]622
623 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]624 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]625 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]626}
627
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]628TargetLowering::~TargetLowering() {
629 delete &TLOF;
630}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]631
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]632MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
633 return MVT::getIntegerVT(8*TD->getPointerSize());
634}
635
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]636/// canOpTrap - Returns true if the operation can trap for the value type.
637/// VT must be a legal type.
638bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
639 assert(isTypeLegal(VT));
640 switch (Op) {
641 default:
642 return false;
643 case ISD::FDIV:
644 case ISD::FREM:
645 case ISD::SDIV:
646 case ISD::UDIV:
647 case ISD::SREM:
648 case ISD::UREM:
649 return true;
650 }
651}
652
653
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]654static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]655 unsigned &NumIntermediates,
656 EVT &RegisterVT,
657 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]658 // Figure out the right, legal destination reg to copy into.
659 unsigned NumElts = VT.getVectorNumElements();
660 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]661
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]662 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]663
664 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]665 // could break down into LHS/RHS like LegalizeDAG does.
666 if (!isPowerOf2_32(NumElts)) {
667 NumVectorRegs = NumElts;
668 NumElts = 1;
669 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]670
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]671 // Divide the input until we get to a supported size. This will always
672 // end with a scalar if the target doesn't support vectors.
673 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
674 NumElts >>= 1;
675 NumVectorRegs <<= 1;
676 }
677
678 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]679
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]680 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
681 if (!TLI->isTypeLegal(NewVT))
682 NewVT = EltTy;
683 IntermediateVT = NewVT;
684
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]685 unsigned NewVTSize = NewVT.getSizeInBits();
686
687 // Convert sizes such as i33 to i64.
688 if (!isPowerOf2_32(NewVTSize))
689 NewVTSize = NextPowerOf2(NewVTSize);
690
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]691 EVT DestVT = TLI->getRegisterType(NewVT);
692 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]695
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]696 // Otherwise, promotion or legal types use the same number of registers as
697 // the vector decimated to the appropriate level.
698 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]699}
700
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]701/// isLegalRC - Return true if the value types that can be represented by the
702/// specified register class are all legal.
703bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
704 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
705 I != E; ++I) {
706 if (isTypeLegal(*I))
707 return true;
708 }
709 return false;
710}
711
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]712/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]713/// of the register class for the specified type and its associated "cost".
714std::pair<const TargetRegisterClass*, uint8_t>
715TargetLowering::findRepresentativeClass(EVT VT) const {
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame^]716 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]717 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
718 if (!RC)
719 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]720
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame^]721 // Compute the set of all super-register classes.
722 // Include direct sub-classes of RC in case there are no super-registers.
723 BitVector SuperRegRC(TRI->getNumRegClasses());
724 for (SuperRegClassIterator RCI(RC, TRI, true); RCI.isValid(); ++RCI)
725 SuperRegRC.setBitsInMask(RCI.getMask());
726
727 // Find the first legal register class in the set.
728 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
729 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
730 if (isLegalRC(SuperRC))
731 return std::make_pair(SuperRC, 1);
732 }
733 llvm_unreachable("Inconsistent register class tables.");
734}
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]735
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]736/// computeRegisterProperties - Once all of the register classes are added,
737/// this allows us to compute derived properties we expose.
738void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]739 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]740 "Too many value types for ValueTypeActions to hold!");
741
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]742 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]743 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]744 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]745 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]746 }
747 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]748 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]749
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]750 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]751 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]752 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]753 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]754
755 // Every integer value type larger than this largest register takes twice as
756 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]757 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]758 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
759 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]760 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]761 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]762 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
763 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]764 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]765 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]766
767 // Inspect all of the ValueType's smaller than the largest integer
768 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]769 unsigned LegalIntReg = LargestIntReg;
770 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]771 IntReg >= (unsigned)MVT::i1; --IntReg) {
772 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]773 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]774 LegalIntReg = IntReg;
775 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]776 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]777 (MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]778 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]779 }
780 }
781
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]782 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]783 if (!isTypeLegal(MVT::ppcf128)) {
784 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
785 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
786 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]787 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]788 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]789
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]790 // Decide how to handle f64. If the target does not have native f64 support,
791 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]792 if (!isTypeLegal(MVT::f64)) {
793 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
794 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
795 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]796 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]797 }
798
799 // Decide how to handle f32. If the target does not have native support for
800 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]801 if (!isTypeLegal(MVT::f32)) {
802 if (isTypeLegal(MVT::f64)) {
803 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
804 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
805 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]806 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]807 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]808 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
809 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
810 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]811 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]812 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]813 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]814
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]815 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]816 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
817 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]818 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]819 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]820
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]821 // Determine if there is a legal wider type. If so, we should promote to
822 // that wider vector type.
823 EVT EltVT = VT.getVectorElementType();
824 unsigned NElts = VT.getVectorNumElements();
825 if (NElts != 1) {
826 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]827 // If we allow the promotion of vector elements using a flag,
828 // then return TypePromoteInteger on vector elements.
829 // First try to promote the elements of integer vectors. If no legal
830 // promotion was found, fallback to the widen-vector method.
831 if (mayPromoteElements)
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]832 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
833 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]834 // Promote vectors of integers to vectors with the same number
835 // of elements, with a wider element type.
836 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
837 && SVT.getVectorNumElements() == NElts &&
838 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
839 TransformToType[i] = SVT;
840 RegisterTypeForVT[i] = SVT;
841 NumRegistersForVT[i] = 1;
842 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
843 IsLegalWiderType = true;
844 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]845 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]846 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]847
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]848 if (IsLegalWiderType) continue;
849
850 // Try to widen the vector.
851 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
852 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]853 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]854 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]855 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]856 TransformToType[i] = SVT;
857 RegisterTypeForVT[i] = SVT;
858 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]859 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]860 IsLegalWiderType = true;
861 break;
862 }
863 }
864 if (IsLegalWiderType) continue;
865 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]866
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]867 MVT IntermediateVT;
868 EVT RegisterVT;
869 unsigned NumIntermediates;
870 NumRegistersForVT[i] =
871 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
872 RegisterVT, this);
873 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]874
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]875 EVT NVT = VT.getPow2VectorType();
876 if (NVT == VT) {
877 // Type is already a power of 2. The default action is to split.
878 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]879 unsigned NumElts = VT.getVectorNumElements();
880 ValueTypeActions.setTypeAction(VT,
881 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]882 } else {
883 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]884 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]885 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]886 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]887
888 // Determine the 'representative' register class for each value type.
889 // An representative register class is the largest (meaning one which is
890 // not a sub-register class / subreg register class) legal register class for
891 // a group of value types. For example, on i386, i8, i16, and i32
892 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]893 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]894 const TargetRegisterClass* RRC;
895 uint8_t Cost;
896 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
897 RepRegClassForVT[i] = RRC;
898 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]899 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]900}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]901
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]902const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
903 return NULL;
904}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]905
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]906
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]907EVT TargetLowering::getSetCCResultType(EVT VT) const {
908 assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]909 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]910}
911
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]912MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
913 return MVT::i32; // return the default value
914}
915
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]916/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]917/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
918/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
919/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]920///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]921/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]922/// register. It also returns the VT and quantity of the intermediate values
923/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]924///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]925unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]926 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]927 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]928 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]929 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]930
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]931 // If there is a wider vector type with the same element type as this one,
Nadav Rotemdb346162012-04-21 20:08:32 +0000[diff] [blame]932 // or a promoted vector type that has the same number of elements which
933 // are wider, then we should convert to that legal vector type.
934 // This handles things like <2 x float> -> <4 x float> and
935 // <4 x i1> -> <4 x i32>.
936 LegalizeTypeAction TA = getTypeAction(Context, VT);
937 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]938 RegisterVT = getTypeToTransformTo(Context, VT);
939 if (isTypeLegal(RegisterVT)) {
940 IntermediateVT = RegisterVT;
941 NumIntermediates = 1;
942 return 1;
943 }
944 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]945
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]946 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]947 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]948
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]949 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]950
951 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]952 // could break down into LHS/RHS like LegalizeDAG does.
953 if (!isPowerOf2_32(NumElts)) {
954 NumVectorRegs = NumElts;
955 NumElts = 1;
956 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]957
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]958 // Divide the input until we get to a supported size. This will always
959 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]960 while (NumElts > 1 && !isTypeLegal(
961 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]962 NumElts >>= 1;
963 NumVectorRegs <<= 1;
964 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]965
966 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]967
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]968 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]969 if (!isTypeLegal(NewVT))
970 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]971 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]972
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]973 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]974 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]975 unsigned NewVTSize = NewVT.getSizeInBits();
976
977 // Convert sizes such as i33 to i64.
978 if (!isPowerOf2_32(NewVTSize))
979 NewVTSize = NextPowerOf2(NewVTSize);
980
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]981 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]982 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]983
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]984 // Otherwise, promotion or legal types use the same number of registers as
985 // the vector decimated to the appropriate level.
986 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]987}
988
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]989/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]990/// type of the given function. This does not require a DAG or a return value,
991/// and is suitable for use before any DAGs for the function are constructed.
992/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]993void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]994 SmallVectorImpl<ISD::OutputArg> &Outs,
995 const TargetLowering &TLI,
996 SmallVectorImpl<uint64_t> *Offsets) {
997 SmallVector<EVT, 4> ValueVTs;
998 ComputeValueVTs(TLI, ReturnType, ValueVTs);
999 unsigned NumValues = ValueVTs.size();
1000 if (NumValues == 0) return;
1001 unsigned Offset = 0;
1002
1003 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1004 EVT VT = ValueVTs[j];
1005 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1006
1007 if (attr & Attribute::SExt)
1008 ExtendKind = ISD::SIGN_EXTEND;
1009 else if (attr & Attribute::ZExt)
1010 ExtendKind = ISD::ZERO_EXTEND;
1011
1012 // FIXME: C calling convention requires the return type to be promoted to
1013 // at least 32-bit. But this is not necessary for non-C calling
1014 // conventions. The frontend should mark functions whose return values
1015 // require promoting with signext or zeroext attributes.
1016 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1017 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1018 if (VT.bitsLT(MinVT))
1019 VT = MinVT;
1020 }
1021
1022 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1023 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1024 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1025 PartVT.getTypeForEVT(ReturnType->getContext()));
1026
1027 // 'inreg' on function refers to return value
1028 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1029 if (attr & Attribute::InReg)
1030 Flags.setInReg();
1031
1032 // Propagate extension type if any
1033 if (attr & Attribute::SExt)
1034 Flags.setSExt();
1035 else if (attr & Attribute::ZExt)
1036 Flags.setZExt();
1037
1038 for (unsigned i = 0; i < NumParts; ++i) {
1039 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1040 if (Offsets) {
1041 Offsets->push_back(Offset);
1042 Offset += PartSize;
1043 }
1044 }
1045 }
1046}
1047
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1048/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1049/// function arguments in the caller parameter area. This is the actual
1050/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1051unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1052 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1053}
1054
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1055/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1056/// current function. The returned value is a member of the
1057/// MachineJumpTableInfo::JTEntryKind enum.
1058unsigned TargetLowering::getJumpTableEncoding() const {
1059 // In non-pic modes, just use the address of a block.
1060 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1061 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1062
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1063 // In PIC mode, if the target supports a GPRel32 directive, use it.
1064 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1065 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1066
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1067 // Otherwise, use a label difference.
1068 return MachineJumpTableInfo::EK_LabelDifference32;
1069}
1070
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1071SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1072 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1073 // If our PIC model is GP relative, use the global offset table as the base.
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1074 unsigned JTEncoding = getJumpTableEncoding();
1075
1076 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1077 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1078 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1079
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1080 return Table;
1081}
1082
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1083/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1084/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1085/// MCExpr.
1086const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1087TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1088 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1089 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1090 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1091}
1092
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1093bool
1094TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1095 // Assume that everything is safe in static mode.
1096 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1097 return true;
1098
1099 // In dynamic-no-pic mode, assume that known defined values are safe.
1100 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1101 GA &&
1102 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1103 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1104 return true;
1105
1106 // Otherwise assume nothing is safe.
1107 return false;
1108}
1109
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1110//===----------------------------------------------------------------------===//
1111// Optimization Methods
1112//===----------------------------------------------------------------------===//
1113
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1114/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1115/// specified instruction is a constant integer. If so, check to see if there
1116/// are any bits set in the constant that are not demanded. If so, shrink the
1117/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1118bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1119 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1120 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1121
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1122 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1123 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1124 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1125 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1126 case ISD::AND:
1127 case ISD::OR: {
1128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1129 if (!C) return false;
1130
1131 if (Op.getOpcode() == ISD::XOR &&
1132 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1133 return false;
1134
1135 // if we can expand it to have all bits set, do it
1136 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1137 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1138 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1139 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1140 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1141 VT));
1142 return CombineTo(Op, New);
1143 }
1144
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1145 break;
1146 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1147 }
1148
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1149 return false;
1150}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1151
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1152/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1153/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1154/// cast, but it could be generalized for targets with other types of
1155/// implicit widening casts.
1156bool
1157TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1158 unsigned BitWidth,
1159 const APInt &Demanded,
1160 DebugLoc dl) {
1161 assert(Op.getNumOperands() == 2 &&
1162 "ShrinkDemandedOp only supports binary operators!");
1163 assert(Op.getNode()->getNumValues() == 1 &&
1164 "ShrinkDemandedOp only supports nodes with one result!");
1165
1166 // Don't do this if the node has another user, which may require the
1167 // full value.
1168 if (!Op.getNode()->hasOneUse())
1169 return false;
1170
1171 // Search for the smallest integer type with free casts to and from
1172 // Op's type. For expedience, just check power-of-2 integer types.
1173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1174 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1175 if (!isPowerOf2_32(SmallVTBits))
1176 SmallVTBits = NextPowerOf2(SmallVTBits);
1177 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1178 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1179 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1180 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1181 // We found a type with free casts.
1182 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1183 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1184 Op.getNode()->getOperand(0)),
1185 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1186 Op.getNode()->getOperand(1)));
1187 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1188 return CombineTo(Op, Z);
1189 }
1190 }
1191 return false;
1192}
1193
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1194/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1195/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1196/// use this information to simplify Op, create a new simplified DAG node and
1197/// return true, returning the original and new nodes in Old and New. Otherwise,
1198/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1199/// the expression (used to simplify the caller). The KnownZero/One bits may
1200/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1201bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1202 const APInt &DemandedMask,
1203 APInt &KnownZero,
1204 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1205 TargetLoweringOpt &TLO,
1206 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1207 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1208 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1209 "Mask size mismatches value type size!");
1210 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1211 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1212
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1213 // Don't know anything.
1214 KnownZero = KnownOne = APInt(BitWidth, 0);
1215
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1216 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1217 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1218 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1219 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1220 // simplify things downstream.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1221 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222 return false;
1223 }
1224 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1225 // just set the NewMask to all bits.
1226 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1227 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1228 // Not demanding any bits from Op.
1229 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1230 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1231 return false;
1232 } else if (Depth == 6) { // Limit search depth.
1233 return false;
1234 }
1235
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1236 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1237 switch (Op.getOpcode()) {
1238 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1239 // We know all of the bits for a constant!
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1240 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1241 KnownZero = ~KnownOne;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1242 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1243 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1244 // If the RHS is a constant, check to see if the LHS would be zero without
1245 // using the bits from the RHS. Below, we use knowledge about the RHS to
1246 // simplify the LHS, here we're using information from the LHS to simplify
1247 // the RHS.
1248 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1249 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1250 // Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1251 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1252 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1253 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1254 return TLO.CombineTo(Op, Op.getOperand(0));
1255 // If any of the set bits in the RHS are known zero on the LHS, shrink
1256 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1257 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1258 return true;
1259 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1260
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1261 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1262 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1263 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1264 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1265 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1266 KnownZero2, KnownOne2, TLO, Depth+1))
1267 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1268 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1269
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1270 // If all of the demanded bits are known one on one side, return the other.
1271 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1272 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1273 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1274 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1275 return TLO.CombineTo(Op, Op.getOperand(1));
1276 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1277 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1278 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1279 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1280 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1281 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1282 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1283 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1284 return true;
1285
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1286 // Output known-1 bits are only known if set in both the LHS & RHS.
1287 KnownOne &= KnownOne2;
1288 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1289 KnownZero |= KnownZero2;
1290 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1291 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1292 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1293 KnownOne, TLO, Depth+1))
1294 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1295 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1296 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 KnownZero2, KnownOne2, TLO, Depth+1))
1298 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1299 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1300
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1301 // If all of the demanded bits are known zero on one side, return the other.
1302 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1303 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1304 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1305 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1306 return TLO.CombineTo(Op, Op.getOperand(1));
1307 // If all of the potentially set bits on one side are known to be set on
1308 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1309 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1310 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1311 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1312 return TLO.CombineTo(Op, Op.getOperand(1));
1313 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1314 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1315 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1316 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1317 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1318 return true;
1319
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1320 // Output known-0 bits are only known if clear in both the LHS & RHS.
1321 KnownZero &= KnownZero2;
1322 // Output known-1 are known to be set if set in either the LHS | RHS.
1323 KnownOne |= KnownOne2;
1324 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1325 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1326 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1327 KnownOne, TLO, Depth+1))
1328 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1329 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1330 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331 KnownOne2, TLO, Depth+1))
1332 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1333 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1334
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1335 // If all of the demanded bits are known zero on one side, return the other.
1336 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1337 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1338 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1339 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1340 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1341 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1342 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1343 return true;
1344
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1345 // If all of the unknown bits are known to be zero on one side or the other
1346 // (but not both) turn this into an *inclusive* or.
1347 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1348 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1349 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1350 Op.getOperand(0),
1351 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1352
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1353 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1354 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1355 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1356 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1357
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1358 // If all of the demanded bits on one side are known, and all of the set
1359 // bits on that side are also known to be set on the other side, turn this
1360 // into an AND, as we know the bits will be cleared.
1361 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Joel Jonesd16ce172012-04-17 22:23:10 +0000[diff] [blame]1362 // NB: it is okay if more bits are known than are requested
1363 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1364 if (KnownOne == KnownOne2) { // set bits are the same on both sides
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1365 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1366 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1367 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1368 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1369 }
1370 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1371
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1372 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1373 // for XOR, we prefer to force bits to 1 if they will make a -1.
1374 // if we can't force bits, try to shrink constant
1375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1376 APInt Expanded = C->getAPIntValue() | (~NewMask);
1377 // if we can expand it to have all bits set, do it
1378 if (Expanded.isAllOnesValue()) {
1379 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1380 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1381 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1382 TLO.DAG.getConstant(Expanded, VT));
1383 return TLO.CombineTo(Op, New);
1384 }
1385 // if it already has all the bits set, nothing to change
1386 // but don't shrink either!
1387 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1388 return true;
1389 }
1390 }
1391
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1392 KnownZero = KnownZeroOut;
1393 KnownOne = KnownOneOut;
1394 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1395 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1396 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1397 KnownOne, TLO, Depth+1))
1398 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1399 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1400 KnownOne2, TLO, Depth+1))
1401 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1402 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1403 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1404
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1405 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1406 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1407 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1408
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1409 // Only known if known in both the LHS and RHS.
1410 KnownOne &= KnownOne2;
1411 KnownZero &= KnownZero2;
1412 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1413 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1414 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1415 KnownOne, TLO, Depth+1))
1416 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1417 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1418 KnownOne2, TLO, Depth+1))
1419 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1422
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1423 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1424 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1425 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1426
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1427 // Only known if known in both the LHS and RHS.
1428 KnownOne &= KnownOne2;
1429 KnownZero &= KnownZero2;
1430 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1431 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1432 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1433 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1434 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1435
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1436 // If the shift count is an invalid immediate, don't do anything.
1437 if (ShAmt >= BitWidth)
1438 break;
1439
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1440 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1441 // single shift. We can do this if the bottom bits (which are shifted
1442 // out) are never demanded.
1443 if (InOp.getOpcode() == ISD::SRL &&
1444 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1445 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1446 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1447 unsigned Opc = ISD::SHL;
1448 int Diff = ShAmt-C1;
1449 if (Diff < 0) {
1450 Diff = -Diff;
1451 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1452 }
1453
1454 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1455 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1456 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1457 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1458 InOp.getOperand(0), NewSA));
1459 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1460 }
1461
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1462 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1463 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1464 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1465
1466 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1467 // are not demanded. This will likely allow the anyext to be folded away.
1468 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1469 SDValue InnerOp = InOp.getNode()->getOperand(0);
1470 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1471 unsigned InnerBits = InnerVT.getSizeInBits();
1472 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1473 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1474 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1475 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1476 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1477 SDValue NarrowShl =
1478 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1479 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1480 return
1481 TLO.CombineTo(Op,
1482 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1483 NarrowShl));
1484 }
1485 }
1486
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1487 KnownZero <<= SA->getZExtValue();
1488 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1489 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1490 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1491 }
1492 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1493 case ISD::SRL:
1494 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1495 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1496 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1497 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1498 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1499
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1500 // If the shift count is an invalid immediate, don't do anything.
1501 if (ShAmt >= BitWidth)
1502 break;
1503
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1504 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1505 // single shift. We can do this if the top bits (which are shifted out)
1506 // are never demanded.
1507 if (InOp.getOpcode() == ISD::SHL &&
1508 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1509 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1510 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1511 unsigned Opc = ISD::SRL;
1512 int Diff = ShAmt-C1;
1513 if (Diff < 0) {
1514 Diff = -Diff;
1515 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1516 }
1517
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1518 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1519 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1520 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1521 InOp.getOperand(0), NewSA));
1522 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1523 }
1524
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1525 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1526 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1527 KnownZero, KnownOne, TLO, Depth+1))
1528 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1529 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1530 KnownZero = KnownZero.lshr(ShAmt);
1531 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1532
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1533 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1534 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1535 }
1536 break;
1537 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1538 // If this is an arithmetic shift right and only the low-bit is set, we can
1539 // always convert this into a logical shr, even if the shift amount is
1540 // variable. The low bit of the shift cannot be an input sign bit unless
1541 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1542 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1543 return TLO.CombineTo(Op,
1544 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1545 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1546
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1547 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1548 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1549 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1550
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1551 // If the shift count is an invalid immediate, don't do anything.
1552 if (ShAmt >= BitWidth)
1553 break;
1554
1555 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1556
1557 // If any of the demanded bits are produced by the sign extension, we also
1558 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1559 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1560 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1561 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1562
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1563 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1564 KnownZero, KnownOne, TLO, Depth+1))
1565 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1566 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1567 KnownZero = KnownZero.lshr(ShAmt);
1568 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1569
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1570 // Handle the sign bit, adjusted to where it is now in the mask.
1571 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1572
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1573 // If the input sign bit is known to be zero, or if none of the top bits
1574 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1575 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1576 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1577 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1578 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1579 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1580 KnownOne |= HighBits;
1581 }
1582 }
1583 break;
1584 case ISD::SIGN_EXTEND_INREG: {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1585 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1586
1587 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1588 // If we only care about the highest bit, don't bother shifting right.
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1589 if (MsbMask == DemandedMask) {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1590 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1591 SDValue InOp = Op.getOperand(0);
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1592
1593 // Compute the correct shift amount type, which must be getShiftAmountTy
1594 // for scalar types after legalization.
1595 EVT ShiftAmtTy = Op.getValueType();
1596 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1597 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1598
1599 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1600 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1601 Op.getValueType(), InOp, ShiftAmt));
1602 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1603
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1604 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1605 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1606 APInt NewBits =
1607 APInt::getHighBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1608 BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1609
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1610 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1611 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1612 return TLO.CombineTo(Op, Op.getOperand(0));
1613
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1614 APInt InSignBit =
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1615 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1616 APInt InputDemandedBits =
1617 APInt::getLowBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1618 ExVT.getScalarType().getSizeInBits()) &
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1619 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1620
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1621 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1622 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1623 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1624
1625 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1626 KnownZero, KnownOne, TLO, Depth+1))
1627 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1628 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1629
1630 // If the sign bit of the input is known set or clear, then we know the
1631 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1632
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1633 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1634 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1635 return TLO.CombineTo(Op,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1636 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1637
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1638 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1639 KnownOne |= NewBits;
1640 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1641 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1642 KnownZero &= ~NewBits;
1643 KnownOne &= ~NewBits;
1644 }
1645 break;
1646 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1647 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1648 unsigned OperandBitWidth =
1649 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1650 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1651
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1652 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1653 APInt NewBits =
1654 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1655 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1656 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1657 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1658 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1659
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1660 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1661 KnownZero, KnownOne, TLO, Depth+1))
1662 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1663 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1664 KnownZero = KnownZero.zext(BitWidth);
1665 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1666 KnownZero |= NewBits;
1667 break;
1668 }
1669 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1670 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1671 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1672 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1673 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1674 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1675
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1676 // If none of the top bits are demanded, convert this into an any_extend.
1677 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1678 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1679 Op.getValueType(),
1680 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1681
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1682 // Since some of the sign extended bits are demanded, we know that the sign
1683 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1684 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1685 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1686 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1687
1688 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1689 KnownOne, TLO, Depth+1))
1690 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1691 KnownZero = KnownZero.zext(BitWidth);
1692 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1693
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1694 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1695 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1696 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1697 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1698 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1699
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1700 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1701 if (KnownOne.intersects(InSignBit)) {
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1702 KnownOne |= NewBits;
1703 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1704 } else { // Otherwise, top bits aren't known.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1705 assert((KnownOne & NewBits) == 0);
1706 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1707 }
1708 break;
1709 }
1710 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1711 unsigned OperandBitWidth =
1712 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1713 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1714 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1715 KnownZero, KnownOne, TLO, Depth+1))
1716 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1717 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1718 KnownZero = KnownZero.zext(BitWidth);
1719 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1720 break;
1721 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1722 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1723 // Simplify the input, using demanded bit information, and compute the known
1724 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1725 unsigned OperandBitWidth =
1726 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1727 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1728 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1729 KnownZero, KnownOne, TLO, Depth+1))
1730 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1731 KnownZero = KnownZero.trunc(BitWidth);
1732 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1733
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1734 // If the input is only used by this truncate, see if we can shrink it based
1735 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1736 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1737 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1738 switch (In.getOpcode()) {
1739 default: break;
1740 case ISD::SRL:
1741 // Shrink SRL by a constant if none of the high bits shifted in are
1742 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1743 if (TLO.LegalTypes() &&
1744 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1745 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1746 // undesirable.
1747 break;
1748 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1749 if (!ShAmt)
1750 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1751 SDValue Shift = In.getOperand(1);
1752 if (TLO.LegalTypes()) {
1753 uint64_t ShVal = ShAmt->getZExtValue();
1754 Shift =
1755 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1756 }
1757
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1758 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1759 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1760 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1761
1762 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1763 // None of the shifted in bits are needed. Add a truncate of the
1764 // shift input, then shift it.
1765 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1766 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1767 In.getOperand(0));
1768 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1769 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1770 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1771 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1772 }
1773 break;
1774 }
1775 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1776
1777 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1778 break;
1779 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1780 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1781 // AssertZext demands all of the high bits, plus any of the low bits
1782 // demanded by its users.
1783 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1784 APInt InMask = APInt::getLowBitsSet(BitWidth,
1785 VT.getSizeInBits());
1786 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1787 KnownZero, KnownOne, TLO, Depth+1))
1788 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1789 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1790
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1791 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1792 break;
1793 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1794 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1795 // If this is an FP->Int bitcast and if the sign bit is the only
1796 // thing demanded, turn this into a FGETSIGN.
Eli Friedmanca072a32011-12-15 02:07:20 +0000[diff] [blame]1797 if (!TLO.LegalOperations() &&
1798 !Op.getValueType().isVector() &&
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1799 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1800 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1801 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1802 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1803 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1804 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1805 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1806 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1807 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1808 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1809 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1810 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1811 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1812 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1813 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1814 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1815 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1816 Sign, ShAmt));
1817 }
1818 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1819 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1820 case ISD::ADD:
1821 case ISD::MUL:
1822 case ISD::SUB: {
1823 // Add, Sub, and Mul don't demand any bits in positions beyond that
1824 // of the highest bit demanded of them.
1825 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1826 BitWidth - NewMask.countLeadingZeros());
1827 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1828 KnownOne2, TLO, Depth+1))
1829 return true;
1830 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1831 KnownOne2, TLO, Depth+1))
1832 return true;
1833 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1834 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1835 return true;
1836 }
1837 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1838 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1839 // Just use ComputeMaskedBits to compute output bits.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1840 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1841 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1842 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1843
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1844 // If we know the value of all of the demanded bits, return this as a
1845 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1846 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1847 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1848
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1849 return false;
1850}
1851
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1852/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1853/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1854/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1855void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1856 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1857 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1858 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1859 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1860 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1861 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1862 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1863 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1864 "Should use MaskedValueIsZero if you don't know whether Op"
1865 " is a target node!");
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1866 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1867}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1868
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1869/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1870/// targets that want to expose additional information about sign bits to the
1871/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1872unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1873 unsigned Depth) const {
1874 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1875 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1876 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1877 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1878 "Should use ComputeNumSignBits if you don't know whether Op"
1879 " is a target node!");
1880 return 1;
1881}
1882
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1883/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1884/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1885/// determine which bit is set.
1886///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1887static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1888 // A left-shift of a constant one will have exactly one bit set, because
1889 // shifting the bit off the end is undefined.
1890 if (Val.getOpcode() == ISD::SHL)
1891 if (ConstantSDNode *C =
1892 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1893 if (C->getAPIntValue() == 1)
1894 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1895
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1896 // Similarly, a right-shift of a constant sign-bit will have exactly
1897 // one bit set.
1898 if (Val.getOpcode() == ISD::SRL)
1899 if (ConstantSDNode *C =
1900 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1901 if (C->getAPIntValue().isSignBit())
1902 return true;
1903
1904 // More could be done here, though the above checks are enough
1905 // to handle some common cases.
1906
1907 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1908 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1909 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1910 APInt KnownZero, KnownOne;
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1911 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1912 return (KnownZero.countPopulation() == BitWidth - 1) &&
1913 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1914}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1915
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1916/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1917/// and cc. If it is unable to simplify it, return a null SDValue.
1918SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1919TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1920 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1921 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1922 SelectionDAG &DAG = DCI.DAG;
1923
1924 // These setcc operations always fold.
1925 switch (Cond) {
1926 default: break;
1927 case ISD::SETFALSE:
1928 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1929 case ISD::SETTRUE:
1930 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1931 }
1932
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1933 // Ensure that the constant occurs on the RHS, and fold constant
1934 // comparisons.
1935 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1936 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1937
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1938 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1939 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1940
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1941 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1942 // equality comparison, then we're just comparing whether X itself is
1943 // zero.
1944 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1945 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1946 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1947 const APInt &ShAmt
1948 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1949 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1950 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1951 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1952 // (srl (ctlz x), 5) == 0 -> X != 0
1953 // (srl (ctlz x), 5) != 1 -> X != 0
1954 Cond = ISD::SETNE;
1955 } else {
1956 // (srl (ctlz x), 5) != 0 -> X == 0
1957 // (srl (ctlz x), 5) == 1 -> X == 0
1958 Cond = ISD::SETEQ;
1959 }
1960 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1961 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1962 Zero, Cond);
1963 }
1964 }
1965
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1966 SDValue CTPOP = N0;
1967 // Look through truncs that don't change the value of a ctpop.
1968 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1969 CTPOP = N0.getOperand(0);
1970
1971 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1972 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1973 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1974 EVT CTVT = CTPOP.getValueType();
1975 SDValue CTOp = CTPOP.getOperand(0);
1976
1977 // (ctpop x) u< 2 -> (x & x-1) == 0
1978 // (ctpop x) u> 1 -> (x & x-1) != 0
1979 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1980 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1981 DAG.getConstant(1, CTVT));
1982 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1983 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1984 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1985 }
1986
1987 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1988 }
1989
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]1990 // (zext x) == C --> x == (trunc C)
1991 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1992 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1993 unsigned MinBits = N0.getValueSizeInBits();
1994 SDValue PreZExt;
1995 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1996 // ZExt
1997 MinBits = N0->getOperand(0).getValueSizeInBits();
1998 PreZExt = N0->getOperand(0);
1999 } else if (N0->getOpcode() == ISD::AND) {
2000 // DAGCombine turns costly ZExts into ANDs
2001 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2002 if ((C->getAPIntValue()+1).isPowerOf2()) {
2003 MinBits = C->getAPIntValue().countTrailingOnes();
2004 PreZExt = N0->getOperand(0);
2005 }
2006 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2007 // ZEXTLOAD
2008 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2009 MinBits = LN0->getMemoryVT().getSizeInBits();
2010 PreZExt = N0;
2011 }
2012 }
2013
2014 // Make sure we're not loosing bits from the constant.
2015 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2016 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2017 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2018 // Will get folded away.
2019 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2020 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2021 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2022 }
2023 }
2024 }
2025
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2026 // If the LHS is '(and load, const)', the RHS is 0,
2027 // the test is for equality or unsigned, and all 1 bits of the const are
2028 // in the same partial word, see if we can shorten the load.
2029 if (DCI.isBeforeLegalize() &&
2030 N0.getOpcode() == ISD::AND && C1 == 0 &&
2031 N0.getNode()->hasOneUse() &&
2032 isa<LoadSDNode>(N0.getOperand(0)) &&
2033 N0.getOperand(0).getNode()->hasOneUse() &&
2034 isa<ConstantSDNode>(N0.getOperand(1))) {
2035 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2036 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2037 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2038 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2039 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2040 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2041 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2042 // 8 bits, but have to be careful...
2043 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2044 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2045 const APInt &Mask =
2046 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2047 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2048 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2049 for (unsigned offset=0; offset<origWidth/width; offset++) {
2050 if ((newMask & Mask) == Mask) {
2051 if (!TD->isLittleEndian())
2052 bestOffset = (origWidth/width - offset - 1) * (width/8);
2053 else
2054 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2055 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2056 bestWidth = width;
2057 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2058 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2059 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2060 }
2061 }
2062 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2063 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2064 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2065 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2066 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2067 SDValue Ptr = Lod->getBasePtr();
2068 if (bestOffset != 0)
2069 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2070 DAG.getConstant(bestOffset, PtrType));
2071 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2072 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2073 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2074 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2075 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2076 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2077 DAG.getConstant(bestMask.trunc(bestWidth),
2078 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2079 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2080 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2081 }
2082 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2083
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2084 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2085 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2086 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2087
2088 // If the comparison constant has bits in the upper part, the
2089 // zero-extended value could never match.
2090 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2091 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2092 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2093 case ISD::SETUGT:
2094 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2095 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2096 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2097 case ISD::SETULE:
2098 case ISD::SETNE: return DAG.getConstant(1, VT);
2099 case ISD::SETGT:
2100 case ISD::SETGE:
2101 // True if the sign bit of C1 is set.
2102 return DAG.getConstant(C1.isNegative(), VT);
2103 case ISD::SETLT:
2104 case ISD::SETLE:
2105 // True if the sign bit of C1 isn't set.
2106 return DAG.getConstant(C1.isNonNegative(), VT);
2107 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2108 break;
2109 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2110 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2111
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2112 // Otherwise, we can perform the comparison with the low bits.
2113 switch (Cond) {
2114 case ISD::SETEQ:
2115 case ISD::SETNE:
2116 case ISD::SETUGT:
2117 case ISD::SETUGE:
2118 case ISD::SETULT:
2119 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2120 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2121 if (DCI.isBeforeLegalizeOps() ||
2122 (isOperationLegal(ISD::SETCC, newVT) &&
2123 getCondCodeAction(Cond, newVT)==Legal))
2124 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2125 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2126 Cond);
2127 break;
2128 }
2129 default:
2130 break; // todo, be more careful with signed comparisons
2131 }
2132 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2133 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2134 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2135 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2136 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2137 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2138
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2139 // If the constant doesn't fit into the number of bits for the source of
2140 // the sign extension, it is impossible for both sides to be equal.
2141 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2142 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2143
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2144 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2145 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2146 if (Op0Ty == ExtSrcTy) {
2147 ZextOp = N0.getOperand(0);
2148 } else {
2149 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2150 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2151 DAG.getConstant(Imm, Op0Ty));
2152 }
2153 if (!DCI.isCalledByLegalizer())
2154 DCI.AddToWorklist(ZextOp.getNode());
2155 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2156 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2157 DAG.getConstant(C1 & APInt::getLowBitsSet(
2158 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2159 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2160 ExtDstTy),
2161 Cond);
2162 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2163 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2164 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2165 if (N0.getOpcode() == ISD::SETCC &&
2166 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2167 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2168 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2169 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2170 // Invert the condition.
2171 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2172 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2173 N0.getOperand(0).getValueType().isInteger());
2174 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2175 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2176
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2177 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2178 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2179 N0.getOperand(0).getOpcode() == ISD::XOR &&
2180 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2181 isa<ConstantSDNode>(N0.getOperand(1)) &&
2182 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2183 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2184 // can only do this if the top bits are known zero.
2185 unsigned BitWidth = N0.getValueSizeInBits();
2186 if (DAG.MaskedValueIsZero(N0,
2187 APInt::getHighBitsSet(BitWidth,
2188 BitWidth-1))) {
2189 // Okay, get the un-inverted input value.
2190 SDValue Val;
2191 if (N0.getOpcode() == ISD::XOR)
2192 Val = N0.getOperand(0);
2193 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2194 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2195 N0.getOperand(0).getOpcode() == ISD::XOR);
2196 // ((X^1)&1)^1 -> X & 1
2197 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2198 N0.getOperand(0).getOperand(0),
2199 N0.getOperand(1));
2200 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2201
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2202 return DAG.getSetCC(dl, VT, Val, N1,
2203 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2204 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2205 } else if (N1C->getAPIntValue() == 1 &&
2206 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2207 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2208 SDValue Op0 = N0;
2209 if (Op0.getOpcode() == ISD::TRUNCATE)
2210 Op0 = Op0.getOperand(0);
2211
2212 if ((Op0.getOpcode() == ISD::XOR) &&
2213 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2214 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2215 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2216 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2217 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2218 Cond);
2219 } else if (Op0.getOpcode() == ISD::AND &&
2220 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2221 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2222 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2223 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2224 Op0 = DAG.getNode(ISD::AND, dl, VT,
2225 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2226 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2227 else if (Op0.getValueType().bitsLT(VT))
2228 Op0 = DAG.getNode(ISD::AND, dl, VT,
2229 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2230 DAG.getConstant(1, VT));
2231
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2232 return DAG.getSetCC(dl, VT, Op0,
2233 DAG.getConstant(0, Op0.getValueType()),
2234 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2235 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2236 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2237 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2238
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2239 APInt MinVal, MaxVal;
2240 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2241 if (ISD::isSignedIntSetCC(Cond)) {
2242 MinVal = APInt::getSignedMinValue(OperandBitSize);
2243 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2244 } else {
2245 MinVal = APInt::getMinValue(OperandBitSize);
2246 MaxVal = APInt::getMaxValue(OperandBitSize);
2247 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2248
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2249 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2250 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2251 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2252 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2253 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2254 DAG.getConstant(C1-1, N1.getValueType()),
2255 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2256 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2257
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2258 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2259 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2260 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2261 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2262 DAG.getConstant(C1+1, N1.getValueType()),
2263 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2264 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2265
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2266 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2267 return DAG.getConstant(0, VT); // X < MIN --> false
2268 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2269 return DAG.getConstant(1, VT); // X >= MIN --> true
2270 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2271 return DAG.getConstant(0, VT); // X > MAX --> false
2272 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2273 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2274
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2275 // Canonicalize setgt X, Min --> setne X, Min
2276 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2277 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2278 // Canonicalize setlt X, Max --> setne X, Max
2279 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2280 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2281
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2282 // If we have setult X, 1, turn it into seteq X, 0
2283 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2284 return DAG.getSetCC(dl, VT, N0,
2285 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2286 ISD::SETEQ);
2287 // If we have setugt X, Max-1, turn it into seteq X, Max
2288 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2289 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2290 DAG.getConstant(MaxVal, N0.getValueType()),
2291 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2292
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2293 // If we have "setcc X, C0", check to see if we can shrink the immediate
2294 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2295
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2296 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2297 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2298 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2299 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2300 DAG.getConstant(0, N1.getValueType()),
2301 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2302
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2303 // SETULT X, SINTMIN -> SETGT X, -1
2304 if (Cond == ISD::SETULT &&
2305 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2306 SDValue ConstMinusOne =
2307 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2308 N1.getValueType());
2309 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2310 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2311
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2312 // Fold bit comparisons when we can.
2313 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2314 (VT == N0.getValueType() ||
2315 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2316 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2317 if (ConstantSDNode *AndRHS =
2318 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2319 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2320 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2321 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2322 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2323 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2324 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2325 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2326 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2327 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2328 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2329 // (X & 8) == 8 --> (X & 8) >> 3
2330 // Perform the xform if C1 is a single bit.
2331 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2332 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2333 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2334 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2335 }
2336 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2337 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2338 }
2339
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2340 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2341 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2342 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2343 if (O.getNode()) return O;
2344 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2345 // If the RHS of an FP comparison is a constant, simplify it away in
2346 // some cases.
2347 if (CFP->getValueAPF().isNaN()) {
2348 // If an operand is known to be a nan, we can fold it.
2349 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2350 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2351 case 0: // Known false.
2352 return DAG.getConstant(0, VT);
2353 case 1: // Known true.
2354 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2355 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2356 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2357 }
2358 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2359
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2360 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2361 // constant if knowing that the operand is non-nan is enough. We prefer to
2362 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2363 // materialize 0.0.
2364 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2365 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2366
2367 // If the condition is not legal, see if we can find an equivalent one
2368 // which is legal.
2369 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2370 // If the comparison was an awkward floating-point == or != and one of
2371 // the comparison operands is infinity or negative infinity, convert the
2372 // condition to a less-awkward <= or >=.
2373 if (CFP->getValueAPF().isInfinity()) {
2374 if (CFP->getValueAPF().isNegative()) {
2375 if (Cond == ISD::SETOEQ &&
2376 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2377 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2378 if (Cond == ISD::SETUEQ &&
2379 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2380 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2381 if (Cond == ISD::SETUNE &&
2382 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2383 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2384 if (Cond == ISD::SETONE &&
2385 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2386 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2387 } else {
2388 if (Cond == ISD::SETOEQ &&
2389 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2390 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2391 if (Cond == ISD::SETUEQ &&
2392 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2393 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2394 if (Cond == ISD::SETUNE &&
2395 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2396 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2397 if (Cond == ISD::SETONE &&
2398 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2399 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2400 }
2401 }
2402 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2403 }
2404
2405 if (N0 == N1) {
2406 // We can always fold X == X for integer setcc's.
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2407 if (N0.getValueType().isInteger()) {
2408 switch (getBooleanContents(N0.getValueType().isVector())) {
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2409 case UndefinedBooleanContent:
2410 case ZeroOrOneBooleanContent:
2411 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2412 case ZeroOrNegativeOneBooleanContent:
2413 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2414 }
2415 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2416 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2417 if (UOF == 2) // FP operators that are undefined on NaNs.
2418 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2419 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2420 return DAG.getConstant(UOF, VT);
2421 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2422 // if it is not already.
2423 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2424 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2425 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2426 }
2427
2428 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2429 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2430 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2431 N0.getOpcode() == ISD::XOR) {
2432 // Simplify (X+Y) == (X+Z) --> Y == Z
2433 if (N0.getOpcode() == N1.getOpcode()) {
2434 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2435 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2436 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2437 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2438 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2439 // If X op Y == Y op X, try other combinations.
2440 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2441 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2442 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2443 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2444 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2445 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2446 }
2447 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2448
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2449 // If RHS is a legal immediate value for a compare instruction, we need
2450 // to be careful about increasing register pressure needlessly.
2451 bool LegalRHSImm = false;
2452
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2453 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2454 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2455 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2456 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2457 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2458 DAG.getConstant(RHSC->getAPIntValue()-
2459 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2460 N0.getValueType()), Cond);
2461 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2462
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2463 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2464 if (N0.getOpcode() == ISD::XOR)
2465 // If we know that all of the inverted bits are zero, don't bother
2466 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2467 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2468 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2469 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2470 DAG.getConstant(LHSR->getAPIntValue() ^
2471 RHSC->getAPIntValue(),
2472 N0.getValueType()),
2473 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2474 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2475
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2476 // Turn (C1-X) == C2 --> X == C1-C2
2477 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2478 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2479 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2480 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2481 DAG.getConstant(SUBC->getAPIntValue() -
2482 RHSC->getAPIntValue(),
2483 N0.getValueType()),
2484 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2485 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2486 }
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2487
2488 // Could RHSC fold directly into a compare?
2489 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2490 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2491 }
2492
2493 // Simplify (X+Z) == X --> Z == 0
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2494 // Don't do this if X is an immediate that can fold into a cmp
2495 // instruction and X+Z has other uses. It could be an induction variable
2496 // chain, and the transform would increase register pressure.
2497 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2498 if (N0.getOperand(0) == N1)
2499 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2500 DAG.getConstant(0, N0.getValueType()), Cond);
2501 if (N0.getOperand(1) == N1) {
2502 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2503 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2504 DAG.getConstant(0, N0.getValueType()), Cond);
2505 else if (N0.getNode()->hasOneUse()) {
2506 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2507 // (Z-X) == X --> Z == X<<1
2508 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2509 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2510 if (!DCI.isCalledByLegalizer())
2511 DCI.AddToWorklist(SH.getNode());
2512 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2513 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2514 }
2515 }
2516 }
2517
2518 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2519 N1.getOpcode() == ISD::XOR) {
2520 // Simplify X == (X+Z) --> Z == 0
2521 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2522 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2523 DAG.getConstant(0, N1.getValueType()), Cond);
2524 } else if (N1.getOperand(1) == N0) {
2525 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2526 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2527 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2528 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2529 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2530 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2531 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2532 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2533 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2534 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2535 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2536 }
2537 }
2538 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2539
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2540 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2541 // Note that where y is variable and is known to have at most
2542 // one bit set (for example, if it is z&1) we cannot do this;
2543 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2544 if (N0.getOpcode() == ISD::AND)
2545 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2546 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2547 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2548 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2549 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2550 }
2551 }
2552 if (N1.getOpcode() == ISD::AND)
2553 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2554 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2555 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2556 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2557 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2558 }
2559 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2560 }
2561
2562 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2563 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2564 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2565 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2566 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2567 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2568 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2569 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2570 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2571 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2572 break;
2573 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2574 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2575 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2576 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2577 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2578 Temp = DAG.getNOT(dl, N0, MVT::i1);
2579 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2580 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2581 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2582 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2583 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2584 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2585 Temp = DAG.getNOT(dl, N1, MVT::i1);
2586 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2587 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2588 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2589 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2590 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2591 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2592 Temp = DAG.getNOT(dl, N0, MVT::i1);
2593 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2594 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2595 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2596 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2597 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2598 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2599 Temp = DAG.getNOT(dl, N1, MVT::i1);
2600 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2601 break;
2602 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2603 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2604 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2605 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2606 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2607 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2608 }
2609 return N0;
2610 }
2611
2612 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2613 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2614}
2615
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2616/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2617/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2618bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2619 int64_t &Offset) const {
2620 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2621 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2622 GA = GASD->getGlobal();
2623 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2624 return true;
2625 }
2626
2627 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2628 SDValue N1 = N->getOperand(0);
2629 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2630 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2631 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2632 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2633 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2634 return true;
2635 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2636 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2637 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2638 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2639 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2640 return true;
2641 }
2642 }
2643 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2644
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2645 return false;
2646}
2647
2648
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2649SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2650PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2651 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2652 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2653}
2654
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2655//===----------------------------------------------------------------------===//
2656// Inline Assembler Implementation Methods
2657//===----------------------------------------------------------------------===//
2658
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2659
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2660TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2661TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2662 if (Constraint.size() == 1) {
2663 switch (Constraint[0]) {
2664 default: break;
2665 case 'r': return C_RegisterClass;
2666 case 'm': // memory
2667 case 'o': // offsetable
2668 case 'V': // not offsetable
2669 return C_Memory;
2670 case 'i': // Simple Integer or Relocatable Constant
2671 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2672 case 'E': // Floating Point Constant
2673 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2674 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2675 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2676 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2677 case 'I': // Target registers.
2678 case 'J':
2679 case 'K':
2680 case 'L':
2681 case 'M':
2682 case 'N':
2683 case 'O':
2684 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2685 case '<':
2686 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2687 return C_Other;
2688 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2689 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2690
2691 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2692 Constraint[Constraint.size()-1] == '}')
2693 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2694 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2695}
2696
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2697/// LowerXConstraint - try to replace an X constraint, which matches anything,
2698/// with another that has more specific requirements based on the type of the
2699/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2700const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2701 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2702 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2703 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2704 return "f"; // works for many targets
2705 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2706}
2707
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2708/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2709/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2710void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2711 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2712 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2713 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2714
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2715 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2716
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2717 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2718 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2719 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2720 case 'X': // Allows any operand; labels (basic block) use this.
2721 if (Op.getOpcode() == ISD::BasicBlock) {
2722 Ops.push_back(Op);
2723 return;
2724 }
2725 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2726 case 'i': // Simple Integer or Relocatable Constant
2727 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2728 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2729 // These operands are interested in values of the form (GV+C), where C may
2730 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2731 // is possible and fine if either GV or C are missing.
2732 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2733 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2734
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2735 // If we have "(add GV, C)", pull out GV/C
2736 if (Op.getOpcode() == ISD::ADD) {
2737 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2738 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2739 if (C == 0 || GA == 0) {
2740 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2741 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2742 }
2743 if (C == 0 || GA == 0)
2744 C = 0, GA = 0;
2745 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2746
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2747 // If we find a valid operand, map to the TargetXXX version so that the
2748 // value itself doesn't get selected.
2749 if (GA) { // Either &GV or &GV+C
2750 if (ConstraintLetter != 'n') {
2751 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2752 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2753 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2754 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2755 Op.getValueType(), Offs));
2756 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2757 }
2758 }
2759 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2760 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2761 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2762 // gcc prints these as sign extended. Sign extend value to 64 bits
2763 // now; without this it would get ZExt'd later in
2764 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2765 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2766 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2767 return;
2768 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2769 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2770 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2771 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2772 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2773}
2774
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2775std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2776getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2777 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2778 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2779 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2780 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2781
2782 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2783 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2784
2785 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2786 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2787 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2788 E = RI->regclass_end(); RCI != E; ++RCI) {
2789 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2790
2791 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2792 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]2793 if (!isLegalRC(RC))
2794 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2795
2796 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2797 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2798 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2799 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2800 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2801 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2802
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2803 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2804}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2805
2806//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2807// Constraint Selection.
2808
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2809/// isMatchingInputConstraint - Return true of this is an input operand that is
2810/// a matching constraint like "4".
2811bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2812 assert(!ConstraintCode.empty() && "No known constraint!");
2813 return isdigit(ConstraintCode[0]);
2814}
2815
2816/// getMatchedOperand - If this is an input matching constraint, this method
2817/// returns the output operand it matches.
2818unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2819 assert(!ConstraintCode.empty() && "No known constraint!");
2820 return atoi(ConstraintCode.c_str());
2821}
2822
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2823
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2824/// ParseConstraints - Split up the constraint string from the inline
2825/// assembly value into the specific constraints and their prefixes,
2826/// and also tie in the associated operand values.
2827/// If this returns an empty vector, and if the constraint string itself
2828/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2829TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2830 ImmutableCallSite CS) const {
2831 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2832 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2833 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2834 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2835
2836 // Do a prepass over the constraints, canonicalizing them, and building up the
2837 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2838 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2839 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2840
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2841 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2842 unsigned ResNo = 0; // ResNo - The result number of the next output.
2843
2844 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2845 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2846 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2847
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2848 // Update multiple alternative constraint count.
2849 if (OpInfo.multipleAlternatives.size() > maCount)
2850 maCount = OpInfo.multipleAlternatives.size();
2851
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2852 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2853
2854 // Compute the value type for each operand.
2855 switch (OpInfo.Type) {
2856 case InlineAsm::isOutput:
2857 // Indirect outputs just consume an argument.
2858 if (OpInfo.isIndirect) {
2859 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2860 break;
2861 }
2862
2863 // The return value of the call is this value. As such, there is no
2864 // corresponding argument.
2865 assert(!CS.getType()->isVoidTy() &&
2866 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2867 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2868 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2869 } else {
2870 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2871 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2872 }
2873 ++ResNo;
2874 break;
2875 case InlineAsm::isInput:
2876 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2877 break;
2878 case InlineAsm::isClobber:
2879 // Nothing to do.
2880 break;
2881 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2882
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2883 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2884 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2885 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2886 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2887 if (!PtrTy)
2888 report_fatal_error("Indirect operand for inline asm not a pointer!");
2889 OpTy = PtrTy->getElementType();
2890 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2891
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2892 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2893 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2894 if (STy->getNumElements() == 1)
2895 OpTy = STy->getElementType(0);
2896
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2897 // If OpTy is not a single value, it may be a struct/union that we
2898 // can tile with integers.
2899 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2900 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2901 switch (BitSize) {
2902 default: break;
2903 case 1:
2904 case 8:
2905 case 16:
2906 case 32:
2907 case 64:
2908 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2909 OpInfo.ConstraintVT =
2910 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2911 break;
2912 }
2913 } else if (dyn_cast<PointerType>(OpTy)) {
2914 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2915 } else {
2916 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2917 }
2918 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2919 }
2920
2921 // If we have multiple alternative constraints, select the best alternative.
2922 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2923 if (maCount) {
2924 unsigned bestMAIndex = 0;
2925 int bestWeight = -1;
2926 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2927 int weight = -1;
2928 unsigned maIndex;
2929 // Compute the sums of the weights for each alternative, keeping track
2930 // of the best (highest weight) one so far.
2931 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2932 int weightSum = 0;
2933 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2934 cIndex != eIndex; ++cIndex) {
2935 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2936 if (OpInfo.Type == InlineAsm::isClobber)
2937 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2938
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2939 // If this is an output operand with a matching input operand,
2940 // look up the matching input. If their types mismatch, e.g. one
2941 // is an integer, the other is floating point, or their sizes are
2942 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2943 if (OpInfo.hasMatchingInput()) {
2944 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2945 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2946 if ((OpInfo.ConstraintVT.isInteger() !=
2947 Input.ConstraintVT.isInteger()) ||
2948 (OpInfo.ConstraintVT.getSizeInBits() !=
2949 Input.ConstraintVT.getSizeInBits())) {
2950 weightSum = -1; // Can't match.
2951 break;
2952 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2953 }
2954 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2955 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2956 if (weight == -1) {
2957 weightSum = -1;
2958 break;
2959 }
2960 weightSum += weight;
2961 }
2962 // Update best.
2963 if (weightSum > bestWeight) {
2964 bestWeight = weightSum;
2965 bestMAIndex = maIndex;
2966 }
2967 }
2968
2969 // Now select chosen alternative in each constraint.
2970 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2971 cIndex != eIndex; ++cIndex) {
2972 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2973 if (cInfo.Type == InlineAsm::isClobber)
2974 continue;
2975 cInfo.selectAlternative(bestMAIndex);
2976 }
2977 }
2978 }
2979
2980 // Check and hook up tied operands, choose constraint code to use.
2981 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2982 cIndex != eIndex; ++cIndex) {
2983 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2984
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2985 // If this is an output operand with a matching input operand, look up the
2986 // matching input. If their types mismatch, e.g. one is an integer, the
2987 // other is floating point, or their sizes are different, flag it as an
2988 // error.
2989 if (OpInfo.hasMatchingInput()) {
2990 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2991
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2992 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2993 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2994 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2995 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2996 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2997 if ((OpInfo.ConstraintVT.isInteger() !=
2998 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2999 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3000 report_fatal_error("Unsupported asm: input constraint"
3001 " with a matching output constraint of"
3002 " incompatible type!");
3003 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3004 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3005
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3006 }
3007 }
3008
3009 return ConstraintOperands;
3010}
3011
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3012
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3013/// getConstraintGenerality - Return an integer indicating how general CT
3014/// is.
3015static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3016 switch (CT) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3017 case TargetLowering::C_Other:
3018 case TargetLowering::C_Unknown:
3019 return 0;
3020 case TargetLowering::C_Register:
3021 return 1;
3022 case TargetLowering::C_RegisterClass:
3023 return 2;
3024 case TargetLowering::C_Memory:
3025 return 3;
3026 }
Chandler Carruth732f05c2012-01-10 18:08:01 +0000[diff] [blame]3027 llvm_unreachable("Invalid constraint type");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3028}
3029
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3030/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3031/// This object must already have been set up with the operand type
3032/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3033TargetLowering::ConstraintWeight
3034 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3035 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3036 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3037 if (maIndex >= (int)info.multipleAlternatives.size())
3038 rCodes = &info.Codes;
3039 else
3040 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3041 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3042
3043 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3044 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3045 ConstraintWeight weight =
3046 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3047 if (weight > BestWeight)
3048 BestWeight = weight;
3049 }
3050
3051 return BestWeight;
3052}
3053
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3054/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3055/// This object must already have been set up with the operand type
3056/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3057TargetLowering::ConstraintWeight
3058 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3059 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3060 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3061 Value *CallOperandVal = info.CallOperandVal;
3062 // If we don't have a value, we can't do a match,
3063 // but allow it at the lowest weight.
3064 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3065 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3066 // Look at the constraint type.
3067 switch (*constraint) {
3068 case 'i': // immediate integer.
3069 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3070 if (isa<ConstantInt>(CallOperandVal))
3071 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3072 break;
3073 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3074 if (isa<GlobalValue>(CallOperandVal))
3075 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3076 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3077 case 'E': // immediate float if host format.
3078 case 'F': // immediate float.
3079 if (isa<ConstantFP>(CallOperandVal))
3080 weight = CW_Constant;
3081 break;
3082 case '<': // memory operand with autodecrement.
3083 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3084 case 'm': // memory operand.
3085 case 'o': // offsettable memory operand
3086 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3087 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3088 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3089 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3090 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3091 // note: Clang converts "g" to "imr".
3092 if (CallOperandVal->getType()->isIntegerTy())
3093 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3094 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3095 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3096 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3097 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3098 break;
3099 }
3100 return weight;
3101}
3102
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3103/// ChooseConstraint - If there are multiple different constraints that we
3104/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3105/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3106/// Other -> immediates and magic values
3107/// Register -> one specific register
3108/// RegisterClass -> a group of regs
3109/// Memory -> memory
3110/// Ideally, we would pick the most specific constraint possible: if we have
3111/// something that fits into a register, we would pick it. The problem here
3112/// is that if we have something that could either be in a register or in
3113/// memory that use of the register could cause selection of *other*
3114/// operands to fail: they might only succeed if we pick memory. Because of
3115/// this the heuristic we use is:
3116///
3117/// 1) If there is an 'other' constraint, and if the operand is valid for
3118/// that constraint, use it. This makes us take advantage of 'i'
3119/// constraints when available.
3120/// 2) Otherwise, pick the most general constraint present. This prefers
3121/// 'm' over 'r', for example.
3122///
3123static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3124 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3125 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3126 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3127 unsigned BestIdx = 0;
3128 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3129 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3130
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3131 // Loop over the options, keeping track of the most general one.
3132 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3133 TargetLowering::ConstraintType CType =
3134 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3135
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3136 // If this is an 'other' constraint, see if the operand is valid for it.
3137 // For example, on X86 we might have an 'rI' constraint. If the operand
3138 // is an integer in the range [0..31] we want to use I (saving a load
3139 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3140 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3141 assert(OpInfo.Codes[i].size() == 1 &&
3142 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3143 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3144 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3145 ResultOps, *DAG);
3146 if (!ResultOps.empty()) {
3147 BestType = CType;
3148 BestIdx = i;
3149 break;
3150 }
3151 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3152
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3153 // Things with matching constraints can only be registers, per gcc
3154 // documentation. This mainly affects "g" constraints.
3155 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3156 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3157
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3158 // This constraint letter is more general than the previous one, use it.
3159 int Generality = getConstraintGenerality(CType);
3160 if (Generality > BestGenerality) {
3161 BestType = CType;
3162 BestIdx = i;
3163 BestGenerality = Generality;
3164 }
3165 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3166
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3167 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3168 OpInfo.ConstraintType = BestType;
3169}
3170
3171/// ComputeConstraintToUse - Determines the constraint code and constraint
3172/// type to use for the specific AsmOperandInfo, setting
3173/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3174void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3175 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3176 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3177 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3178
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3179 // Single-letter constraints ('r') are very common.
3180 if (OpInfo.Codes.size() == 1) {
3181 OpInfo.ConstraintCode = OpInfo.Codes[0];
3182 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3183 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3184 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3185 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3186
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3187 // 'X' matches anything.
3188 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3189 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3190 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3191 // the result, which is not what we want to look at; leave them alone.
3192 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3193 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3194 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3195 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3196 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3197
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3198 // Otherwise, try to resolve it to something we know about by looking at
3199 // the actual operand type.
3200 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3201 OpInfo.ConstraintCode = Repl;
3202 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3203 }
3204 }
3205}
3206
3207//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3208// Loop Strength Reduction hooks
3209//===----------------------------------------------------------------------===//
3210
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3211/// isLegalAddressingMode - Return true if the addressing mode represented
3212/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3213bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3214 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3215 // The default implementation of this implements a conservative RISCy, r+r and
3216 // r+i addr mode.
3217
3218 // Allows a sign-extended 16-bit immediate field.
3219 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3220 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3221
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3222 // No global is ever allowed as a base.
3223 if (AM.BaseGV)
3224 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3225
3226 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3227 switch (AM.Scale) {
3228 case 0: // "r+i" or just "i", depending on HasBaseReg.
3229 break;
3230 case 1:
3231 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3232 return false;
3233 // Otherwise we have r+r or r+i.
3234 break;
3235 case 2:
3236 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3237 return false;
3238 // Allow 2*r as r+r.
3239 break;
3240 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3241
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3242 return true;
3243}
3244
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3245/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3246/// with the multiplicative inverse of the constant.
3247SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3248 SelectionDAG &DAG) const {
3249 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3250 APInt d = C->getAPIntValue();
3251 assert(d != 0 && "Division by zero!");
3252
3253 // Shift the value upfront if it is even, so the LSB is one.
3254 unsigned ShAmt = d.countTrailingZeros();
3255 if (ShAmt) {
3256 // TODO: For UDIV use SRL instead of SRA.
3257 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3258 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3259 d = d.ashr(ShAmt);
3260 }
3261
3262 // Calculate the multiplicative inverse, using Newton's method.
3263 APInt t, xn = d;
3264 while ((t = d*xn) != 1)
3265 xn *= APInt(d.getBitWidth(), 2) - t;
3266
3267 Op2 = DAG.getConstant(xn, Op1.getValueType());
3268 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3269}
3270
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3271/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3272/// return a DAG expression to select that will generate the same value by
3273/// multiplying by a magic number. See:
3274/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3275SDValue TargetLowering::
3276BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3277 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3278 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3279 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3280
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3281 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3282 // FIXME: We should be more aggressive here.
3283 if (!isTypeLegal(VT))
3284 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3285
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3286 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3287 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3288
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3289 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3290 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3291 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3292 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3293 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3294 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3295 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3296 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3297 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3298 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3299 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3300 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3301 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3302 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3303 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3304 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3305 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3306 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3307 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3308 }
3309 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3310 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3311 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3312 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3313 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3314 }
3315 // Shift right algebraic if shift value is nonzero
3316 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3317 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3318 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3319 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3320 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3321 }
3322 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3323 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3324 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3325 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3326 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3327 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3328 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3329}
3330
3331/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3332/// return a DAG expression to select that will generate the same value by
3333/// multiplying by a magic number. See:
3334/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3335SDValue TargetLowering::
3336BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3337 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3338 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3339 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3340
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3341 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3342 // FIXME: We should be more aggressive here.
3343 if (!isTypeLegal(VT))
3344 return SDValue();
3345
3346 // FIXME: We should use a narrower constant when the upper
3347 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3348 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3349 APInt::mu magics = N1C.magicu();
3350
3351 SDValue Q = N->getOperand(0);
3352
3353 // If the divisor is even, we can avoid using the expensive fixup by shifting
3354 // the divided value upfront.
3355 if (magics.a != 0 && !N1C[0]) {
3356 unsigned Shift = N1C.countTrailingZeros();
3357 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3358 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3359 if (Created)
3360 Created->push_back(Q.getNode());
3361
3362 // Get magic number for the shifted divisor.
3363 magics = N1C.lshr(Shift).magicu(Shift);
3364 assert(magics.a == 0 && "Should use cheap fixup now");
3365 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3366
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3367 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3368 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3369 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3370 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3371 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3372 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3373 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3374 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3375 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3376 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3377 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3378 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3379 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3380
3381 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3382 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3383 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3384 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3385 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3386 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3387 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3388 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3389 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3390 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3391 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3392 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3393 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3394 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3395 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3396 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3397 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3398 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3399 }
3400}