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gerrit-public.fairphone.software / platform / external / llvm / e853d2e2508e21b5c3156c7d8b6e6902a7d2604a / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 56f3a45c9a67def86c8fb382f22955cceab466e7 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]28#include "llvm/ADT/BitVector.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]29#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]30#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]31#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]32#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]33#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]34using namespace llvm;
35
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]36/// InitLibcallNames - Set default libcall names.
37///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]38static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]39 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]42 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]43 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]46 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]47 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]50 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]51 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]52 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]55 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]59 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]60 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]63 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]64 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]65 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]68 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]69 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]70 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]73 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]74 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]75 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]78 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]79
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
91
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]96 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]98 Names[RTLIB::SUB_F32] = "__subsf3";
99 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]100 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]102 Names[RTLIB::MUL_F32] = "__mulsf3";
103 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]104 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]106 Names[RTLIB::DIV_F32] = "__divsf3";
107 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]108 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]110 Names[RTLIB::REM_F32] = "fmodf";
111 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]112 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]113 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]114 Names[RTLIB::FMA_F32] = "fmaf";
115 Names[RTLIB::FMA_F64] = "fma";
116 Names[RTLIB::FMA_F80] = "fmal";
117 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]118 Names[RTLIB::POWI_F32] = "__powisf2";
119 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]120 Names[RTLIB::POWI_F80] = "__powixf2";
121 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]122 Names[RTLIB::SQRT_F32] = "sqrtf";
123 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]124 Names[RTLIB::SQRT_F80] = "sqrtl";
125 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]126 Names[RTLIB::LOG_F32] = "logf";
127 Names[RTLIB::LOG_F64] = "log";
128 Names[RTLIB::LOG_F80] = "logl";
129 Names[RTLIB::LOG_PPCF128] = "logl";
130 Names[RTLIB::LOG2_F32] = "log2f";
131 Names[RTLIB::LOG2_F64] = "log2";
132 Names[RTLIB::LOG2_F80] = "log2l";
133 Names[RTLIB::LOG2_PPCF128] = "log2l";
134 Names[RTLIB::LOG10_F32] = "log10f";
135 Names[RTLIB::LOG10_F64] = "log10";
136 Names[RTLIB::LOG10_F80] = "log10l";
137 Names[RTLIB::LOG10_PPCF128] = "log10l";
138 Names[RTLIB::EXP_F32] = "expf";
139 Names[RTLIB::EXP_F64] = "exp";
140 Names[RTLIB::EXP_F80] = "expl";
141 Names[RTLIB::EXP_PPCF128] = "expl";
142 Names[RTLIB::EXP2_F32] = "exp2f";
143 Names[RTLIB::EXP2_F64] = "exp2";
144 Names[RTLIB::EXP2_F80] = "exp2l";
145 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]146 Names[RTLIB::SIN_F32] = "sinf";
147 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]148 Names[RTLIB::SIN_F80] = "sinl";
149 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]150 Names[RTLIB::COS_F32] = "cosf";
151 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]152 Names[RTLIB::COS_F80] = "cosl";
153 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]154 Names[RTLIB::POW_F32] = "powf";
155 Names[RTLIB::POW_F64] = "pow";
156 Names[RTLIB::POW_F80] = "powl";
157 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]158 Names[RTLIB::CEIL_F32] = "ceilf";
159 Names[RTLIB::CEIL_F64] = "ceil";
160 Names[RTLIB::CEIL_F80] = "ceill";
161 Names[RTLIB::CEIL_PPCF128] = "ceill";
162 Names[RTLIB::TRUNC_F32] = "truncf";
163 Names[RTLIB::TRUNC_F64] = "trunc";
164 Names[RTLIB::TRUNC_F80] = "truncl";
165 Names[RTLIB::TRUNC_PPCF128] = "truncl";
166 Names[RTLIB::RINT_F32] = "rintf";
167 Names[RTLIB::RINT_F64] = "rint";
168 Names[RTLIB::RINT_F80] = "rintl";
169 Names[RTLIB::RINT_PPCF128] = "rintl";
170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174 Names[RTLIB::FLOOR_F32] = "floorf";
175 Names[RTLIB::FLOOR_F64] = "floor";
176 Names[RTLIB::FLOOR_F80] = "floorl";
177 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]178 Names[RTLIB::COPYSIGN_F32] = "copysignf";
179 Names[RTLIB::COPYSIGN_F64] = "copysign";
180 Names[RTLIB::COPYSIGN_F80] = "copysignl";
181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]246 Names[RTLIB::OEQ_F32] = "__eqsf2";
247 Names[RTLIB::OEQ_F64] = "__eqdf2";
248 Names[RTLIB::UNE_F32] = "__nesf2";
249 Names[RTLIB::UNE_F64] = "__nedf2";
250 Names[RTLIB::OGE_F32] = "__gesf2";
251 Names[RTLIB::OGE_F64] = "__gedf2";
252 Names[RTLIB::OLT_F32] = "__ltsf2";
253 Names[RTLIB::OLT_F64] = "__ltdf2";
254 Names[RTLIB::OLE_F32] = "__lesf2";
255 Names[RTLIB::OLE_F64] = "__ledf2";
256 Names[RTLIB::OGT_F32] = "__gtsf2";
257 Names[RTLIB::OGT_F64] = "__gtdf2";
258 Names[RTLIB::UO_F32] = "__unordsf2";
259 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]260 Names[RTLIB::O_F32] = "__unordsf2";
261 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]262 Names[RTLIB::MEMCPY] = "memcpy";
263 Names[RTLIB::MEMMOVE] = "memmove";
264 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]298}
299
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]300/// InitLibcallCallingConvs - Set default libcall CallingConvs.
301///
302static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304 CCs[i] = CallingConv::C;
305 }
306}
307
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]308/// getFPEXT - Return the FPEXT_*_* value for the given types, or
309/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]311 if (OpVT == MVT::f32) {
312 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]313 return FPEXT_F32_F64;
314 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]315
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]316 return UNKNOWN_LIBCALL;
317}
318
319/// getFPROUND - Return the FPROUND_*_* value for the given types, or
320/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]322 if (RetVT == MVT::f32) {
323 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]324 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]325 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]326 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]327 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]328 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]329 } else if (RetVT == MVT::f64) {
330 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]331 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]332 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]333 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]334 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]335
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]336 return UNKNOWN_LIBCALL;
337}
338
339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]342 if (OpVT == MVT::f32) {
343 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]344 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]345 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]346 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]347 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]348 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]349 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]350 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]351 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]352 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]353 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]354 if (RetVT == MVT::i8)
355 return FPTOSINT_F64_I8;
356 if (RetVT == MVT::i16)
357 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]358 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]359 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]361 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]362 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]363 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]364 } else if (OpVT == MVT::f80) {
365 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]366 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]367 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]368 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]369 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]370 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]371 } else if (OpVT == MVT::ppcf128) {
372 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]373 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]374 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]375 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]376 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]377 return FPTOSINT_PPCF128_I128;
378 }
379 return UNKNOWN_LIBCALL;
380}
381
382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]385 if (OpVT == MVT::f32) {
386 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]387 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]388 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]389 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]390 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]393 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]394 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]395 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]396 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]397 if (RetVT == MVT::i8)
398 return FPTOUINT_F64_I8;
399 if (RetVT == MVT::i16)
400 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]401 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]402 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]403 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]404 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]405 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]406 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]407 } else if (OpVT == MVT::f80) {
408 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]409 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]410 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]411 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]412 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]413 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]414 } else if (OpVT == MVT::ppcf128) {
415 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]416 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]417 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]418 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]419 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]420 return FPTOUINT_PPCF128_I128;
421 }
422 return UNKNOWN_LIBCALL;
423}
424
425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]428 if (OpVT == MVT::i32) {
429 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]430 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]431 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]432 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]434 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]436 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]437 } else if (OpVT == MVT::i64) {
438 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]443 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]444 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]445 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]446 } else if (OpVT == MVT::i128) {
447 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]449 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]450 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]451 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]452 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]453 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]454 return SINTTOFP_I128_PPCF128;
455 }
456 return UNKNOWN_LIBCALL;
457}
458
459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]466 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]467 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]468 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]469 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]470 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]471 } else if (OpVT == MVT::i64) {
472 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]475 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]476 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]477 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]478 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]479 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]480 } else if (OpVT == MVT::i128) {
481 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]483 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]484 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]485 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]486 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]487 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]488 return UINTTOFP_I128_PPCF128;
489 }
490 return UNKNOWN_LIBCALL;
491}
492
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]493/// InitCmpLibcallCCs - Set default comparison libcall CC.
494///
495static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499 CCs[RTLIB::UNE_F32] = ISD::SETNE;
500 CCs[RTLIB::UNE_F64] = ISD::SETNE;
501 CCs[RTLIB::OGE_F32] = ISD::SETGE;
502 CCs[RTLIB::OGE_F64] = ISD::SETGE;
503 CCs[RTLIB::OLT_F32] = ISD::SETLT;
504 CCs[RTLIB::OLT_F64] = ISD::SETLT;
505 CCs[RTLIB::OLE_F32] = ISD::SETLE;
506 CCs[RTLIB::OLE_F64] = ISD::SETLE;
507 CCs[RTLIB::OGT_F32] = ISD::SETGT;
508 CCs[RTLIB::OGT_F64] = ISD::SETGT;
509 CCs[RTLIB::UO_F32] = ISD::SETNE;
510 CCs[RTLIB::UO_F64] = ISD::SETNE;
511 CCs[RTLIB::O_F32] = ISD::SETEQ;
512 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]513}
514
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]515/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]516TargetLowering::TargetLowering(const TargetMachine &tm,
517 const TargetLoweringObjectFile *tlof)
Nadav Rotemfcb2c3c2012-06-04 11:27:21 +0000[diff] [blame]518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]519 // All operations default to being supported.
520 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]521 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]524 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]525
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]526 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]528 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]529 for (unsigned IM = (unsigned)ISD::PRE_INC;
530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]533 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]534
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]535 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]538 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]539
540 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]542
543 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]544 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]545 // to optimize expansions for certain constants.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]546 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]547 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]550
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]551 // These library functions default to expand.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]552 setOperationAction(ISD::FLOG , MVT::f16, Expand);
553 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
554 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555 setOperationAction(ISD::FEXP , MVT::f16, Expand);
556 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
557 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
560 setOperationAction(ISD::FRINT, MVT::f16, Expand);
561 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]562 setOperationAction(ISD::FLOG , MVT::f32, Expand);
563 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
564 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565 setOperationAction(ISD::FEXP , MVT::f32, Expand);
566 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
567 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
570 setOperationAction(ISD::FRINT, MVT::f32, Expand);
571 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]572 setOperationAction(ISD::FLOG , MVT::f64, Expand);
573 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
574 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575 setOperationAction(ISD::FEXP , MVT::f64, Expand);
576 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
577 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
580 setOperationAction(ISD::FRINT, MVT::f64, Expand);
581 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]582
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]583 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]584 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]585
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]586 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]587 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]588 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]589 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]590 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]591 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
592 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]593 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]594 UseUnderscoreSetJmp = false;
595 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]596 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]597 IntDivIsCheap = false;
598 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]599 JumpIsExpensive = false;
Benjamin Krameraaf723d2012-05-05 12:49:14 +0000[diff] [blame]600 predictableSelectIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]601 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]602 ExceptionPointerRegister = 0;
603 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]604 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]605 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]606 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]607 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]608 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]609 MinFunctionAlignment = 0;
610 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]611 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]612 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]613 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]614 InsertFencesForAtomic = false;
Evan Cheng769951f2012-07-02 22:39:56 +0000[diff] [blame]615 SupportJumpTables = true;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]616
617 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]618 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]619 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]620}
621
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]622TargetLowering::~TargetLowering() {
623 delete &TLOF;
624}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]625
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]626MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
627 return MVT::getIntegerVT(8*TD->getPointerSize());
628}
629
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]630/// canOpTrap - Returns true if the operation can trap for the value type.
631/// VT must be a legal type.
632bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633 assert(isTypeLegal(VT));
634 switch (Op) {
635 default:
636 return false;
637 case ISD::FDIV:
638 case ISD::FREM:
639 case ISD::SDIV:
640 case ISD::UDIV:
641 case ISD::SREM:
642 case ISD::UREM:
643 return true;
644 }
645}
646
647
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]648static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]649 unsigned &NumIntermediates,
650 EVT &RegisterVT,
651 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]652 // Figure out the right, legal destination reg to copy into.
653 unsigned NumElts = VT.getVectorNumElements();
654 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]655
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]656 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]657
658 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]659 // could break down into LHS/RHS like LegalizeDAG does.
660 if (!isPowerOf2_32(NumElts)) {
661 NumVectorRegs = NumElts;
662 NumElts = 1;
663 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]664
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]665 // Divide the input until we get to a supported size. This will always
666 // end with a scalar if the target doesn't support vectors.
667 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
668 NumElts >>= 1;
669 NumVectorRegs <<= 1;
670 }
671
672 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]673
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]674 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675 if (!TLI->isTypeLegal(NewVT))
676 NewVT = EltTy;
677 IntermediateVT = NewVT;
678
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]679 unsigned NewVTSize = NewVT.getSizeInBits();
680
681 // Convert sizes such as i33 to i64.
682 if (!isPowerOf2_32(NewVTSize))
683 NewVTSize = NextPowerOf2(NewVTSize);
684
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]685 EVT DestVT = TLI->getRegisterType(NewVT);
686 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]687 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]688 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]689
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]690 // Otherwise, promotion or legal types use the same number of registers as
691 // the vector decimated to the appropriate level.
692 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]693}
694
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]695/// isLegalRC - Return true if the value types that can be represented by the
696/// specified register class are all legal.
697bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
698 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
699 I != E; ++I) {
700 if (isTypeLegal(*I))
701 return true;
702 }
703 return false;
704}
705
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]706/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]707/// of the register class for the specified type and its associated "cost".
708std::pair<const TargetRegisterClass*, uint8_t>
709TargetLowering::findRepresentativeClass(EVT VT) const {
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]710 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]711 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
712 if (!RC)
713 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]714
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]715 // Compute the set of all super-register classes.
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]716 BitVector SuperRegRC(TRI->getNumRegClasses());
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]717 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]718 SuperRegRC.setBitsInMask(RCI.getMask());
719
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]720 // Find the first legal register class with the largest spill size.
721 const TargetRegisterClass *BestRC = RC;
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]722 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
723 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]724 // We want the largest possible spill size.
725 if (SuperRC->getSize() <= BestRC->getSize())
726 continue;
727 if (!isLegalRC(SuperRC))
728 continue;
729 BestRC = SuperRC;
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]730 }
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]731 return std::make_pair(BestRC, 1);
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]732}
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]733
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]734/// computeRegisterProperties - Once all of the register classes are added,
735/// this allows us to compute derived properties we expose.
736void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]737 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]738 "Too many value types for ValueTypeActions to hold!");
739
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]740 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]741 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]742 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]743 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]744 }
745 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]746 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]747
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]748 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]749 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]750 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]751 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]752
753 // Every integer value type larger than this largest register takes twice as
754 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]755 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]756 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
757 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]758 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]759 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]760 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
761 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]762 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]763 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]764
765 // Inspect all of the ValueType's smaller than the largest integer
766 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]767 unsigned LegalIntReg = LargestIntReg;
768 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]769 IntReg >= (unsigned)MVT::i1; --IntReg) {
770 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]771 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]772 LegalIntReg = IntReg;
773 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]774 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Roman Divacky59324292012-09-05 22:26:57 +0000[diff] [blame]775 (const MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]776 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]777 }
778 }
779
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]780 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]781 if (!isTypeLegal(MVT::ppcf128)) {
782 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
783 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
784 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]785 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]786 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]787
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]788 // Decide how to handle f64. If the target does not have native f64 support,
789 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]790 if (!isTypeLegal(MVT::f64)) {
791 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
792 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
793 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]794 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]795 }
796
797 // Decide how to handle f32. If the target does not have native support for
798 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]799 if (!isTypeLegal(MVT::f32)) {
800 if (isTypeLegal(MVT::f64)) {
801 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
802 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
803 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]804 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]805 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]806 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
807 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
808 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]809 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]810 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]811 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]812
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]813 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]814 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]816 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]817 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]818
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]819 // Determine if there is a legal wider type. If so, we should promote to
820 // that wider vector type.
821 EVT EltVT = VT.getVectorElementType();
822 unsigned NElts = VT.getVectorNumElements();
823 if (NElts != 1) {
824 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]825 // First try to promote the elements of integer vectors. If no legal
826 // promotion was found, fallback to the widen-vector method.
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]827 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
828 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]829 // Promote vectors of integers to vectors with the same number
830 // of elements, with a wider element type.
831 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
832 && SVT.getVectorNumElements() == NElts &&
833 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
834 TransformToType[i] = SVT;
835 RegisterTypeForVT[i] = SVT;
836 NumRegistersForVT[i] = 1;
837 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
838 IsLegalWiderType = true;
839 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]840 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]841 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]842
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]843 if (IsLegalWiderType) continue;
844
845 // Try to widen the vector.
846 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
847 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]848 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]849 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]850 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]851 TransformToType[i] = SVT;
852 RegisterTypeForVT[i] = SVT;
853 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]854 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]855 IsLegalWiderType = true;
856 break;
857 }
858 }
859 if (IsLegalWiderType) continue;
860 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]861
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]862 MVT IntermediateVT;
863 EVT RegisterVT;
864 unsigned NumIntermediates;
865 NumRegistersForVT[i] =
866 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
867 RegisterVT, this);
868 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]869
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]870 EVT NVT = VT.getPow2VectorType();
871 if (NVT == VT) {
872 // Type is already a power of 2. The default action is to split.
873 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]874 unsigned NumElts = VT.getVectorNumElements();
875 ValueTypeActions.setTypeAction(VT,
876 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]877 } else {
878 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]879 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]880 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]881 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]882
883 // Determine the 'representative' register class for each value type.
884 // An representative register class is the largest (meaning one which is
885 // not a sub-register class / subreg register class) legal register class for
886 // a group of value types. For example, on i386, i8, i16, and i32
887 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]888 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]889 const TargetRegisterClass* RRC;
890 uint8_t Cost;
891 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
892 RepRegClassForVT[i] = RRC;
893 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]894 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]895}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]896
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]897const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
898 return NULL;
899}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]900
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]901EVT TargetLowering::getSetCCResultType(EVT VT) const {
902 assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]903 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]904}
905
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]906MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
907 return MVT::i32; // return the default value
908}
909
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]910/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]911/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
912/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
913/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]914///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]915/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]916/// register. It also returns the VT and quantity of the intermediate values
917/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]918///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]919unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]920 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]921 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]922 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]923 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]924
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]925 // If there is a wider vector type with the same element type as this one,
Nadav Rotemdb346162012-04-21 20:08:32 +0000[diff] [blame]926 // or a promoted vector type that has the same number of elements which
927 // are wider, then we should convert to that legal vector type.
928 // This handles things like <2 x float> -> <4 x float> and
929 // <4 x i1> -> <4 x i32>.
930 LegalizeTypeAction TA = getTypeAction(Context, VT);
931 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]932 RegisterVT = getTypeToTransformTo(Context, VT);
933 if (isTypeLegal(RegisterVT)) {
934 IntermediateVT = RegisterVT;
935 NumIntermediates = 1;
936 return 1;
937 }
938 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]939
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]940 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]941 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]942
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]943 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]944
945 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]946 // could break down into LHS/RHS like LegalizeDAG does.
947 if (!isPowerOf2_32(NumElts)) {
948 NumVectorRegs = NumElts;
949 NumElts = 1;
950 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]951
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]952 // Divide the input until we get to a supported size. This will always
953 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]954 while (NumElts > 1 && !isTypeLegal(
955 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]956 NumElts >>= 1;
957 NumVectorRegs <<= 1;
958 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]959
960 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]961
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]962 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]963 if (!isTypeLegal(NewVT))
964 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]965 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]966
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]967 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]968 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]969 unsigned NewVTSize = NewVT.getSizeInBits();
970
971 // Convert sizes such as i33 to i64.
972 if (!isPowerOf2_32(NewVTSize))
973 NewVTSize = NextPowerOf2(NewVTSize);
974
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]975 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]976 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]977
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]978 // Otherwise, promotion or legal types use the same number of registers as
979 // the vector decimated to the appropriate level.
980 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]981}
982
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]983/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]984/// type of the given function. This does not require a DAG or a return value,
985/// and is suitable for use before any DAGs for the function are constructed.
986/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]987void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]988 SmallVectorImpl<ISD::OutputArg> &Outs,
Eli Friedman2db0e9e2012-05-25 00:09:29 +0000[diff] [blame]989 const TargetLowering &TLI) {
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]990 SmallVector<EVT, 4> ValueVTs;
991 ComputeValueVTs(TLI, ReturnType, ValueVTs);
992 unsigned NumValues = ValueVTs.size();
993 if (NumValues == 0) return;
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]994
995 for (unsigned j = 0, f = NumValues; j != f; ++j) {
996 EVT VT = ValueVTs[j];
997 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
998
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]999 if (attr.hasSExtAttr())
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1000 ExtendKind = ISD::SIGN_EXTEND;
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]1001 else if (attr.hasZExtAttr())
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1002 ExtendKind = ISD::ZERO_EXTEND;
1003
1004 // FIXME: C calling convention requires the return type to be promoted to
1005 // at least 32-bit. But this is not necessary for non-C calling
1006 // conventions. The frontend should mark functions whose return values
1007 // require promoting with signext or zeroext attributes.
1008 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1009 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1010 if (VT.bitsLT(MinVT))
1011 VT = MinVT;
1012 }
1013
1014 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1015 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1016
1017 // 'inreg' on function refers to return value
1018 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]1019 if (attr.hasInRegAttr())
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1020 Flags.setInReg();
1021
1022 // Propagate extension type if any
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]1023 if (attr.hasSExtAttr())
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1024 Flags.setSExt();
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]1025 else if (attr.hasZExtAttr())
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1026 Flags.setZExt();
1027
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame^]1028 for (unsigned i = 0; i < NumParts; ++i)
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1029 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1030 }
1031}
1032
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1033/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1034/// function arguments in the caller parameter area. This is the actual
1035/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1036unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1037 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1038}
1039
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1040/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1041/// current function. The returned value is a member of the
1042/// MachineJumpTableInfo::JTEntryKind enum.
1043unsigned TargetLowering::getJumpTableEncoding() const {
1044 // In non-pic modes, just use the address of a block.
1045 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1046 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1047
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1048 // In PIC mode, if the target supports a GPRel32 directive, use it.
1049 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1050 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1051
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1052 // Otherwise, use a label difference.
1053 return MachineJumpTableInfo::EK_LabelDifference32;
1054}
1055
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1056SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1057 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1058 // If our PIC model is GP relative, use the global offset table as the base.
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1059 unsigned JTEncoding = getJumpTableEncoding();
1060
1061 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1062 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1063 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1064
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1065 return Table;
1066}
1067
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1068/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1069/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1070/// MCExpr.
1071const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1072TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1073 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1074 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1075 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1076}
1077
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1078bool
1079TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1080 // Assume that everything is safe in static mode.
1081 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1082 return true;
1083
1084 // In dynamic-no-pic mode, assume that known defined values are safe.
1085 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1086 GA &&
1087 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1088 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1089 return true;
1090
1091 // Otherwise assume nothing is safe.
1092 return false;
1093}
1094
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1095//===----------------------------------------------------------------------===//
1096// Optimization Methods
1097//===----------------------------------------------------------------------===//
1098
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1099/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1100/// specified instruction is a constant integer. If so, check to see if there
1101/// are any bits set in the constant that are not demanded. If so, shrink the
1102/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1103bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1104 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1105 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1106
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1107 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1108 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1109 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1110 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1111 case ISD::AND:
1112 case ISD::OR: {
1113 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1114 if (!C) return false;
1115
1116 if (Op.getOpcode() == ISD::XOR &&
1117 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1118 return false;
1119
1120 // if we can expand it to have all bits set, do it
1121 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1122 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1123 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1124 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1125 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1126 VT));
1127 return CombineTo(Op, New);
1128 }
1129
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1130 break;
1131 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1132 }
1133
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1134 return false;
1135}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1136
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1137/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1138/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1139/// cast, but it could be generalized for targets with other types of
1140/// implicit widening casts.
1141bool
1142TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1143 unsigned BitWidth,
1144 const APInt &Demanded,
1145 DebugLoc dl) {
1146 assert(Op.getNumOperands() == 2 &&
1147 "ShrinkDemandedOp only supports binary operators!");
1148 assert(Op.getNode()->getNumValues() == 1 &&
1149 "ShrinkDemandedOp only supports nodes with one result!");
1150
1151 // Don't do this if the node has another user, which may require the
1152 // full value.
1153 if (!Op.getNode()->hasOneUse())
1154 return false;
1155
1156 // Search for the smallest integer type with free casts to and from
1157 // Op's type. For expedience, just check power-of-2 integer types.
1158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1159 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1160 if (!isPowerOf2_32(SmallVTBits))
1161 SmallVTBits = NextPowerOf2(SmallVTBits);
1162 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1163 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1164 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1165 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1166 // We found a type with free casts.
1167 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1168 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1169 Op.getNode()->getOperand(0)),
1170 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1171 Op.getNode()->getOperand(1)));
1172 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1173 return CombineTo(Op, Z);
1174 }
1175 }
1176 return false;
1177}
1178
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1179/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1180/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1181/// use this information to simplify Op, create a new simplified DAG node and
1182/// return true, returning the original and new nodes in Old and New. Otherwise,
1183/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1184/// the expression (used to simplify the caller). The KnownZero/One bits may
1185/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1186bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1187 const APInt &DemandedMask,
1188 APInt &KnownZero,
1189 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1190 TargetLoweringOpt &TLO,
1191 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1192 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1193 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1194 "Mask size mismatches value type size!");
1195 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1196 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1197
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1198 // Don't know anything.
1199 KnownZero = KnownOne = APInt(BitWidth, 0);
1200
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1201 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1202 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1203 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1204 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1205 // simplify things downstream.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1206 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1207 return false;
1208 }
1209 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1210 // just set the NewMask to all bits.
1211 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1212 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1213 // Not demanding any bits from Op.
1214 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1215 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1216 return false;
1217 } else if (Depth == 6) { // Limit search depth.
1218 return false;
1219 }
1220
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1221 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1222 switch (Op.getOpcode()) {
1223 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1224 // We know all of the bits for a constant!
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1225 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1226 KnownZero = ~KnownOne;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1227 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1228 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1229 // If the RHS is a constant, check to see if the LHS would be zero without
1230 // using the bits from the RHS. Below, we use knowledge about the RHS to
1231 // simplify the LHS, here we're using information from the LHS to simplify
1232 // the RHS.
1233 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1234 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1235 // Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1236 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1237 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1238 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1239 return TLO.CombineTo(Op, Op.getOperand(0));
1240 // If any of the set bits in the RHS are known zero on the LHS, shrink
1241 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1242 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1243 return true;
1244 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1245
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1246 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1247 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1248 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1249 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1250 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1251 KnownZero2, KnownOne2, TLO, Depth+1))
1252 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1253 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1254
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1255 // If all of the demanded bits are known one on one side, return the other.
1256 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1257 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1258 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1259 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1260 return TLO.CombineTo(Op, Op.getOperand(1));
1261 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1262 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1263 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1264 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1265 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1266 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1267 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1268 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1269 return true;
1270
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1271 // Output known-1 bits are only known if set in both the LHS & RHS.
1272 KnownOne &= KnownOne2;
1273 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1274 KnownZero |= KnownZero2;
1275 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1276 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1277 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1278 KnownOne, TLO, Depth+1))
1279 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1280 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1281 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1282 KnownZero2, KnownOne2, TLO, Depth+1))
1283 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1284 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1285
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1286 // If all of the demanded bits are known zero on one side, return the other.
1287 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1288 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1289 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1290 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1291 return TLO.CombineTo(Op, Op.getOperand(1));
1292 // If all of the potentially set bits on one side are known to be set on
1293 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1294 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1295 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1296 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 return TLO.CombineTo(Op, Op.getOperand(1));
1298 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1299 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1300 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1301 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1302 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1303 return true;
1304
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1305 // Output known-0 bits are only known if clear in both the LHS & RHS.
1306 KnownZero &= KnownZero2;
1307 // Output known-1 are known to be set if set in either the LHS | RHS.
1308 KnownOne |= KnownOne2;
1309 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1310 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1311 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1312 KnownOne, TLO, Depth+1))
1313 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1314 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1315 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1316 KnownOne2, TLO, Depth+1))
1317 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1318 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1319
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1320 // If all of the demanded bits are known zero on one side, return the other.
1321 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1322 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1323 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1324 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1325 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1326 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1327 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1328 return true;
1329
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1330 // If all of the unknown bits are known to be zero on one side or the other
1331 // (but not both) turn this into an *inclusive* or.
1332 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1333 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1334 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1335 Op.getOperand(0),
1336 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1337
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1338 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1339 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1340 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1341 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1342
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1343 // If all of the demanded bits on one side are known, and all of the set
1344 // bits on that side are also known to be set on the other side, turn this
1345 // into an AND, as we know the bits will be cleared.
1346 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Joel Jonesd16ce172012-04-17 22:23:10 +0000[diff] [blame]1347 // NB: it is okay if more bits are known than are requested
1348 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1349 if (KnownOne == KnownOne2) { // set bits are the same on both sides
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1350 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1351 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1352 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1353 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1354 }
1355 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1356
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1357 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1358 // for XOR, we prefer to force bits to 1 if they will make a -1.
1359 // if we can't force bits, try to shrink constant
1360 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1361 APInt Expanded = C->getAPIntValue() | (~NewMask);
1362 // if we can expand it to have all bits set, do it
1363 if (Expanded.isAllOnesValue()) {
1364 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1365 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1366 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1367 TLO.DAG.getConstant(Expanded, VT));
1368 return TLO.CombineTo(Op, New);
1369 }
1370 // if it already has all the bits set, nothing to change
1371 // but don't shrink either!
1372 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1373 return true;
1374 }
1375 }
1376
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1377 KnownZero = KnownZeroOut;
1378 KnownOne = KnownOneOut;
1379 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1380 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1381 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1382 KnownOne, TLO, Depth+1))
1383 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1384 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1385 KnownOne2, TLO, Depth+1))
1386 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1387 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1388 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1389
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1390 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1391 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1392 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1393
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1394 // Only known if known in both the LHS and RHS.
1395 KnownOne &= KnownOne2;
1396 KnownZero &= KnownZero2;
1397 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1398 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1399 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1400 KnownOne, TLO, Depth+1))
1401 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1402 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1403 KnownOne2, TLO, Depth+1))
1404 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1405 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1406 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1407
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1408 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1409 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1410 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1411
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1412 // Only known if known in both the LHS and RHS.
1413 KnownOne &= KnownOne2;
1414 KnownZero &= KnownZero2;
1415 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1416 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1417 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1418 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1419 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1420
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1421 // If the shift count is an invalid immediate, don't do anything.
1422 if (ShAmt >= BitWidth)
1423 break;
1424
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1425 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1426 // single shift. We can do this if the bottom bits (which are shifted
1427 // out) are never demanded.
1428 if (InOp.getOpcode() == ISD::SRL &&
1429 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1430 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1431 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1432 unsigned Opc = ISD::SHL;
1433 int Diff = ShAmt-C1;
1434 if (Diff < 0) {
1435 Diff = -Diff;
1436 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1437 }
1438
1439 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1440 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1441 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1442 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1443 InOp.getOperand(0), NewSA));
1444 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1445 }
1446
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1447 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1448 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1449 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1450
1451 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1452 // are not demanded. This will likely allow the anyext to be folded away.
1453 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1454 SDValue InnerOp = InOp.getNode()->getOperand(0);
1455 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1456 unsigned InnerBits = InnerVT.getSizeInBits();
1457 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1458 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1459 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1460 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1461 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1462 SDValue NarrowShl =
1463 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1464 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1465 return
1466 TLO.CombineTo(Op,
1467 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1468 NarrowShl));
1469 }
1470 }
1471
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1472 KnownZero <<= SA->getZExtValue();
1473 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1474 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1475 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1476 }
1477 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1478 case ISD::SRL:
1479 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1480 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1481 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1482 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1483 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1484
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1485 // If the shift count is an invalid immediate, don't do anything.
1486 if (ShAmt >= BitWidth)
1487 break;
1488
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1489 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1490 // single shift. We can do this if the top bits (which are shifted out)
1491 // are never demanded.
1492 if (InOp.getOpcode() == ISD::SHL &&
1493 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1494 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1495 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1496 unsigned Opc = ISD::SRL;
1497 int Diff = ShAmt-C1;
1498 if (Diff < 0) {
1499 Diff = -Diff;
1500 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1501 }
1502
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1503 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1504 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1505 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1506 InOp.getOperand(0), NewSA));
1507 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1508 }
1509
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1510 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1511 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1512 KnownZero, KnownOne, TLO, Depth+1))
1513 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1514 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1515 KnownZero = KnownZero.lshr(ShAmt);
1516 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1517
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1518 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1519 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1520 }
1521 break;
1522 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1523 // If this is an arithmetic shift right and only the low-bit is set, we can
1524 // always convert this into a logical shr, even if the shift amount is
1525 // variable. The low bit of the shift cannot be an input sign bit unless
1526 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1527 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1528 return TLO.CombineTo(Op,
1529 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1530 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1531
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1532 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1533 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1534 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1535
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1536 // If the shift count is an invalid immediate, don't do anything.
1537 if (ShAmt >= BitWidth)
1538 break;
1539
1540 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1541
1542 // If any of the demanded bits are produced by the sign extension, we also
1543 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1544 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1545 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1546 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1547
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1548 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1549 KnownZero, KnownOne, TLO, Depth+1))
1550 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1551 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1552 KnownZero = KnownZero.lshr(ShAmt);
1553 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1554
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1555 // Handle the sign bit, adjusted to where it is now in the mask.
1556 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1557
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1558 // If the input sign bit is known to be zero, or if none of the top bits
1559 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1560 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1561 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1562 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1563 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1564 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1565 KnownOne |= HighBits;
1566 }
1567 }
1568 break;
1569 case ISD::SIGN_EXTEND_INREG: {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1570 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1571
1572 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1573 // If we only care about the highest bit, don't bother shifting right.
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1574 if (MsbMask == DemandedMask) {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1575 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1576 SDValue InOp = Op.getOperand(0);
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1577
1578 // Compute the correct shift amount type, which must be getShiftAmountTy
1579 // for scalar types after legalization.
1580 EVT ShiftAmtTy = Op.getValueType();
1581 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1582 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1583
1584 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1585 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1586 Op.getValueType(), InOp, ShiftAmt));
1587 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1588
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1589 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1590 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1591 APInt NewBits =
1592 APInt::getHighBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1593 BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1594
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1595 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1596 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1597 return TLO.CombineTo(Op, Op.getOperand(0));
1598
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1599 APInt InSignBit =
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1600 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1601 APInt InputDemandedBits =
1602 APInt::getLowBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1603 ExVT.getScalarType().getSizeInBits()) &
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1604 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1605
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1606 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1607 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1608 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1609
1610 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1611 KnownZero, KnownOne, TLO, Depth+1))
1612 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1613 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1614
1615 // If the sign bit of the input is known set or clear, then we know the
1616 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1617
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1618 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1619 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1620 return TLO.CombineTo(Op,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1621 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1622
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1623 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1624 KnownOne |= NewBits;
1625 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1626 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1627 KnownZero &= ~NewBits;
1628 KnownOne &= ~NewBits;
1629 }
1630 break;
1631 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1632 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1633 unsigned OperandBitWidth =
1634 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1635 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1636
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1637 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1638 APInt NewBits =
1639 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1640 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1641 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1642 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1643 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1644
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1645 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1646 KnownZero, KnownOne, TLO, Depth+1))
1647 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1648 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1649 KnownZero = KnownZero.zext(BitWidth);
1650 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1651 KnownZero |= NewBits;
1652 break;
1653 }
1654 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1655 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1656 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1657 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1658 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1659 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1660
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1661 // If none of the top bits are demanded, convert this into an any_extend.
1662 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1663 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1664 Op.getValueType(),
1665 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1666
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1667 // Since some of the sign extended bits are demanded, we know that the sign
1668 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1669 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1670 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1671 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1672
1673 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1674 KnownOne, TLO, Depth+1))
1675 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1676 KnownZero = KnownZero.zext(BitWidth);
1677 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1678
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1679 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1680 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1681 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1682 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1683 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1684
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1685 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1686 if (KnownOne.intersects(InSignBit)) {
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1687 KnownOne |= NewBits;
1688 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1689 } else { // Otherwise, top bits aren't known.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1690 assert((KnownOne & NewBits) == 0);
1691 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1692 }
1693 break;
1694 }
1695 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1696 unsigned OperandBitWidth =
1697 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1698 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1699 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1700 KnownZero, KnownOne, TLO, Depth+1))
1701 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1702 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1703 KnownZero = KnownZero.zext(BitWidth);
1704 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1705 break;
1706 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1707 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1708 // Simplify the input, using demanded bit information, and compute the known
1709 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1710 unsigned OperandBitWidth =
1711 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1712 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1713 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1714 KnownZero, KnownOne, TLO, Depth+1))
1715 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1716 KnownZero = KnownZero.trunc(BitWidth);
1717 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1718
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1719 // If the input is only used by this truncate, see if we can shrink it based
1720 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1721 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1722 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1723 switch (In.getOpcode()) {
1724 default: break;
1725 case ISD::SRL:
1726 // Shrink SRL by a constant if none of the high bits shifted in are
1727 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1728 if (TLO.LegalTypes() &&
1729 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1730 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1731 // undesirable.
1732 break;
1733 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1734 if (!ShAmt)
1735 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1736 SDValue Shift = In.getOperand(1);
1737 if (TLO.LegalTypes()) {
1738 uint64_t ShVal = ShAmt->getZExtValue();
1739 Shift =
1740 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1741 }
1742
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1743 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1744 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1745 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1746
1747 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1748 // None of the shifted in bits are needed. Add a truncate of the
1749 // shift input, then shift it.
1750 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1751 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1752 In.getOperand(0));
1753 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1754 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1755 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1756 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1757 }
1758 break;
1759 }
1760 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1761
1762 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1763 break;
1764 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1765 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1766 // AssertZext demands all of the high bits, plus any of the low bits
1767 // demanded by its users.
1768 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1769 APInt InMask = APInt::getLowBitsSet(BitWidth,
1770 VT.getSizeInBits());
1771 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1772 KnownZero, KnownOne, TLO, Depth+1))
1773 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1774 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1775
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1776 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1777 break;
1778 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1779 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1780 // If this is an FP->Int bitcast and if the sign bit is the only
1781 // thing demanded, turn this into a FGETSIGN.
Eli Friedmanca072a32011-12-15 02:07:20 +0000[diff] [blame]1782 if (!TLO.LegalOperations() &&
1783 !Op.getValueType().isVector() &&
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1784 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1785 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1786 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1787 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1788 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1789 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1790 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1791 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1792 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1793 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1794 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1795 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1796 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1797 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1798 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1799 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1800 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1801 Sign, ShAmt));
1802 }
1803 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1804 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1805 case ISD::ADD:
1806 case ISD::MUL:
1807 case ISD::SUB: {
1808 // Add, Sub, and Mul don't demand any bits in positions beyond that
1809 // of the highest bit demanded of them.
1810 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1811 BitWidth - NewMask.countLeadingZeros());
1812 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1813 KnownOne2, TLO, Depth+1))
1814 return true;
1815 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1816 KnownOne2, TLO, Depth+1))
1817 return true;
1818 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1819 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1820 return true;
1821 }
1822 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1823 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1824 // Just use ComputeMaskedBits to compute output bits.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1825 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1826 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1827 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1828
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1829 // If we know the value of all of the demanded bits, return this as a
1830 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1831 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1832 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1833
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1834 return false;
1835}
1836
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1837/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1838/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1839/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1840void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1841 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1842 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1843 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1844 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1845 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1846 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1847 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1848 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1849 "Should use MaskedValueIsZero if you don't know whether Op"
1850 " is a target node!");
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1851 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1852}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1853
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1854/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1855/// targets that want to expose additional information about sign bits to the
1856/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1857unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1858 unsigned Depth) const {
1859 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1860 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1861 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1862 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1863 "Should use ComputeNumSignBits if you don't know whether Op"
1864 " is a target node!");
1865 return 1;
1866}
1867
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1868/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1869/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1870/// determine which bit is set.
1871///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1872static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1873 // A left-shift of a constant one will have exactly one bit set, because
1874 // shifting the bit off the end is undefined.
1875 if (Val.getOpcode() == ISD::SHL)
1876 if (ConstantSDNode *C =
1877 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1878 if (C->getAPIntValue() == 1)
1879 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1880
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1881 // Similarly, a right-shift of a constant sign-bit will have exactly
1882 // one bit set.
1883 if (Val.getOpcode() == ISD::SRL)
1884 if (ConstantSDNode *C =
1885 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1886 if (C->getAPIntValue().isSignBit())
1887 return true;
1888
1889 // More could be done here, though the above checks are enough
1890 // to handle some common cases.
1891
1892 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1893 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1894 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1895 APInt KnownZero, KnownOne;
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1896 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1897 return (KnownZero.countPopulation() == BitWidth - 1) &&
1898 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1899}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1900
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1901/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1902/// and cc. If it is unable to simplify it, return a null SDValue.
1903SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1904TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1905 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1906 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1907 SelectionDAG &DAG = DCI.DAG;
1908
1909 // These setcc operations always fold.
1910 switch (Cond) {
1911 default: break;
1912 case ISD::SETFALSE:
1913 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1914 case ISD::SETTRUE:
1915 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1916 }
1917
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1918 // Ensure that the constant occurs on the RHS, and fold constant
1919 // comparisons.
1920 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1921 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1922
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1923 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1924 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1925
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1926 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1927 // equality comparison, then we're just comparing whether X itself is
1928 // zero.
1929 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1930 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1931 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1932 const APInt &ShAmt
1933 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1934 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1935 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1936 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1937 // (srl (ctlz x), 5) == 0 -> X != 0
1938 // (srl (ctlz x), 5) != 1 -> X != 0
1939 Cond = ISD::SETNE;
1940 } else {
1941 // (srl (ctlz x), 5) != 0 -> X == 0
1942 // (srl (ctlz x), 5) == 1 -> X == 0
1943 Cond = ISD::SETEQ;
1944 }
1945 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1946 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1947 Zero, Cond);
1948 }
1949 }
1950
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1951 SDValue CTPOP = N0;
1952 // Look through truncs that don't change the value of a ctpop.
1953 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1954 CTPOP = N0.getOperand(0);
1955
1956 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1957 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1958 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1959 EVT CTVT = CTPOP.getValueType();
1960 SDValue CTOp = CTPOP.getOperand(0);
1961
1962 // (ctpop x) u< 2 -> (x & x-1) == 0
1963 // (ctpop x) u> 1 -> (x & x-1) != 0
1964 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1965 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1966 DAG.getConstant(1, CTVT));
1967 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1968 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1969 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1970 }
1971
1972 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1973 }
1974
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]1975 // (zext x) == C --> x == (trunc C)
1976 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1977 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1978 unsigned MinBits = N0.getValueSizeInBits();
1979 SDValue PreZExt;
1980 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1981 // ZExt
1982 MinBits = N0->getOperand(0).getValueSizeInBits();
1983 PreZExt = N0->getOperand(0);
1984 } else if (N0->getOpcode() == ISD::AND) {
1985 // DAGCombine turns costly ZExts into ANDs
1986 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1987 if ((C->getAPIntValue()+1).isPowerOf2()) {
1988 MinBits = C->getAPIntValue().countTrailingOnes();
1989 PreZExt = N0->getOperand(0);
1990 }
1991 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1992 // ZEXTLOAD
1993 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1994 MinBits = LN0->getMemoryVT().getSizeInBits();
1995 PreZExt = N0;
1996 }
1997 }
1998
Benjamin Kramerd9b0b022012-06-02 10:20:22 +0000[diff] [blame]1999 // Make sure we're not losing bits from the constant.
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]2000 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2001 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2002 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2003 // Will get folded away.
2004 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2005 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2006 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2007 }
2008 }
2009 }
2010
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2011 // If the LHS is '(and load, const)', the RHS is 0,
2012 // the test is for equality or unsigned, and all 1 bits of the const are
2013 // in the same partial word, see if we can shorten the load.
2014 if (DCI.isBeforeLegalize() &&
2015 N0.getOpcode() == ISD::AND && C1 == 0 &&
2016 N0.getNode()->hasOneUse() &&
2017 isa<LoadSDNode>(N0.getOperand(0)) &&
2018 N0.getOperand(0).getNode()->hasOneUse() &&
2019 isa<ConstantSDNode>(N0.getOperand(1))) {
2020 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2021 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2022 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2023 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2024 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2025 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2026 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2027 // 8 bits, but have to be careful...
2028 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2029 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2030 const APInt &Mask =
2031 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2032 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2033 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2034 for (unsigned offset=0; offset<origWidth/width; offset++) {
2035 if ((newMask & Mask) == Mask) {
2036 if (!TD->isLittleEndian())
2037 bestOffset = (origWidth/width - offset - 1) * (width/8);
2038 else
2039 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2040 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2041 bestWidth = width;
2042 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2043 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2044 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2045 }
2046 }
2047 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2048 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2049 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2050 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2051 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2052 SDValue Ptr = Lod->getBasePtr();
2053 if (bestOffset != 0)
2054 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2055 DAG.getConstant(bestOffset, PtrType));
2056 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2057 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2058 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2059 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2060 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2061 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2062 DAG.getConstant(bestMask.trunc(bestWidth),
2063 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2064 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2065 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2066 }
2067 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2068
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2069 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2070 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2071 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2072
2073 // If the comparison constant has bits in the upper part, the
2074 // zero-extended value could never match.
2075 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2076 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2077 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2078 case ISD::SETUGT:
2079 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2080 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2081 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2082 case ISD::SETULE:
2083 case ISD::SETNE: return DAG.getConstant(1, VT);
2084 case ISD::SETGT:
2085 case ISD::SETGE:
2086 // True if the sign bit of C1 is set.
2087 return DAG.getConstant(C1.isNegative(), VT);
2088 case ISD::SETLT:
2089 case ISD::SETLE:
2090 // True if the sign bit of C1 isn't set.
2091 return DAG.getConstant(C1.isNonNegative(), VT);
2092 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2093 break;
2094 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2095 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2096
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2097 // Otherwise, we can perform the comparison with the low bits.
2098 switch (Cond) {
2099 case ISD::SETEQ:
2100 case ISD::SETNE:
2101 case ISD::SETUGT:
2102 case ISD::SETUGE:
2103 case ISD::SETULT:
2104 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2105 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2106 if (DCI.isBeforeLegalizeOps() ||
2107 (isOperationLegal(ISD::SETCC, newVT) &&
2108 getCondCodeAction(Cond, newVT)==Legal))
2109 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2110 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2111 Cond);
2112 break;
2113 }
2114 default:
2115 break; // todo, be more careful with signed comparisons
2116 }
2117 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2118 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2119 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2120 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2121 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2122 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2123
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2124 // If the constant doesn't fit into the number of bits for the source of
2125 // the sign extension, it is impossible for both sides to be equal.
2126 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2127 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2128
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2129 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2130 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2131 if (Op0Ty == ExtSrcTy) {
2132 ZextOp = N0.getOperand(0);
2133 } else {
2134 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2135 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2136 DAG.getConstant(Imm, Op0Ty));
2137 }
2138 if (!DCI.isCalledByLegalizer())
2139 DCI.AddToWorklist(ZextOp.getNode());
2140 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2141 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2142 DAG.getConstant(C1 & APInt::getLowBitsSet(
2143 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2144 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2145 ExtDstTy),
2146 Cond);
2147 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2148 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2149 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2150 if (N0.getOpcode() == ISD::SETCC &&
2151 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2152 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2153 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2154 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2155 // Invert the condition.
2156 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2157 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2158 N0.getOperand(0).getValueType().isInteger());
2159 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2160 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2161
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2162 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2163 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2164 N0.getOperand(0).getOpcode() == ISD::XOR &&
2165 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2166 isa<ConstantSDNode>(N0.getOperand(1)) &&
2167 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2168 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2169 // can only do this if the top bits are known zero.
2170 unsigned BitWidth = N0.getValueSizeInBits();
2171 if (DAG.MaskedValueIsZero(N0,
2172 APInt::getHighBitsSet(BitWidth,
2173 BitWidth-1))) {
2174 // Okay, get the un-inverted input value.
2175 SDValue Val;
2176 if (N0.getOpcode() == ISD::XOR)
2177 Val = N0.getOperand(0);
2178 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2179 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2180 N0.getOperand(0).getOpcode() == ISD::XOR);
2181 // ((X^1)&1)^1 -> X & 1
2182 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2183 N0.getOperand(0).getOperand(0),
2184 N0.getOperand(1));
2185 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2186
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2187 return DAG.getSetCC(dl, VT, Val, N1,
2188 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2189 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2190 } else if (N1C->getAPIntValue() == 1 &&
2191 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2192 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2193 SDValue Op0 = N0;
2194 if (Op0.getOpcode() == ISD::TRUNCATE)
2195 Op0 = Op0.getOperand(0);
2196
2197 if ((Op0.getOpcode() == ISD::XOR) &&
2198 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2199 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2200 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2201 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2202 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2203 Cond);
2204 } else if (Op0.getOpcode() == ISD::AND &&
2205 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2206 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2207 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2208 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2209 Op0 = DAG.getNode(ISD::AND, dl, VT,
2210 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2211 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2212 else if (Op0.getValueType().bitsLT(VT))
2213 Op0 = DAG.getNode(ISD::AND, dl, VT,
2214 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2215 DAG.getConstant(1, VT));
2216
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2217 return DAG.getSetCC(dl, VT, Op0,
2218 DAG.getConstant(0, Op0.getValueType()),
2219 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2220 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2221 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2222 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2223
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2224 APInt MinVal, MaxVal;
2225 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2226 if (ISD::isSignedIntSetCC(Cond)) {
2227 MinVal = APInt::getSignedMinValue(OperandBitSize);
2228 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2229 } else {
2230 MinVal = APInt::getMinValue(OperandBitSize);
2231 MaxVal = APInt::getMaxValue(OperandBitSize);
2232 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2233
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2234 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2235 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2236 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2237 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2238 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2239 DAG.getConstant(C1-1, N1.getValueType()),
2240 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2241 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2242
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2243 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2244 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2245 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2246 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2247 DAG.getConstant(C1+1, N1.getValueType()),
2248 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2249 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2250
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2251 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2252 return DAG.getConstant(0, VT); // X < MIN --> false
2253 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2254 return DAG.getConstant(1, VT); // X >= MIN --> true
2255 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2256 return DAG.getConstant(0, VT); // X > MAX --> false
2257 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2258 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2259
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2260 // Canonicalize setgt X, Min --> setne X, Min
2261 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2262 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2263 // Canonicalize setlt X, Max --> setne X, Max
2264 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2265 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2266
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2267 // If we have setult X, 1, turn it into seteq X, 0
2268 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2269 return DAG.getSetCC(dl, VT, N0,
2270 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2271 ISD::SETEQ);
2272 // If we have setugt X, Max-1, turn it into seteq X, Max
2273 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2274 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2275 DAG.getConstant(MaxVal, N0.getValueType()),
2276 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2277
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2278 // If we have "setcc X, C0", check to see if we can shrink the immediate
2279 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2280
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2281 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2282 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2283 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2284 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2285 DAG.getConstant(0, N1.getValueType()),
2286 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2287
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2288 // SETULT X, SINTMIN -> SETGT X, -1
2289 if (Cond == ISD::SETULT &&
2290 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2291 SDValue ConstMinusOne =
2292 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2293 N1.getValueType());
2294 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2295 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2296
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2297 // Fold bit comparisons when we can.
2298 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2299 (VT == N0.getValueType() ||
2300 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2301 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2302 if (ConstantSDNode *AndRHS =
2303 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2304 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2305 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2306 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2307 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2308 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2309 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2310 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2311 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2312 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2313 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2314 // (X & 8) == 8 --> (X & 8) >> 3
2315 // Perform the xform if C1 is a single bit.
2316 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2317 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2318 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2319 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2320 }
2321 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2322 }
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2323
Evan Chengb4d49592012-07-17 07:47:50 +0000[diff] [blame]2324 if (C1.getMinSignedBits() <= 64 &&
2325 !isLegalICmpImmediate(C1.getSExtValue())) {
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2326 // (X & -256) == 256 -> (X >> 8) == 1
2327 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2328 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2329 if (ConstantSDNode *AndRHS =
2330 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2331 const APInt &AndRHSC = AndRHS->getAPIntValue();
2332 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2333 unsigned ShiftBits = AndRHSC.countTrailingZeros();
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2334 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2335 getPointerTy() : getShiftAmountTy(N0.getValueType());
2336 EVT CmpTy = N0.getValueType();
2337 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2338 DAG.getConstant(ShiftBits, ShiftTy));
2339 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2340 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2341 }
2342 }
Evan Chengf5c05392012-07-17 08:31:11 +0000[diff] [blame]2343 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2344 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2345 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2346 // X < 0x100000000 -> (X >> 32) < 1
2347 // X >= 0x100000000 -> (X >> 32) >= 1
2348 // X <= 0x0ffffffff -> (X >> 32) < 1
2349 // X > 0x0ffffffff -> (X >> 32) >= 1
2350 unsigned ShiftBits;
2351 APInt NewC = C1;
2352 ISD::CondCode NewCond = Cond;
2353 if (AdjOne) {
2354 ShiftBits = C1.countTrailingOnes();
2355 NewC = NewC + 1;
2356 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2357 } else {
2358 ShiftBits = C1.countTrailingZeros();
2359 }
2360 NewC = NewC.lshr(ShiftBits);
2361 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2362 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Evan Chengf5c05392012-07-17 08:31:11 +0000[diff] [blame]2363 getPointerTy() : getShiftAmountTy(N0.getValueType());
2364 EVT CmpTy = N0.getValueType();
2365 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2366 DAG.getConstant(ShiftBits, ShiftTy));
2367 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2368 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2369 }
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2370 }
2371 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2372 }
2373
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2374 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2375 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2376 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2377 if (O.getNode()) return O;
2378 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2379 // If the RHS of an FP comparison is a constant, simplify it away in
2380 // some cases.
2381 if (CFP->getValueAPF().isNaN()) {
2382 // If an operand is known to be a nan, we can fold it.
2383 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2384 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2385 case 0: // Known false.
2386 return DAG.getConstant(0, VT);
2387 case 1: // Known true.
2388 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2389 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2390 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2391 }
2392 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2393
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2394 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2395 // constant if knowing that the operand is non-nan is enough. We prefer to
2396 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2397 // materialize 0.0.
2398 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2399 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2400
2401 // If the condition is not legal, see if we can find an equivalent one
2402 // which is legal.
2403 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2404 // If the comparison was an awkward floating-point == or != and one of
2405 // the comparison operands is infinity or negative infinity, convert the
2406 // condition to a less-awkward <= or >=.
2407 if (CFP->getValueAPF().isInfinity()) {
2408 if (CFP->getValueAPF().isNegative()) {
2409 if (Cond == ISD::SETOEQ &&
2410 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2411 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2412 if (Cond == ISD::SETUEQ &&
2413 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2414 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2415 if (Cond == ISD::SETUNE &&
2416 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2417 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2418 if (Cond == ISD::SETONE &&
2419 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2420 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2421 } else {
2422 if (Cond == ISD::SETOEQ &&
2423 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2424 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2425 if (Cond == ISD::SETUEQ &&
2426 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2427 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2428 if (Cond == ISD::SETUNE &&
2429 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2430 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2431 if (Cond == ISD::SETONE &&
2432 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2433 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2434 }
2435 }
2436 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2437 }
2438
2439 if (N0 == N1) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2440 // The sext(setcc()) => setcc() optimization relies on the appropriate
2441 // constant being emitted.
Nadav Roteme7576402012-09-06 11:13:55 +0000[diff] [blame]2442 uint64_t EqVal = 0;
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2443 switch (getBooleanContents(N0.getValueType().isVector())) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2444 case UndefinedBooleanContent:
2445 case ZeroOrOneBooleanContent:
2446 EqVal = ISD::isTrueWhenEqual(Cond);
2447 break;
2448 case ZeroOrNegativeOneBooleanContent:
2449 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2450 break;
2451 }
2452
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2453 // We can always fold X == X for integer setcc's.
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2454 if (N0.getValueType().isInteger()) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2455 return DAG.getConstant(EqVal, VT);
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2456 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2457 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2458 if (UOF == 2) // FP operators that are undefined on NaNs.
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2459 return DAG.getConstant(EqVal, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2460 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2461 return DAG.getConstant(EqVal, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2462 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2463 // if it is not already.
2464 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
Micah Villmow8c574be2012-07-31 18:07:43 +0000[diff] [blame]2465 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2466 getCondCodeAction(NewCond, N0.getValueType()) == Legal))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2467 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2468 }
2469
2470 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2471 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2472 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2473 N0.getOpcode() == ISD::XOR) {
2474 // Simplify (X+Y) == (X+Z) --> Y == Z
2475 if (N0.getOpcode() == N1.getOpcode()) {
2476 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2477 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2478 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2479 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2480 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2481 // If X op Y == Y op X, try other combinations.
2482 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2483 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2484 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2485 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2486 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2487 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2488 }
2489 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2490
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2491 // If RHS is a legal immediate value for a compare instruction, we need
2492 // to be careful about increasing register pressure needlessly.
2493 bool LegalRHSImm = false;
2494
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2495 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2496 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2497 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2498 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2499 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2500 DAG.getConstant(RHSC->getAPIntValue()-
2501 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2502 N0.getValueType()), Cond);
2503 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2504
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2505 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2506 if (N0.getOpcode() == ISD::XOR)
2507 // If we know that all of the inverted bits are zero, don't bother
2508 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2509 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2510 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2511 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2512 DAG.getConstant(LHSR->getAPIntValue() ^
2513 RHSC->getAPIntValue(),
2514 N0.getValueType()),
2515 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2516 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2517
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2518 // Turn (C1-X) == C2 --> X == C1-C2
2519 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2520 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2521 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2522 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2523 DAG.getConstant(SUBC->getAPIntValue() -
2524 RHSC->getAPIntValue(),
2525 N0.getValueType()),
2526 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2527 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2528 }
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2529
2530 // Could RHSC fold directly into a compare?
2531 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2532 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2533 }
2534
2535 // Simplify (X+Z) == X --> Z == 0
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2536 // Don't do this if X is an immediate that can fold into a cmp
2537 // instruction and X+Z has other uses. It could be an induction variable
2538 // chain, and the transform would increase register pressure.
2539 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2540 if (N0.getOperand(0) == N1)
2541 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2542 DAG.getConstant(0, N0.getValueType()), Cond);
2543 if (N0.getOperand(1) == N1) {
2544 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2545 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2546 DAG.getConstant(0, N0.getValueType()), Cond);
2547 else if (N0.getNode()->hasOneUse()) {
2548 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2549 // (Z-X) == X --> Z == X<<1
2550 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2551 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2552 if (!DCI.isCalledByLegalizer())
2553 DCI.AddToWorklist(SH.getNode());
2554 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2555 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2556 }
2557 }
2558 }
2559
2560 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2561 N1.getOpcode() == ISD::XOR) {
2562 // Simplify X == (X+Z) --> Z == 0
2563 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2564 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2565 DAG.getConstant(0, N1.getValueType()), Cond);
2566 } else if (N1.getOperand(1) == N0) {
2567 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2568 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2569 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2570 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2571 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2572 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2573 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2574 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2575 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2576 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2577 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2578 }
2579 }
2580 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2581
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2582 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2583 // Note that where y is variable and is known to have at most
2584 // one bit set (for example, if it is z&1) we cannot do this;
2585 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2586 if (N0.getOpcode() == ISD::AND)
2587 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2588 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2589 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2590 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2591 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2592 }
2593 }
2594 if (N1.getOpcode() == ISD::AND)
2595 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2596 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2597 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2598 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2599 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2600 }
2601 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2602 }
2603
2604 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2605 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2606 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2607 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2608 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2609 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2610 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2611 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2612 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2613 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2614 break;
2615 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2616 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2617 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2618 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2619 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2620 Temp = DAG.getNOT(dl, N0, MVT::i1);
2621 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2622 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2623 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2624 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2625 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2626 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2627 Temp = DAG.getNOT(dl, N1, MVT::i1);
2628 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2629 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2630 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2631 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2632 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2633 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2634 Temp = DAG.getNOT(dl, N0, MVT::i1);
2635 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2636 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2637 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2638 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2639 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2640 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2641 Temp = DAG.getNOT(dl, N1, MVT::i1);
2642 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2643 break;
2644 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2645 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2646 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2647 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2648 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2649 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2650 }
2651 return N0;
2652 }
2653
2654 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2655 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2656}
2657
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2658/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2659/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2660bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2661 int64_t &Offset) const {
2662 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2663 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2664 GA = GASD->getGlobal();
2665 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2666 return true;
2667 }
2668
2669 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2670 SDValue N1 = N->getOperand(0);
2671 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2672 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2673 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2674 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2675 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2676 return true;
2677 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2678 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2679 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2680 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2681 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2682 return true;
2683 }
2684 }
2685 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2686
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2687 return false;
2688}
2689
2690
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2691SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2692PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2693 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2694 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2695}
2696
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2697//===----------------------------------------------------------------------===//
2698// Inline Assembler Implementation Methods
2699//===----------------------------------------------------------------------===//
2700
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2701
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2702TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2703TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2704 if (Constraint.size() == 1) {
2705 switch (Constraint[0]) {
2706 default: break;
2707 case 'r': return C_RegisterClass;
2708 case 'm': // memory
2709 case 'o': // offsetable
2710 case 'V': // not offsetable
2711 return C_Memory;
2712 case 'i': // Simple Integer or Relocatable Constant
2713 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2714 case 'E': // Floating Point Constant
2715 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2716 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2717 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2718 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2719 case 'I': // Target registers.
2720 case 'J':
2721 case 'K':
2722 case 'L':
2723 case 'M':
2724 case 'N':
2725 case 'O':
2726 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2727 case '<':
2728 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2729 return C_Other;
2730 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2731 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2732
2733 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2734 Constraint[Constraint.size()-1] == '}')
2735 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2736 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2737}
2738
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2739/// LowerXConstraint - try to replace an X constraint, which matches anything,
2740/// with another that has more specific requirements based on the type of the
2741/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2742const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2743 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2744 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2745 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2746 return "f"; // works for many targets
2747 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2748}
2749
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2750/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2751/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2752void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2753 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2754 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2755 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2756
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2757 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2758
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2759 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2760 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2761 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2762 case 'X': // Allows any operand; labels (basic block) use this.
2763 if (Op.getOpcode() == ISD::BasicBlock) {
2764 Ops.push_back(Op);
2765 return;
2766 }
2767 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2768 case 'i': // Simple Integer or Relocatable Constant
2769 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2770 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2771 // These operands are interested in values of the form (GV+C), where C may
2772 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2773 // is possible and fine if either GV or C are missing.
2774 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2775 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2776
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2777 // If we have "(add GV, C)", pull out GV/C
2778 if (Op.getOpcode() == ISD::ADD) {
2779 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2780 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2781 if (C == 0 || GA == 0) {
2782 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2783 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2784 }
2785 if (C == 0 || GA == 0)
2786 C = 0, GA = 0;
2787 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2788
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2789 // If we find a valid operand, map to the TargetXXX version so that the
2790 // value itself doesn't get selected.
2791 if (GA) { // Either &GV or &GV+C
2792 if (ConstraintLetter != 'n') {
2793 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2794 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2795 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2796 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2797 Op.getValueType(), Offs));
2798 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2799 }
2800 }
2801 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2802 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2803 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2804 // gcc prints these as sign extended. Sign extend value to 64 bits
2805 // now; without this it would get ZExt'd later in
2806 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2807 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2808 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2809 return;
2810 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2811 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2812 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2813 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2814 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2815}
2816
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2817std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2818getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2819 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2820 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2821 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2822 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2823
2824 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2825 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2826
2827 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2828 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2829 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2830 E = RI->regclass_end(); RCI != E; ++RCI) {
2831 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2832
2833 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2834 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]2835 if (!isLegalRC(RC))
2836 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2837
2838 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2839 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2840 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2841 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2842 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2843 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2844
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2845 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2846}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2847
2848//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2849// Constraint Selection.
2850
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2851/// isMatchingInputConstraint - Return true of this is an input operand that is
2852/// a matching constraint like "4".
2853bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2854 assert(!ConstraintCode.empty() && "No known constraint!");
2855 return isdigit(ConstraintCode[0]);
2856}
2857
2858/// getMatchedOperand - If this is an input matching constraint, this method
2859/// returns the output operand it matches.
2860unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2861 assert(!ConstraintCode.empty() && "No known constraint!");
2862 return atoi(ConstraintCode.c_str());
2863}
2864
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2865
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2866/// ParseConstraints - Split up the constraint string from the inline
2867/// assembly value into the specific constraints and their prefixes,
2868/// and also tie in the associated operand values.
2869/// If this returns an empty vector, and if the constraint string itself
2870/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2871TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2872 ImmutableCallSite CS) const {
2873 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2874 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2875 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2876 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2877
2878 // Do a prepass over the constraints, canonicalizing them, and building up the
2879 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2880 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2881 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2882
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2883 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2884 unsigned ResNo = 0; // ResNo - The result number of the next output.
2885
2886 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2887 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2888 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2889
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2890 // Update multiple alternative constraint count.
2891 if (OpInfo.multipleAlternatives.size() > maCount)
2892 maCount = OpInfo.multipleAlternatives.size();
2893
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2894 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2895
2896 // Compute the value type for each operand.
2897 switch (OpInfo.Type) {
2898 case InlineAsm::isOutput:
2899 // Indirect outputs just consume an argument.
2900 if (OpInfo.isIndirect) {
2901 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2902 break;
2903 }
2904
2905 // The return value of the call is this value. As such, there is no
2906 // corresponding argument.
2907 assert(!CS.getType()->isVoidTy() &&
2908 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2909 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2910 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2911 } else {
2912 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2913 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2914 }
2915 ++ResNo;
2916 break;
2917 case InlineAsm::isInput:
2918 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2919 break;
2920 case InlineAsm::isClobber:
2921 // Nothing to do.
2922 break;
2923 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2924
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2925 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2926 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2927 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2928 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2929 if (!PtrTy)
2930 report_fatal_error("Indirect operand for inline asm not a pointer!");
2931 OpTy = PtrTy->getElementType();
2932 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2933
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2934 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2935 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2936 if (STy->getNumElements() == 1)
2937 OpTy = STy->getElementType(0);
2938
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2939 // If OpTy is not a single value, it may be a struct/union that we
2940 // can tile with integers.
2941 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2942 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2943 switch (BitSize) {
2944 default: break;
2945 case 1:
2946 case 8:
2947 case 16:
2948 case 32:
2949 case 64:
2950 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2951 OpInfo.ConstraintVT =
2952 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2953 break;
2954 }
2955 } else if (dyn_cast<PointerType>(OpTy)) {
2956 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2957 } else {
2958 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2959 }
2960 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2961 }
2962
2963 // If we have multiple alternative constraints, select the best alternative.
2964 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2965 if (maCount) {
2966 unsigned bestMAIndex = 0;
2967 int bestWeight = -1;
2968 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2969 int weight = -1;
2970 unsigned maIndex;
2971 // Compute the sums of the weights for each alternative, keeping track
2972 // of the best (highest weight) one so far.
2973 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2974 int weightSum = 0;
2975 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2976 cIndex != eIndex; ++cIndex) {
2977 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2978 if (OpInfo.Type == InlineAsm::isClobber)
2979 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2980
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2981 // If this is an output operand with a matching input operand,
2982 // look up the matching input. If their types mismatch, e.g. one
2983 // is an integer, the other is floating point, or their sizes are
2984 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2985 if (OpInfo.hasMatchingInput()) {
2986 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2987 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2988 if ((OpInfo.ConstraintVT.isInteger() !=
2989 Input.ConstraintVT.isInteger()) ||
2990 (OpInfo.ConstraintVT.getSizeInBits() !=
2991 Input.ConstraintVT.getSizeInBits())) {
2992 weightSum = -1; // Can't match.
2993 break;
2994 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2995 }
2996 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2997 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2998 if (weight == -1) {
2999 weightSum = -1;
3000 break;
3001 }
3002 weightSum += weight;
3003 }
3004 // Update best.
3005 if (weightSum > bestWeight) {
3006 bestWeight = weightSum;
3007 bestMAIndex = maIndex;
3008 }
3009 }
3010
3011 // Now select chosen alternative in each constraint.
3012 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3013 cIndex != eIndex; ++cIndex) {
3014 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3015 if (cInfo.Type == InlineAsm::isClobber)
3016 continue;
3017 cInfo.selectAlternative(bestMAIndex);
3018 }
3019 }
3020 }
3021
3022 // Check and hook up tied operands, choose constraint code to use.
3023 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3024 cIndex != eIndex; ++cIndex) {
3025 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3026
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3027 // If this is an output operand with a matching input operand, look up the
3028 // matching input. If their types mismatch, e.g. one is an integer, the
3029 // other is floating point, or their sizes are different, flag it as an
3030 // error.
3031 if (OpInfo.hasMatchingInput()) {
3032 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3033
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3034 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Bill Wendling96cb1122012-07-19 00:04:14 +0000[diff] [blame]3035 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3036 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3037 OpInfo.ConstraintVT);
3038 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3039 getRegForInlineAsmConstraint(Input.ConstraintCode,
3040 Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3041 if ((OpInfo.ConstraintVT.isInteger() !=
3042 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]3043 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3044 report_fatal_error("Unsupported asm: input constraint"
3045 " with a matching output constraint of"
3046 " incompatible type!");
3047 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3048 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3049
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3050 }
3051 }
3052
3053 return ConstraintOperands;
3054}
3055
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3056
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3057/// getConstraintGenerality - Return an integer indicating how general CT
3058/// is.
3059static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3060 switch (CT) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3061 case TargetLowering::C_Other:
3062 case TargetLowering::C_Unknown:
3063 return 0;
3064 case TargetLowering::C_Register:
3065 return 1;
3066 case TargetLowering::C_RegisterClass:
3067 return 2;
3068 case TargetLowering::C_Memory:
3069 return 3;
3070 }
Chandler Carruth732f05c2012-01-10 18:08:01 +0000[diff] [blame]3071 llvm_unreachable("Invalid constraint type");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3072}
3073
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3074/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3075/// This object must already have been set up with the operand type
3076/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3077TargetLowering::ConstraintWeight
3078 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3079 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3080 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3081 if (maIndex >= (int)info.multipleAlternatives.size())
3082 rCodes = &info.Codes;
3083 else
3084 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3085 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3086
3087 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3088 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3089 ConstraintWeight weight =
3090 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3091 if (weight > BestWeight)
3092 BestWeight = weight;
3093 }
3094
3095 return BestWeight;
3096}
3097
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3098/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3099/// This object must already have been set up with the operand type
3100/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3101TargetLowering::ConstraintWeight
3102 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3103 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3104 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3105 Value *CallOperandVal = info.CallOperandVal;
3106 // If we don't have a value, we can't do a match,
3107 // but allow it at the lowest weight.
3108 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3109 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3110 // Look at the constraint type.
3111 switch (*constraint) {
3112 case 'i': // immediate integer.
3113 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3114 if (isa<ConstantInt>(CallOperandVal))
3115 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3116 break;
3117 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3118 if (isa<GlobalValue>(CallOperandVal))
3119 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3120 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3121 case 'E': // immediate float if host format.
3122 case 'F': // immediate float.
3123 if (isa<ConstantFP>(CallOperandVal))
3124 weight = CW_Constant;
3125 break;
3126 case '<': // memory operand with autodecrement.
3127 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3128 case 'm': // memory operand.
3129 case 'o': // offsettable memory operand
3130 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3131 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3132 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3133 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3134 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3135 // note: Clang converts "g" to "imr".
3136 if (CallOperandVal->getType()->isIntegerTy())
3137 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3138 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3139 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3140 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3141 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3142 break;
3143 }
3144 return weight;
3145}
3146
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3147/// ChooseConstraint - If there are multiple different constraints that we
3148/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3149/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3150/// Other -> immediates and magic values
3151/// Register -> one specific register
3152/// RegisterClass -> a group of regs
3153/// Memory -> memory
3154/// Ideally, we would pick the most specific constraint possible: if we have
3155/// something that fits into a register, we would pick it. The problem here
3156/// is that if we have something that could either be in a register or in
3157/// memory that use of the register could cause selection of *other*
3158/// operands to fail: they might only succeed if we pick memory. Because of
3159/// this the heuristic we use is:
3160///
3161/// 1) If there is an 'other' constraint, and if the operand is valid for
3162/// that constraint, use it. This makes us take advantage of 'i'
3163/// constraints when available.
3164/// 2) Otherwise, pick the most general constraint present. This prefers
3165/// 'm' over 'r', for example.
3166///
3167static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3168 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3169 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3170 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3171 unsigned BestIdx = 0;
3172 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3173 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3174
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3175 // Loop over the options, keeping track of the most general one.
3176 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3177 TargetLowering::ConstraintType CType =
3178 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3179
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3180 // If this is an 'other' constraint, see if the operand is valid for it.
3181 // For example, on X86 we might have an 'rI' constraint. If the operand
3182 // is an integer in the range [0..31] we want to use I (saving a load
3183 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3184 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3185 assert(OpInfo.Codes[i].size() == 1 &&
3186 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3187 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3188 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3189 ResultOps, *DAG);
3190 if (!ResultOps.empty()) {
3191 BestType = CType;
3192 BestIdx = i;
3193 break;
3194 }
3195 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3196
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3197 // Things with matching constraints can only be registers, per gcc
3198 // documentation. This mainly affects "g" constraints.
3199 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3200 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3201
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3202 // This constraint letter is more general than the previous one, use it.
3203 int Generality = getConstraintGenerality(CType);
3204 if (Generality > BestGenerality) {
3205 BestType = CType;
3206 BestIdx = i;
3207 BestGenerality = Generality;
3208 }
3209 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3210
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3211 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3212 OpInfo.ConstraintType = BestType;
3213}
3214
3215/// ComputeConstraintToUse - Determines the constraint code and constraint
3216/// type to use for the specific AsmOperandInfo, setting
3217/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3218void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3219 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3220 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3221 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3222
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3223 // Single-letter constraints ('r') are very common.
3224 if (OpInfo.Codes.size() == 1) {
3225 OpInfo.ConstraintCode = OpInfo.Codes[0];
3226 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3227 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3228 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3229 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3230
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3231 // 'X' matches anything.
3232 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3233 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3234 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3235 // the result, which is not what we want to look at; leave them alone.
3236 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3237 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3238 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3239 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3240 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3241
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3242 // Otherwise, try to resolve it to something we know about by looking at
3243 // the actual operand type.
3244 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3245 OpInfo.ConstraintCode = Repl;
3246 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3247 }
3248 }
3249}
3250
3251//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3252// Loop Strength Reduction hooks
3253//===----------------------------------------------------------------------===//
3254
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3255/// isLegalAddressingMode - Return true if the addressing mode represented
3256/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3257bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3258 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3259 // The default implementation of this implements a conservative RISCy, r+r and
3260 // r+i addr mode.
3261
3262 // Allows a sign-extended 16-bit immediate field.
3263 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3264 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3265
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3266 // No global is ever allowed as a base.
3267 if (AM.BaseGV)
3268 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3269
3270 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3271 switch (AM.Scale) {
3272 case 0: // "r+i" or just "i", depending on HasBaseReg.
3273 break;
3274 case 1:
3275 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3276 return false;
3277 // Otherwise we have r+r or r+i.
3278 break;
3279 case 2:
3280 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3281 return false;
3282 // Allow 2*r as r+r.
3283 break;
3284 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3285
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3286 return true;
3287}
3288
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3289/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3290/// with the multiplicative inverse of the constant.
3291SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3292 SelectionDAG &DAG) const {
3293 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3294 APInt d = C->getAPIntValue();
3295 assert(d != 0 && "Division by zero!");
3296
3297 // Shift the value upfront if it is even, so the LSB is one.
3298 unsigned ShAmt = d.countTrailingZeros();
3299 if (ShAmt) {
3300 // TODO: For UDIV use SRL instead of SRA.
3301 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3302 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3303 d = d.ashr(ShAmt);
3304 }
3305
3306 // Calculate the multiplicative inverse, using Newton's method.
3307 APInt t, xn = d;
3308 while ((t = d*xn) != 1)
3309 xn *= APInt(d.getBitWidth(), 2) - t;
3310
3311 Op2 = DAG.getConstant(xn, Op1.getValueType());
3312 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3313}
3314
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3315/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3316/// return a DAG expression to select that will generate the same value by
3317/// multiplying by a magic number. See:
3318/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3319SDValue TargetLowering::
3320BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3321 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3322 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3323 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3324
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3325 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3326 // FIXME: We should be more aggressive here.
3327 if (!isTypeLegal(VT))
3328 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3329
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3330 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3331 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3332
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3333 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3334 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3335 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3336 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3337 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3338 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3339 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3340 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3341 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3342 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3343 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3344 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3345 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3346 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3347 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3348 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3349 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3350 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3351 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3352 }
3353 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3354 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3355 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3356 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3357 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3358 }
3359 // Shift right algebraic if shift value is nonzero
3360 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3361 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3362 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3363 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3364 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3365 }
3366 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3367 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3368 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3369 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3370 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3371 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3372 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3373}
3374
3375/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3376/// return a DAG expression to select that will generate the same value by
3377/// multiplying by a magic number. See:
3378/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3379SDValue TargetLowering::
3380BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3381 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3382 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3383 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3384
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3385 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3386 // FIXME: We should be more aggressive here.
3387 if (!isTypeLegal(VT))
3388 return SDValue();
3389
3390 // FIXME: We should use a narrower constant when the upper
3391 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3392 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3393 APInt::mu magics = N1C.magicu();
3394
3395 SDValue Q = N->getOperand(0);
3396
3397 // If the divisor is even, we can avoid using the expensive fixup by shifting
3398 // the divided value upfront.
3399 if (magics.a != 0 && !N1C[0]) {
3400 unsigned Shift = N1C.countTrailingZeros();
3401 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3402 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3403 if (Created)
3404 Created->push_back(Q.getNode());
3405
3406 // Get magic number for the shifted divisor.
3407 magics = N1C.lshr(Shift).magicu(Shift);
3408 assert(magics.a == 0 && "Should use cheap fixup now");
3409 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3410
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3411 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3412 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3413 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3414 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3415 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3416 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3417 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3418 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3419 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3420 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3421 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3422 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3423 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3424
3425 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3426 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3427 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3428 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3429 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3430 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3431 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3432 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3433 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3434 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3435 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3436 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3437 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3438 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3439 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3440 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3441 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3442 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3443 }
3444}