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gerrit-public.fairphone.software / platform / external / llvm / ecd1c557904815e568258fc5420de479589b0a93 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 6cbe863d0ee5e6f565f0b0fcb4ccda71abd02c1c [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
54 EDInstInfo *getEDInfo() const;
55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
73 const MemoryObject &region,
74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
79 EDInstInfo *getEDInfo() const;
80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
99 return false;
100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]146static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]147 unsigned Insn,
148 uint64_t Address,
149 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]159static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 unsigned Insn,
161 uint64_t Adddress,
162 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]274static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]298static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]300static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
302static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
303 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]304static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]306static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]309
310#include "ARMGenDisassemblerTables.inc"
311#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]312#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]313
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]314static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
315 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]316}
317
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]318static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
319 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]320}
321
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]322EDInstInfo *ARMDisassembler::getEDInfo() const {
323 return instInfoARM;
324}
325
326EDInstInfo *ThumbDisassembler::getEDInfo() const {
327 return instInfoARM;
328}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]330DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]331 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]332 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]333 raw_ostream &os,
334 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint8_t bytes[4];
336
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]337 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
338 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
339
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]340 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]341 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
342 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]343 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]344 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345
346 // Encoded as a small-endian 32-bit word in the stream.
347 uint32_t insn = (bytes[3] << 24) |
348 (bytes[2] << 16) |
349 (bytes[1] << 8) |
350 (bytes[0] << 0);
351
352 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]353 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]354 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]356 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 }
358
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 // VFP and NEON instructions, similarly, are shared between ARM
360 // and Thumb modes.
361 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]362 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]363 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]365 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366 }
367
368 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]369 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]370 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]371 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]372 // Add a fake predicate operand, because we share these instruction
373 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]374 if (!DecodePredicateOperand(MI, 0xE, Address, this))
375 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]376 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]377 }
378
379 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]380 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]381 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]383 // Add a fake predicate operand, because we share these instruction
384 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]385 if (!DecodePredicateOperand(MI, 0xE, Address, this))
386 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]387 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]388 }
389
390 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]391 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]392 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 Size = 4;
394 // Add a fake predicate operand, because we share these instruction
395 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]396 if (!DecodePredicateOperand(MI, 0xE, Address, this))
397 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]398 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]399 }
400
401 MI.clear();
402
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]403 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]404 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]405}
406
407namespace llvm {
408extern MCInstrDesc ARMInsts[];
409}
410
411// Thumb1 instructions don't have explicit S bits. Rather, they
412// implicitly set CPSR. Since it's not represented in the encoding, the
413// auto-generated decoder won't inject the CPSR operand. We need to fix
414// that as a post-pass.
415static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
416 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]417 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 for (unsigned i = 0; i < NumOps; ++i, ++I) {
420 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]422 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
424 return;
425 }
426 }
427
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]428 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]429}
430
431// Most Thumb instructions don't have explicit predicates in the
432// encoding, but rather get their predicates from IT context. We need
433// to fix up the predicate operands using this context information as a
434// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]435MCDisassembler::DecodeStatus
436ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]437 MCDisassembler::DecodeStatus S = Success;
438
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]439 // A few instructions actually have predicates encoded in them. Don't
440 // try to overwrite it if we're seeing one of those.
441 switch (MI.getOpcode()) {
442 case ARM::tBcc:
443 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]444 case ARM::tCBZ:
445 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]446 // Some instructions (mostly conditional branches) are not
447 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]448 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]449 S = SoftFail;
450 else
451 return Success;
452 break;
453 case ARM::tB:
454 case ARM::t2B:
455 // Some instructions (mostly unconditional branches) can
456 // only appears at the end of, or outside of, an IT.
457 if (ITBlock.size() > 1)
458 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]459 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]460 default:
461 break;
462 }
463
464 // If we're in an IT block, base the predicate on that. Otherwise,
465 // assume a predicate of AL.
466 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]467 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]469 if (CC == 0xF)
470 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]471 ITBlock.pop_back();
472 } else
473 CC = ARMCC::AL;
474
475 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]476 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]477 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]478 for (unsigned i = 0; i < NumOps; ++i, ++I) {
479 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]480 if (OpInfo[i].isPredicate()) {
481 I = MI.insert(I, MCOperand::CreateImm(CC));
482 ++I;
483 if (CC == ARMCC::AL)
484 MI.insert(I, MCOperand::CreateReg(0));
485 else
486 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]487 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]488 }
489 }
490
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]491 I = MI.insert(I, MCOperand::CreateImm(CC));
492 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]493 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]494 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]495 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]496 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]497
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]498 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]499}
500
501// Thumb VFP instructions are a special case. Because we share their
502// encodings between ARM and Thumb modes, and they are predicable in ARM
503// mode, the auto-generated decoder will give them an (incorrect)
504// predicate operand. We need to rewrite these operands based on the IT
505// context as a post-pass.
506void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
507 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]508 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]509 CC = ITBlock.back();
510 ITBlock.pop_back();
511 } else
512 CC = ARMCC::AL;
513
514 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
515 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]516 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
517 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]518 if (OpInfo[i].isPredicate() ) {
519 I->setImm(CC);
520 ++I;
521 if (CC == ARMCC::AL)
522 I->setReg(0);
523 else
524 I->setReg(ARM::CPSR);
525 return;
526 }
527 }
528}
529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]530DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]531 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]532 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]533 raw_ostream &os,
534 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]535 uint8_t bytes[4];
536
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]537 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
538 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
539
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]540 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]541 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
542 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]543 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]544 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545
546 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]547 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]548 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]549 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]550 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]551 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]552 }
553
554 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]555 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]556 if (result) {
557 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]558 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]559 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]560 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]561 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]562 }
563
564 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]565 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]566 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]567 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]568 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]569
570 // If we find an IT instruction, we need to parse its condition
571 // code and mask operands so that we can apply them correctly
572 // to the subsequent instructions.
573 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]574 // Nested IT blocks are UNPREDICTABLE.
575 if (!ITBlock.empty())
576 return MCDisassembler::SoftFail;
577
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]578 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]580 unsigned Mask = MI.getOperand(1).getImm();
581 unsigned CondBit0 = Mask >> 4 & 1;
582 unsigned NumTZ = CountTrailingZeros_32(Mask);
583 assert(NumTZ <= 3 && "Invalid IT mask!");
584 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
585 bool T = ((Mask >> Pos) & 1) == CondBit0;
586 if (T)
587 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]589 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]591
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592 ITBlock.push_back(firstcond);
593 }
594
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]595 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]596 }
597
598 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]599 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
600 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]601 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]602 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]603
604 uint32_t insn32 = (bytes[3] << 8) |
605 (bytes[2] << 0) |
606 (bytes[1] << 24) |
607 (bytes[0] << 16);
608 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]609 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]610 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]611 Size = 4;
612 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]613 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]614 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]615 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 }
617
618 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]619 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]620 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]621 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]622 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]623 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]624 }
625
626 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]627 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]628 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 Size = 4;
630 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]631 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632 }
633
634 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]635 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]636 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]637 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]638 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]639 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]640 }
641
642 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
643 MI.clear();
644 uint32_t NEONLdStInsn = insn32;
645 NEONLdStInsn &= 0xF0FFFFFF;
646 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]647 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]648 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]649 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]650 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]651 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]652 }
653 }
654
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]655 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]656 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]657 uint32_t NEONDataInsn = insn32;
658 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
659 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
660 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]661 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]662 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]663 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]664 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]665 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]666 }
667 }
668
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]669 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]670 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]671}
672
673
674extern "C" void LLVMInitializeARMDisassembler() {
675 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
676 createARMDisassembler);
677 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
678 createThumbDisassembler);
679}
680
681static const unsigned GPRDecoderTable[] = {
682 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
683 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
684 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
685 ARM::R12, ARM::SP, ARM::LR, ARM::PC
686};
687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]688static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]689 uint64_t Address, const void *Decoder) {
690 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]691 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]692
693 unsigned Register = GPRDecoderTable[RegNo];
694 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]695 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]696}
697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]698static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]699DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
700 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]701 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]702 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
703}
704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]705static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706 uint64_t Address, const void *Decoder) {
707 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]708 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
710}
711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]712static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]713 uint64_t Address, const void *Decoder) {
714 unsigned Register = 0;
715 switch (RegNo) {
716 case 0:
717 Register = ARM::R0;
718 break;
719 case 1:
720 Register = ARM::R1;
721 break;
722 case 2:
723 Register = ARM::R2;
724 break;
725 case 3:
726 Register = ARM::R3;
727 break;
728 case 9:
729 Register = ARM::R9;
730 break;
731 case 12:
732 Register = ARM::R12;
733 break;
734 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]735 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]736 }
737
738 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]739 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]740}
741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]742static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]744 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]745 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
746}
747
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]748static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
750 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
751 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
752 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
753 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
754 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
755 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
756 ARM::S28, ARM::S29, ARM::S30, ARM::S31
757};
758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]759static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]760 uint64_t Address, const void *Decoder) {
761 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763
764 unsigned Register = SPRDecoderTable[RegNo];
765 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]766 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767}
768
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]769static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
771 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
772 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
773 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
774 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
775 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
776 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
777 ARM::D28, ARM::D29, ARM::D30, ARM::D31
778};
779
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]780static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 uint64_t Address, const void *Decoder) {
782 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784
785 unsigned Register = DPRDecoderTable[RegNo];
786 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]787 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788}
789
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]790static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 uint64_t Address, const void *Decoder) {
792 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
795}
796
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]797static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]798DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
799 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]800 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
803}
804
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]805static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
807 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
808 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
809 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
810};
811
812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]813static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 uint64_t Address, const void *Decoder) {
815 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]816 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 RegNo >>= 1;
818
819 unsigned Register = QPRDecoderTable[RegNo];
820 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]821 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]822}
823
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]824static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]825 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]826 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]827 // AL predicate is not allowed on Thumb1 branches.
828 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]829 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]830 Inst.addOperand(MCOperand::CreateImm(Val));
831 if (Val == ARMCC::AL) {
832 Inst.addOperand(MCOperand::CreateReg(0));
833 } else
834 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]835 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836}
837
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]838static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]839 uint64_t Address, const void *Decoder) {
840 if (Val)
841 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
842 else
843 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]844 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]845}
846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]847static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]848 uint64_t Address, const void *Decoder) {
849 uint32_t imm = Val & 0xFF;
850 uint32_t rot = (Val & 0xF00) >> 7;
851 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
852 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854}
855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]856static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]858 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859
860 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
861 unsigned type = fieldFromInstruction32(Val, 5, 2);
862 unsigned imm = fieldFromInstruction32(Val, 7, 5);
863
864 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
866 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867
868 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
869 switch (type) {
870 case 0:
871 Shift = ARM_AM::lsl;
872 break;
873 case 1:
874 Shift = ARM_AM::lsr;
875 break;
876 case 2:
877 Shift = ARM_AM::asr;
878 break;
879 case 3:
880 Shift = ARM_AM::ror;
881 break;
882 }
883
884 if (Shift == ARM_AM::ror && imm == 0)
885 Shift = ARM_AM::rrx;
886
887 unsigned Op = Shift | (imm << 3);
888 Inst.addOperand(MCOperand::CreateImm(Op));
889
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]890 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]891}
892
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]893static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]894 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]895 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]896
897 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
898 unsigned type = fieldFromInstruction32(Val, 5, 2);
899 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
900
901 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]902 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
903 return MCDisassembler::Fail;
904 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
905 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906
907 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
908 switch (type) {
909 case 0:
910 Shift = ARM_AM::lsl;
911 break;
912 case 1:
913 Shift = ARM_AM::lsr;
914 break;
915 case 2:
916 Shift = ARM_AM::asr;
917 break;
918 case 3:
919 Shift = ARM_AM::ror;
920 break;
921 }
922
923 Inst.addOperand(MCOperand::CreateImm(Shift));
924
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]925 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926}
927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]928static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]930 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]931
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]932 bool writebackLoad = false;
933 unsigned writebackReg = 0;
934 switch (Inst.getOpcode()) {
935 default:
936 break;
937 case ARM::LDMIA_UPD:
938 case ARM::LDMDB_UPD:
939 case ARM::LDMIB_UPD:
940 case ARM::LDMDA_UPD:
941 case ARM::t2LDMIA_UPD:
942 case ARM::t2LDMDB_UPD:
943 writebackLoad = true;
944 writebackReg = Inst.getOperand(0).getReg();
945 break;
946 }
947
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]948 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]949 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]951 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
953 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]954 // Writeback not allowed if Rn is in the target list.
955 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
956 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]957 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 }
959
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]960 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961}
962
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]963static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]966
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
968 unsigned regs = Val & 0xFF;
969
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]970 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
971 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]972 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]973 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
974 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]975 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]977 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978}
979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]980static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]982 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]983
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
985 unsigned regs = (Val & 0xFF) / 2;
986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]987 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
988 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]989 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]990 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
991 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]992 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]994 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995}
996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]997static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]999 // This operand encodes a mask of contiguous zeros between a specified MSB
1000 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1001 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1002 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1003 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1004 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1005 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1006
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1007 DecodeStatus S = MCDisassembler::Success;
1008 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1009
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1010 uint32_t msb_mask = 0xFFFFFFFF;
1011 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1012 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1013
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1014 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1015 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016}
1017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1018static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1020 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1021
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1023 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1024 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1025 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1026 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1027 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1028
1029 switch (Inst.getOpcode()) {
1030 case ARM::LDC_OFFSET:
1031 case ARM::LDC_PRE:
1032 case ARM::LDC_POST:
1033 case ARM::LDC_OPTION:
1034 case ARM::LDCL_OFFSET:
1035 case ARM::LDCL_PRE:
1036 case ARM::LDCL_POST:
1037 case ARM::LDCL_OPTION:
1038 case ARM::STC_OFFSET:
1039 case ARM::STC_PRE:
1040 case ARM::STC_POST:
1041 case ARM::STC_OPTION:
1042 case ARM::STCL_OFFSET:
1043 case ARM::STCL_PRE:
1044 case ARM::STCL_POST:
1045 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1046 case ARM::t2LDC_OFFSET:
1047 case ARM::t2LDC_PRE:
1048 case ARM::t2LDC_POST:
1049 case ARM::t2LDC_OPTION:
1050 case ARM::t2LDCL_OFFSET:
1051 case ARM::t2LDCL_PRE:
1052 case ARM::t2LDCL_POST:
1053 case ARM::t2LDCL_OPTION:
1054 case ARM::t2STC_OFFSET:
1055 case ARM::t2STC_PRE:
1056 case ARM::t2STC_POST:
1057 case ARM::t2STC_OPTION:
1058 case ARM::t2STCL_OFFSET:
1059 case ARM::t2STCL_PRE:
1060 case ARM::t2STCL_POST:
1061 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1062 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1063 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1064 break;
1065 default:
1066 break;
1067 }
1068
1069 Inst.addOperand(MCOperand::CreateImm(coproc));
1070 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1072 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1073 switch (Inst.getOpcode()) {
1074 case ARM::LDC_OPTION:
1075 case ARM::LDCL_OPTION:
1076 case ARM::LDC2_OPTION:
1077 case ARM::LDC2L_OPTION:
1078 case ARM::STC_OPTION:
1079 case ARM::STCL_OPTION:
1080 case ARM::STC2_OPTION:
1081 case ARM::STC2L_OPTION:
1082 case ARM::LDCL_POST:
1083 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1084 case ARM::LDC2L_POST:
1085 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1086 case ARM::t2LDC_OPTION:
1087 case ARM::t2LDCL_OPTION:
1088 case ARM::t2STC_OPTION:
1089 case ARM::t2STCL_OPTION:
1090 case ARM::t2LDCL_POST:
1091 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1092 break;
1093 default:
1094 Inst.addOperand(MCOperand::CreateReg(0));
1095 break;
1096 }
1097
1098 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1099 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1100
1101 bool writeback = (P == 0) || (W == 1);
1102 unsigned idx_mode = 0;
1103 if (P && writeback)
1104 idx_mode = ARMII::IndexModePre;
1105 else if (!P && writeback)
1106 idx_mode = ARMII::IndexModePost;
1107
1108 switch (Inst.getOpcode()) {
1109 case ARM::LDCL_POST:
1110 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1111 case ARM::t2LDCL_POST:
1112 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1113 case ARM::LDC2L_POST:
1114 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1115 imm |= U << 8;
1116 case ARM::LDC_OPTION:
1117 case ARM::LDCL_OPTION:
1118 case ARM::LDC2_OPTION:
1119 case ARM::LDC2L_OPTION:
1120 case ARM::STC_OPTION:
1121 case ARM::STCL_OPTION:
1122 case ARM::STC2_OPTION:
1123 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1124 case ARM::t2LDC_OPTION:
1125 case ARM::t2LDCL_OPTION:
1126 case ARM::t2STC_OPTION:
1127 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1128 Inst.addOperand(MCOperand::CreateImm(imm));
1129 break;
1130 default:
1131 if (U)
1132 Inst.addOperand(MCOperand::CreateImm(
1133 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1134 else
1135 Inst.addOperand(MCOperand::CreateImm(
1136 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1137 break;
1138 }
1139
1140 switch (Inst.getOpcode()) {
1141 case ARM::LDC_OFFSET:
1142 case ARM::LDC_PRE:
1143 case ARM::LDC_POST:
1144 case ARM::LDC_OPTION:
1145 case ARM::LDCL_OFFSET:
1146 case ARM::LDCL_PRE:
1147 case ARM::LDCL_POST:
1148 case ARM::LDCL_OPTION:
1149 case ARM::STC_OFFSET:
1150 case ARM::STC_PRE:
1151 case ARM::STC_POST:
1152 case ARM::STC_OPTION:
1153 case ARM::STCL_OFFSET:
1154 case ARM::STCL_PRE:
1155 case ARM::STCL_POST:
1156 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1157 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1158 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1159 break;
1160 default:
1161 break;
1162 }
1163
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1164 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1165}
1166
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1167static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1168DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1169 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1170 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1171
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1172 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1173 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1174 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1175 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1176 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1177 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1178 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1179 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1180
1181 // On stores, the writeback operand precedes Rt.
1182 switch (Inst.getOpcode()) {
1183 case ARM::STR_POST_IMM:
1184 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1185 case ARM::STRB_POST_IMM:
1186 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1187 case ARM::STRT_POST_REG:
1188 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1189 case ARM::STRBT_POST_REG:
1190 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1192 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1193 break;
1194 default:
1195 break;
1196 }
1197
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1199 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200
1201 // On loads, the writeback operand comes after Rt.
1202 switch (Inst.getOpcode()) {
1203 case ARM::LDR_POST_IMM:
1204 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1205 case ARM::LDRB_POST_IMM:
1206 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1207 case ARM::LDRBT_POST_REG:
1208 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1209 case ARM::LDRT_POST_REG:
1210 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1212 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1213 break;
1214 default:
1215 break;
1216 }
1217
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1219 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1220
1221 ARM_AM::AddrOpc Op = ARM_AM::add;
1222 if (!fieldFromInstruction32(Insn, 23, 1))
1223 Op = ARM_AM::sub;
1224
1225 bool writeback = (P == 0) || (W == 1);
1226 unsigned idx_mode = 0;
1227 if (P && writeback)
1228 idx_mode = ARMII::IndexModePre;
1229 else if (!P && writeback)
1230 idx_mode = ARMII::IndexModePost;
1231
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1232 if (writeback && (Rn == 15 || Rn == Rt))
1233 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1234
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1236 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1237 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1239 switch( fieldFromInstruction32(Insn, 5, 2)) {
1240 case 0:
1241 Opc = ARM_AM::lsl;
1242 break;
1243 case 1:
1244 Opc = ARM_AM::lsr;
1245 break;
1246 case 2:
1247 Opc = ARM_AM::asr;
1248 break;
1249 case 3:
1250 Opc = ARM_AM::ror;
1251 break;
1252 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1253 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1254 }
1255 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1256 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1257
1258 Inst.addOperand(MCOperand::CreateImm(imm));
1259 } else {
1260 Inst.addOperand(MCOperand::CreateReg(0));
1261 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1262 Inst.addOperand(MCOperand::CreateImm(tmp));
1263 }
1264
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1265 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1266 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1267
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1268 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1269}
1270
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1271static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1272 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1273 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1274
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1275 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1276 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1277 unsigned type = fieldFromInstruction32(Val, 5, 2);
1278 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1279 unsigned U = fieldFromInstruction32(Val, 12, 1);
1280
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1281 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 switch (type) {
1283 case 0:
1284 ShOp = ARM_AM::lsl;
1285 break;
1286 case 1:
1287 ShOp = ARM_AM::lsr;
1288 break;
1289 case 2:
1290 ShOp = ARM_AM::asr;
1291 break;
1292 case 3:
1293 ShOp = ARM_AM::ror;
1294 break;
1295 }
1296
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1298 return MCDisassembler::Fail;
1299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1300 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1301 unsigned shift;
1302 if (U)
1303 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1304 else
1305 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1306 Inst.addOperand(MCOperand::CreateImm(shift));
1307
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1308 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1309}
1310
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1311static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1312DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1313 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1314 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1315
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1316 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1317 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1318 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1319 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1320 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1321 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1322 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1323 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1324 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1325
1326 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1327
1328 // For {LD,ST}RD, Rt must be even, else undefined.
1329 switch (Inst.getOpcode()) {
1330 case ARM::STRD:
1331 case ARM::STRD_PRE:
1332 case ARM::STRD_POST:
1333 case ARM::LDRD:
1334 case ARM::LDRD_PRE:
1335 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1336 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1337 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1338 default:
1339 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1340 }
1341
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1342 if (writeback) { // Writeback
1343 if (P)
1344 U |= ARMII::IndexModePre << 9;
1345 else
1346 U |= ARMII::IndexModePost << 9;
1347
1348 // On stores, the writeback operand precedes Rt.
1349 switch (Inst.getOpcode()) {
1350 case ARM::STRD:
1351 case ARM::STRD_PRE:
1352 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1353 case ARM::STRH:
1354 case ARM::STRH_PRE:
1355 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1357 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1358 break;
1359 default:
1360 break;
1361 }
1362 }
1363
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1365 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1366 switch (Inst.getOpcode()) {
1367 case ARM::STRD:
1368 case ARM::STRD_PRE:
1369 case ARM::STRD_POST:
1370 case ARM::LDRD:
1371 case ARM::LDRD_PRE:
1372 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1374 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1375 break;
1376 default:
1377 break;
1378 }
1379
1380 if (writeback) {
1381 // On loads, the writeback operand comes after Rt.
1382 switch (Inst.getOpcode()) {
1383 case ARM::LDRD:
1384 case ARM::LDRD_PRE:
1385 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1386 case ARM::LDRH:
1387 case ARM::LDRH_PRE:
1388 case ARM::LDRH_POST:
1389 case ARM::LDRSH:
1390 case ARM::LDRSH_PRE:
1391 case ARM::LDRSH_POST:
1392 case ARM::LDRSB:
1393 case ARM::LDRSB_PRE:
1394 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1395 case ARM::LDRHTr:
1396 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1398 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1399 break;
1400 default:
1401 break;
1402 }
1403 }
1404
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1407
1408 if (type) {
1409 Inst.addOperand(MCOperand::CreateReg(0));
1410 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1411 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1413 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1414 Inst.addOperand(MCOperand::CreateImm(U));
1415 }
1416
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1417 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1418 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1419
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1420 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421}
1422
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1423static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1424 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1426
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1428 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1429
1430 switch (mode) {
1431 case 0:
1432 mode = ARM_AM::da;
1433 break;
1434 case 1:
1435 mode = ARM_AM::ia;
1436 break;
1437 case 2:
1438 mode = ARM_AM::db;
1439 break;
1440 case 3:
1441 mode = ARM_AM::ib;
1442 break;
1443 }
1444
1445 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1447 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1448
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1449 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450}
1451
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1452static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1453 unsigned Insn,
1454 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1455 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1456
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1457 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1458 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1459 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1460
1461 if (pred == 0xF) {
1462 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1463 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464 Inst.setOpcode(ARM::RFEDA);
1465 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1466 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1467 Inst.setOpcode(ARM::RFEDA_UPD);
1468 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1469 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1470 Inst.setOpcode(ARM::RFEDB);
1471 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1472 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1473 Inst.setOpcode(ARM::RFEDB_UPD);
1474 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1475 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1476 Inst.setOpcode(ARM::RFEIA);
1477 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1478 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1479 Inst.setOpcode(ARM::RFEIA_UPD);
1480 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1481 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1482 Inst.setOpcode(ARM::RFEIB);
1483 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1484 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1485 Inst.setOpcode(ARM::RFEIB_UPD);
1486 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1487 case ARM::STMDA:
1488 Inst.setOpcode(ARM::SRSDA);
1489 break;
1490 case ARM::STMDA_UPD:
1491 Inst.setOpcode(ARM::SRSDA_UPD);
1492 break;
1493 case ARM::STMDB:
1494 Inst.setOpcode(ARM::SRSDB);
1495 break;
1496 case ARM::STMDB_UPD:
1497 Inst.setOpcode(ARM::SRSDB_UPD);
1498 break;
1499 case ARM::STMIA:
1500 Inst.setOpcode(ARM::SRSIA);
1501 break;
1502 case ARM::STMIA_UPD:
1503 Inst.setOpcode(ARM::SRSIA_UPD);
1504 break;
1505 case ARM::STMIB:
1506 Inst.setOpcode(ARM::SRSIB);
1507 break;
1508 case ARM::STMIB_UPD:
1509 Inst.setOpcode(ARM::SRSIB_UPD);
1510 break;
1511 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1512 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1513 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1514
1515 // For stores (which become SRS's, the only operand is the mode.
1516 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1517 Inst.addOperand(
1518 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1519 return S;
1520 }
1521
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1522 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1523 }
1524
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1526 return MCDisassembler::Fail;
1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1528 return MCDisassembler::Fail; // Tied
1529 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1530 return MCDisassembler::Fail;
1531 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1532 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1533
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1534 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1535}
1536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1537static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1538 uint64_t Address, const void *Decoder) {
1539 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1540 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1541 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1542 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1543
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1544 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1545
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1546 // imod == '01' --> UNPREDICTABLE
1547 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1548 // return failure here. The '01' imod value is unprintable, so there's
1549 // nothing useful we could do even if we returned UNPREDICTABLE.
1550
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1551 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1552
1553 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1554 Inst.setOpcode(ARM::CPS3p);
1555 Inst.addOperand(MCOperand::CreateImm(imod));
1556 Inst.addOperand(MCOperand::CreateImm(iflags));
1557 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1558 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1559 Inst.setOpcode(ARM::CPS2p);
1560 Inst.addOperand(MCOperand::CreateImm(imod));
1561 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1562 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1563 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1564 Inst.setOpcode(ARM::CPS1p);
1565 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1566 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1567 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1568 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1569 Inst.setOpcode(ARM::CPS1p);
1570 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1571 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1572 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1573
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1574 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1575}
1576
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1577static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1578 uint64_t Address, const void *Decoder) {
1579 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1580 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1581 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1582 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1583
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1584 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1585
1586 // imod == '01' --> UNPREDICTABLE
1587 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1588 // return failure here. The '01' imod value is unprintable, so there's
1589 // nothing useful we could do even if we returned UNPREDICTABLE.
1590
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1591 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1592
1593 if (imod && M) {
1594 Inst.setOpcode(ARM::t2CPS3p);
1595 Inst.addOperand(MCOperand::CreateImm(imod));
1596 Inst.addOperand(MCOperand::CreateImm(iflags));
1597 Inst.addOperand(MCOperand::CreateImm(mode));
1598 } else if (imod && !M) {
1599 Inst.setOpcode(ARM::t2CPS2p);
1600 Inst.addOperand(MCOperand::CreateImm(imod));
1601 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1602 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1603 } else if (!imod && M) {
1604 Inst.setOpcode(ARM::t2CPS1p);
1605 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1606 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1607 } else {
1608 // imod == '00' && M == '0' --> UNPREDICTABLE
1609 Inst.setOpcode(ARM::t2CPS1p);
1610 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1611 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1612 }
1613
1614 return S;
1615}
1616
1617
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1618static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1619 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1620 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1621
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1622 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1623 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1624 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1625 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1626 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1627
1628 if (pred == 0xF)
1629 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1630
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1631 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1632 return MCDisassembler::Fail;
1633 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1634 return MCDisassembler::Fail;
1635 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1636 return MCDisassembler::Fail;
1637 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1638 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1639
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1640 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1641 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1642
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1643 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1644}
1645
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1646static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1647 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1648 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1649
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1650 unsigned add = fieldFromInstruction32(Val, 12, 1);
1651 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1652 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1653
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1655 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1656
1657 if (!add) imm *= -1;
1658 if (imm == 0 && !add) imm = INT32_MIN;
1659 Inst.addOperand(MCOperand::CreateImm(imm));
1660
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1661 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1662}
1663
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1664static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1665 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1667
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1668 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1669 unsigned U = fieldFromInstruction32(Val, 8, 1);
1670 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1671
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1673 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1674
1675 if (U)
1676 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1677 else
1678 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1679
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1680 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1681}
1682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1683static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684 uint64_t Address, const void *Decoder) {
1685 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1686}
1687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1688static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1689DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1690 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1691 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1692
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1693 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1694 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1695
1696 if (pred == 0xF) {
1697 Inst.setOpcode(ARM::BLXi);
1698 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1699 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1700 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701 }
1702
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1703 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1704 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1705 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1706
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1707 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1708}
1709
1710
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1711static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712 uint64_t Address, const void *Decoder) {
1713 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1714 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1715}
1716
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1717static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1719 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1720
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1722 unsigned align = fieldFromInstruction32(Val, 4, 2);
1723
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1725 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1726 if (!align)
1727 Inst.addOperand(MCOperand::CreateImm(0));
1728 else
1729 Inst.addOperand(MCOperand::CreateImm(4 << align));
1730
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1731 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1732}
1733
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1734static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1735 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1736 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1737
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1738 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1739 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1740 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1741 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1742 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1743 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1744
1745 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1747 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1748
1749 // Second output register
1750 switch (Inst.getOpcode()) {
1751 case ARM::VLD1q8:
1752 case ARM::VLD1q16:
1753 case ARM::VLD1q32:
1754 case ARM::VLD1q64:
1755 case ARM::VLD1q8_UPD:
1756 case ARM::VLD1q16_UPD:
1757 case ARM::VLD1q32_UPD:
1758 case ARM::VLD1q64_UPD:
1759 case ARM::VLD1d8T:
1760 case ARM::VLD1d16T:
1761 case ARM::VLD1d32T:
1762 case ARM::VLD1d64T:
1763 case ARM::VLD1d8T_UPD:
1764 case ARM::VLD1d16T_UPD:
1765 case ARM::VLD1d32T_UPD:
1766 case ARM::VLD1d64T_UPD:
1767 case ARM::VLD1d8Q:
1768 case ARM::VLD1d16Q:
1769 case ARM::VLD1d32Q:
1770 case ARM::VLD1d64Q:
1771 case ARM::VLD1d8Q_UPD:
1772 case ARM::VLD1d16Q_UPD:
1773 case ARM::VLD1d32Q_UPD:
1774 case ARM::VLD1d64Q_UPD:
1775 case ARM::VLD2d8:
1776 case ARM::VLD2d16:
1777 case ARM::VLD2d32:
1778 case ARM::VLD2d8_UPD:
1779 case ARM::VLD2d16_UPD:
1780 case ARM::VLD2d32_UPD:
1781 case ARM::VLD2q8:
1782 case ARM::VLD2q16:
1783 case ARM::VLD2q32:
1784 case ARM::VLD2q8_UPD:
1785 case ARM::VLD2q16_UPD:
1786 case ARM::VLD2q32_UPD:
1787 case ARM::VLD3d8:
1788 case ARM::VLD3d16:
1789 case ARM::VLD3d32:
1790 case ARM::VLD3d8_UPD:
1791 case ARM::VLD3d16_UPD:
1792 case ARM::VLD3d32_UPD:
1793 case ARM::VLD4d8:
1794 case ARM::VLD4d16:
1795 case ARM::VLD4d32:
1796 case ARM::VLD4d8_UPD:
1797 case ARM::VLD4d16_UPD:
1798 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1800 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1801 break;
1802 case ARM::VLD2b8:
1803 case ARM::VLD2b16:
1804 case ARM::VLD2b32:
1805 case ARM::VLD2b8_UPD:
1806 case ARM::VLD2b16_UPD:
1807 case ARM::VLD2b32_UPD:
1808 case ARM::VLD3q8:
1809 case ARM::VLD3q16:
1810 case ARM::VLD3q32:
1811 case ARM::VLD3q8_UPD:
1812 case ARM::VLD3q16_UPD:
1813 case ARM::VLD3q32_UPD:
1814 case ARM::VLD4q8:
1815 case ARM::VLD4q16:
1816 case ARM::VLD4q32:
1817 case ARM::VLD4q8_UPD:
1818 case ARM::VLD4q16_UPD:
1819 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1820 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1821 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1822 default:
1823 break;
1824 }
1825
1826 // Third output register
1827 switch(Inst.getOpcode()) {
1828 case ARM::VLD1d8T:
1829 case ARM::VLD1d16T:
1830 case ARM::VLD1d32T:
1831 case ARM::VLD1d64T:
1832 case ARM::VLD1d8T_UPD:
1833 case ARM::VLD1d16T_UPD:
1834 case ARM::VLD1d32T_UPD:
1835 case ARM::VLD1d64T_UPD:
1836 case ARM::VLD1d8Q:
1837 case ARM::VLD1d16Q:
1838 case ARM::VLD1d32Q:
1839 case ARM::VLD1d64Q:
1840 case ARM::VLD1d8Q_UPD:
1841 case ARM::VLD1d16Q_UPD:
1842 case ARM::VLD1d32Q_UPD:
1843 case ARM::VLD1d64Q_UPD:
1844 case ARM::VLD2q8:
1845 case ARM::VLD2q16:
1846 case ARM::VLD2q32:
1847 case ARM::VLD2q8_UPD:
1848 case ARM::VLD2q16_UPD:
1849 case ARM::VLD2q32_UPD:
1850 case ARM::VLD3d8:
1851 case ARM::VLD3d16:
1852 case ARM::VLD3d32:
1853 case ARM::VLD3d8_UPD:
1854 case ARM::VLD3d16_UPD:
1855 case ARM::VLD3d32_UPD:
1856 case ARM::VLD4d8:
1857 case ARM::VLD4d16:
1858 case ARM::VLD4d32:
1859 case ARM::VLD4d8_UPD:
1860 case ARM::VLD4d16_UPD:
1861 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1863 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1864 break;
1865 case ARM::VLD3q8:
1866 case ARM::VLD3q16:
1867 case ARM::VLD3q32:
1868 case ARM::VLD3q8_UPD:
1869 case ARM::VLD3q16_UPD:
1870 case ARM::VLD3q32_UPD:
1871 case ARM::VLD4q8:
1872 case ARM::VLD4q16:
1873 case ARM::VLD4q32:
1874 case ARM::VLD4q8_UPD:
1875 case ARM::VLD4q16_UPD:
1876 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1878 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1879 break;
1880 default:
1881 break;
1882 }
1883
1884 // Fourth output register
1885 switch (Inst.getOpcode()) {
1886 case ARM::VLD1d8Q:
1887 case ARM::VLD1d16Q:
1888 case ARM::VLD1d32Q:
1889 case ARM::VLD1d64Q:
1890 case ARM::VLD1d8Q_UPD:
1891 case ARM::VLD1d16Q_UPD:
1892 case ARM::VLD1d32Q_UPD:
1893 case ARM::VLD1d64Q_UPD:
1894 case ARM::VLD2q8:
1895 case ARM::VLD2q16:
1896 case ARM::VLD2q32:
1897 case ARM::VLD2q8_UPD:
1898 case ARM::VLD2q16_UPD:
1899 case ARM::VLD2q32_UPD:
1900 case ARM::VLD4d8:
1901 case ARM::VLD4d16:
1902 case ARM::VLD4d32:
1903 case ARM::VLD4d8_UPD:
1904 case ARM::VLD4d16_UPD:
1905 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1906 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1907 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1908 break;
1909 case ARM::VLD4q8:
1910 case ARM::VLD4q16:
1911 case ARM::VLD4q32:
1912 case ARM::VLD4q8_UPD:
1913 case ARM::VLD4q16_UPD:
1914 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1915 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1916 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1917 break;
1918 default:
1919 break;
1920 }
1921
1922 // Writeback operand
1923 switch (Inst.getOpcode()) {
1924 case ARM::VLD1d8_UPD:
1925 case ARM::VLD1d16_UPD:
1926 case ARM::VLD1d32_UPD:
1927 case ARM::VLD1d64_UPD:
1928 case ARM::VLD1q8_UPD:
1929 case ARM::VLD1q16_UPD:
1930 case ARM::VLD1q32_UPD:
1931 case ARM::VLD1q64_UPD:
1932 case ARM::VLD1d8T_UPD:
1933 case ARM::VLD1d16T_UPD:
1934 case ARM::VLD1d32T_UPD:
1935 case ARM::VLD1d64T_UPD:
1936 case ARM::VLD1d8Q_UPD:
1937 case ARM::VLD1d16Q_UPD:
1938 case ARM::VLD1d32Q_UPD:
1939 case ARM::VLD1d64Q_UPD:
1940 case ARM::VLD2d8_UPD:
1941 case ARM::VLD2d16_UPD:
1942 case ARM::VLD2d32_UPD:
1943 case ARM::VLD2q8_UPD:
1944 case ARM::VLD2q16_UPD:
1945 case ARM::VLD2q32_UPD:
1946 case ARM::VLD2b8_UPD:
1947 case ARM::VLD2b16_UPD:
1948 case ARM::VLD2b32_UPD:
1949 case ARM::VLD3d8_UPD:
1950 case ARM::VLD3d16_UPD:
1951 case ARM::VLD3d32_UPD:
1952 case ARM::VLD3q8_UPD:
1953 case ARM::VLD3q16_UPD:
1954 case ARM::VLD3q32_UPD:
1955 case ARM::VLD4d8_UPD:
1956 case ARM::VLD4d16_UPD:
1957 case ARM::VLD4d32_UPD:
1958 case ARM::VLD4q8_UPD:
1959 case ARM::VLD4q16_UPD:
1960 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1961 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1962 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1963 break;
1964 default:
1965 break;
1966 }
1967
1968 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1969 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1970 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1971
1972 // AddrMode6 Offset (register)
1973 if (Rm == 0xD)
1974 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1975 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1977 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1978 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1979
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1980 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981}
1982
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1983static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1984 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1985 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1986
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1987 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1988 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1989 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1990 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1991 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1992 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1993
1994 // Writeback Operand
1995 switch (Inst.getOpcode()) {
1996 case ARM::VST1d8_UPD:
1997 case ARM::VST1d16_UPD:
1998 case ARM::VST1d32_UPD:
1999 case ARM::VST1d64_UPD:
2000 case ARM::VST1q8_UPD:
2001 case ARM::VST1q16_UPD:
2002 case ARM::VST1q32_UPD:
2003 case ARM::VST1q64_UPD:
2004 case ARM::VST1d8T_UPD:
2005 case ARM::VST1d16T_UPD:
2006 case ARM::VST1d32T_UPD:
2007 case ARM::VST1d64T_UPD:
2008 case ARM::VST1d8Q_UPD:
2009 case ARM::VST1d16Q_UPD:
2010 case ARM::VST1d32Q_UPD:
2011 case ARM::VST1d64Q_UPD:
2012 case ARM::VST2d8_UPD:
2013 case ARM::VST2d16_UPD:
2014 case ARM::VST2d32_UPD:
2015 case ARM::VST2q8_UPD:
2016 case ARM::VST2q16_UPD:
2017 case ARM::VST2q32_UPD:
2018 case ARM::VST2b8_UPD:
2019 case ARM::VST2b16_UPD:
2020 case ARM::VST2b32_UPD:
2021 case ARM::VST3d8_UPD:
2022 case ARM::VST3d16_UPD:
2023 case ARM::VST3d32_UPD:
2024 case ARM::VST3q8_UPD:
2025 case ARM::VST3q16_UPD:
2026 case ARM::VST3q32_UPD:
2027 case ARM::VST4d8_UPD:
2028 case ARM::VST4d16_UPD:
2029 case ARM::VST4d32_UPD:
2030 case ARM::VST4q8_UPD:
2031 case ARM::VST4q16_UPD:
2032 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2033 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2034 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2035 break;
2036 default:
2037 break;
2038 }
2039
2040 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2041 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2042 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2043
2044 // AddrMode6 Offset (register)
2045 if (Rm == 0xD)
2046 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2047 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2049 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2050 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2051
2052 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2053 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2054 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2055
2056 // Second input register
2057 switch (Inst.getOpcode()) {
2058 case ARM::VST1q8:
2059 case ARM::VST1q16:
2060 case ARM::VST1q32:
2061 case ARM::VST1q64:
2062 case ARM::VST1q8_UPD:
2063 case ARM::VST1q16_UPD:
2064 case ARM::VST1q32_UPD:
2065 case ARM::VST1q64_UPD:
2066 case ARM::VST1d8T:
2067 case ARM::VST1d16T:
2068 case ARM::VST1d32T:
2069 case ARM::VST1d64T:
2070 case ARM::VST1d8T_UPD:
2071 case ARM::VST1d16T_UPD:
2072 case ARM::VST1d32T_UPD:
2073 case ARM::VST1d64T_UPD:
2074 case ARM::VST1d8Q:
2075 case ARM::VST1d16Q:
2076 case ARM::VST1d32Q:
2077 case ARM::VST1d64Q:
2078 case ARM::VST1d8Q_UPD:
2079 case ARM::VST1d16Q_UPD:
2080 case ARM::VST1d32Q_UPD:
2081 case ARM::VST1d64Q_UPD:
2082 case ARM::VST2d8:
2083 case ARM::VST2d16:
2084 case ARM::VST2d32:
2085 case ARM::VST2d8_UPD:
2086 case ARM::VST2d16_UPD:
2087 case ARM::VST2d32_UPD:
2088 case ARM::VST2q8:
2089 case ARM::VST2q16:
2090 case ARM::VST2q32:
2091 case ARM::VST2q8_UPD:
2092 case ARM::VST2q16_UPD:
2093 case ARM::VST2q32_UPD:
2094 case ARM::VST3d8:
2095 case ARM::VST3d16:
2096 case ARM::VST3d32:
2097 case ARM::VST3d8_UPD:
2098 case ARM::VST3d16_UPD:
2099 case ARM::VST3d32_UPD:
2100 case ARM::VST4d8:
2101 case ARM::VST4d16:
2102 case ARM::VST4d32:
2103 case ARM::VST4d8_UPD:
2104 case ARM::VST4d16_UPD:
2105 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2106 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2107 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2108 break;
2109 case ARM::VST2b8:
2110 case ARM::VST2b16:
2111 case ARM::VST2b32:
2112 case ARM::VST2b8_UPD:
2113 case ARM::VST2b16_UPD:
2114 case ARM::VST2b32_UPD:
2115 case ARM::VST3q8:
2116 case ARM::VST3q16:
2117 case ARM::VST3q32:
2118 case ARM::VST3q8_UPD:
2119 case ARM::VST3q16_UPD:
2120 case ARM::VST3q32_UPD:
2121 case ARM::VST4q8:
2122 case ARM::VST4q16:
2123 case ARM::VST4q32:
2124 case ARM::VST4q8_UPD:
2125 case ARM::VST4q16_UPD:
2126 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2128 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2129 break;
2130 default:
2131 break;
2132 }
2133
2134 // Third input register
2135 switch (Inst.getOpcode()) {
2136 case ARM::VST1d8T:
2137 case ARM::VST1d16T:
2138 case ARM::VST1d32T:
2139 case ARM::VST1d64T:
2140 case ARM::VST1d8T_UPD:
2141 case ARM::VST1d16T_UPD:
2142 case ARM::VST1d32T_UPD:
2143 case ARM::VST1d64T_UPD:
2144 case ARM::VST1d8Q:
2145 case ARM::VST1d16Q:
2146 case ARM::VST1d32Q:
2147 case ARM::VST1d64Q:
2148 case ARM::VST1d8Q_UPD:
2149 case ARM::VST1d16Q_UPD:
2150 case ARM::VST1d32Q_UPD:
2151 case ARM::VST1d64Q_UPD:
2152 case ARM::VST2q8:
2153 case ARM::VST2q16:
2154 case ARM::VST2q32:
2155 case ARM::VST2q8_UPD:
2156 case ARM::VST2q16_UPD:
2157 case ARM::VST2q32_UPD:
2158 case ARM::VST3d8:
2159 case ARM::VST3d16:
2160 case ARM::VST3d32:
2161 case ARM::VST3d8_UPD:
2162 case ARM::VST3d16_UPD:
2163 case ARM::VST3d32_UPD:
2164 case ARM::VST4d8:
2165 case ARM::VST4d16:
2166 case ARM::VST4d32:
2167 case ARM::VST4d8_UPD:
2168 case ARM::VST4d16_UPD:
2169 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2170 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2171 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2172 break;
2173 case ARM::VST3q8:
2174 case ARM::VST3q16:
2175 case ARM::VST3q32:
2176 case ARM::VST3q8_UPD:
2177 case ARM::VST3q16_UPD:
2178 case ARM::VST3q32_UPD:
2179 case ARM::VST4q8:
2180 case ARM::VST4q16:
2181 case ARM::VST4q32:
2182 case ARM::VST4q8_UPD:
2183 case ARM::VST4q16_UPD:
2184 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2185 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2186 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2187 break;
2188 default:
2189 break;
2190 }
2191
2192 // Fourth input register
2193 switch (Inst.getOpcode()) {
2194 case ARM::VST1d8Q:
2195 case ARM::VST1d16Q:
2196 case ARM::VST1d32Q:
2197 case ARM::VST1d64Q:
2198 case ARM::VST1d8Q_UPD:
2199 case ARM::VST1d16Q_UPD:
2200 case ARM::VST1d32Q_UPD:
2201 case ARM::VST1d64Q_UPD:
2202 case ARM::VST2q8:
2203 case ARM::VST2q16:
2204 case ARM::VST2q32:
2205 case ARM::VST2q8_UPD:
2206 case ARM::VST2q16_UPD:
2207 case ARM::VST2q32_UPD:
2208 case ARM::VST4d8:
2209 case ARM::VST4d16:
2210 case ARM::VST4d32:
2211 case ARM::VST4d8_UPD:
2212 case ARM::VST4d16_UPD:
2213 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2215 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2216 break;
2217 case ARM::VST4q8:
2218 case ARM::VST4q16:
2219 case ARM::VST4q32:
2220 case ARM::VST4q8_UPD:
2221 case ARM::VST4q16_UPD:
2222 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2224 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2225 break;
2226 default:
2227 break;
2228 }
2229
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2230 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2231}
2232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2233static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2234 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2235 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2236
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2237 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2238 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2240 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2241 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2242 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2243 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2244
2245 align *= (1 << size);
2246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2247 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2248 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2249 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2251 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2252 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2253 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2255 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2256 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2257
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2259 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2260 Inst.addOperand(MCOperand::CreateImm(align));
2261
2262 if (Rm == 0xD)
2263 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2264 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2266 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2267 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2268
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2269 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2270}
2271
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2272static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2273 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2274 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2275
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2276 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2277 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2278 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2279 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2280 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2281 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2282 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2283 align *= 2*size;
2284
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2285 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2286 return MCDisassembler::Fail;
2287 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2289 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2291 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2292 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2293
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2295 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2296 Inst.addOperand(MCOperand::CreateImm(align));
2297
2298 if (Rm == 0xD)
2299 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2300 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2302 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2303 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2304
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2305 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306}
2307
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2308static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2309 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2310 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2311
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2312 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2313 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2314 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2315 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2316 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2317
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2318 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2319 return MCDisassembler::Fail;
2320 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2321 return MCDisassembler::Fail;
2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2323 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2324 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2326 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2327 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2328
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2330 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2331 Inst.addOperand(MCOperand::CreateImm(0));
2332
2333 if (Rm == 0xD)
2334 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2335 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2337 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2338 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2339
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2340 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2341}
2342
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2343static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2344 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2345 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2346
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2347 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2348 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2349 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2350 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2351 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2352 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2353 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2354
2355 if (size == 0x3) {
2356 size = 4;
2357 align = 16;
2358 } else {
2359 if (size == 2) {
2360 size = 1 << size;
2361 align *= 8;
2362 } else {
2363 size = 1 << size;
2364 align *= 4*size;
2365 }
2366 }
2367
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2369 return MCDisassembler::Fail;
2370 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2371 return MCDisassembler::Fail;
2372 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2373 return MCDisassembler::Fail;
2374 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2375 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2376 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2378 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2379 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2380
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2382 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2383 Inst.addOperand(MCOperand::CreateImm(align));
2384
2385 if (Rm == 0xD)
2386 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2387 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2389 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2390 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2391
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2392 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2393}
2394
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2395static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2396DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2397 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2398 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2399
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2400 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2401 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2402 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2403 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2404 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2405 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2406 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2407 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2408
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2409 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2410 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2411 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2412 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2413 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2414 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2415 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2416
2417 Inst.addOperand(MCOperand::CreateImm(imm));
2418
2419 switch (Inst.getOpcode()) {
2420 case ARM::VORRiv4i16:
2421 case ARM::VORRiv2i32:
2422 case ARM::VBICiv4i16:
2423 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2425 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2426 break;
2427 case ARM::VORRiv8i16:
2428 case ARM::VORRiv4i32:
2429 case ARM::VBICiv8i16:
2430 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2431 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2432 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2433 break;
2434 default:
2435 break;
2436 }
2437
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2438 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2439}
2440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2441static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2444
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2446 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2447 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2448 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2449 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2450
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2451 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2452 return MCDisassembler::Fail;
2453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2454 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2455 Inst.addOperand(MCOperand::CreateImm(8 << size));
2456
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2457 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2458}
2459
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2460static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2461 uint64_t Address, const void *Decoder) {
2462 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2463 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2464}
2465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2466static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2467 uint64_t Address, const void *Decoder) {
2468 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2469 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2470}
2471
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2472static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2473 uint64_t Address, const void *Decoder) {
2474 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2475 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2476}
2477
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2478static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2479 uint64_t Address, const void *Decoder) {
2480 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2481 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2482}
2483
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2484static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2487
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2488 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2489 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2490 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2491 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2492 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2493 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2494 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2495 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2496
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2498 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2499 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2501 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2502 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2503
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2504 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2506 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2507 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2508
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2510 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2512 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513}
2514
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2515static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2516 uint64_t Address, const void *Decoder) {
2517 // The immediate needs to be a fully instantiated float. However, the
2518 // auto-generated decoder is only able to fill in some of the bits
2519 // necessary. For instance, the 'b' bit is replicated multiple times,
2520 // and is even present in inverted form in one bit. We do a little
2521 // binary parsing here to fill in those missing bits, and then
2522 // reinterpret it all as a float.
2523 union {
2524 uint32_t integer;
2525 float fp;
2526 } fp_conv;
2527
2528 fp_conv.integer = Val;
2529 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2530 fp_conv.integer |= b << 26;
2531 fp_conv.integer |= b << 27;
2532 fp_conv.integer |= b << 28;
2533 fp_conv.integer |= b << 29;
2534 fp_conv.integer |= (~b & 0x1) << 30;
2535
2536 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2537 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538}
2539
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2540static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2541 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2542 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2543
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2544 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2545 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2546
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2547 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2548 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2550 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2551 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2552 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2553 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2554 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2555 case ARM::tADDrSPi:
2556 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2557 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2558 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559
2560 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2561 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2562}
2563
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2564static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2565 uint64_t Address, const void *Decoder) {
2566 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2567 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2568}
2569
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2570static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2571 uint64_t Address, const void *Decoder) {
2572 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2573 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574}
2575
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2576static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577 uint64_t Address, const void *Decoder) {
2578 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2579 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2580}
2581
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2582static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2583 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2584 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2585
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2586 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2587 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2588
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2590 return MCDisassembler::Fail;
2591 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2592 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2593
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2594 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595}
2596
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2597static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2598 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2599 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2600
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2601 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2602 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2603
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2604 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2605 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 Inst.addOperand(MCOperand::CreateImm(imm));
2607
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2608 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609}
2610
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2611static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612 uint64_t Address, const void *Decoder) {
2613 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2614
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2615 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616}
2617
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2618static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619 uint64_t Address, const void *Decoder) {
2620 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2621 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2622
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2623 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624}
2625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2626static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2629
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2631 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2632 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2633
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2635 return MCDisassembler::Fail;
2636 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2637 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638 Inst.addOperand(MCOperand::CreateImm(imm));
2639
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2640 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641}
2642
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2643static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2644 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2645 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2646
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2647 switch (Inst.getOpcode()) {
2648 case ARM::t2PLDs:
2649 case ARM::t2PLDWs:
2650 case ARM::t2PLIs:
2651 break;
2652 default: {
2653 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2655 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2656 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2657 }
2658
2659 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2660 if (Rn == 0xF) {
2661 switch (Inst.getOpcode()) {
2662 case ARM::t2LDRBs:
2663 Inst.setOpcode(ARM::t2LDRBpci);
2664 break;
2665 case ARM::t2LDRHs:
2666 Inst.setOpcode(ARM::t2LDRHpci);
2667 break;
2668 case ARM::t2LDRSHs:
2669 Inst.setOpcode(ARM::t2LDRSHpci);
2670 break;
2671 case ARM::t2LDRSBs:
2672 Inst.setOpcode(ARM::t2LDRSBpci);
2673 break;
2674 case ARM::t2PLDs:
2675 Inst.setOpcode(ARM::t2PLDi12);
2676 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2677 break;
2678 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2679 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2680 }
2681
2682 int imm = fieldFromInstruction32(Insn, 0, 12);
2683 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2684 Inst.addOperand(MCOperand::CreateImm(imm));
2685
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2686 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687 }
2688
2689 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2690 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2691 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2693 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2695 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696}
2697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2698static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2699 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2700 int imm = Val & 0xFF;
2701 if (!(Val & 0x100)) imm *= -1;
2702 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2703
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2704 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705}
2706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2707static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2709 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2710
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2711 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2712 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2715 return MCDisassembler::Fail;
2716 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2717 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2718
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2719 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720}
2721
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2722static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2723 uint64_t Address, const void *Decoder) {
2724 DecodeStatus S = MCDisassembler::Success;
2725
2726 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2727 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2728
2729 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2730 return MCDisassembler::Fail;
2731
2732 Inst.addOperand(MCOperand::CreateImm(imm));
2733
2734 return S;
2735}
2736
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2738 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2739 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2740 if (Val == 0)
2741 imm = INT32_MIN;
2742 else if (!(Val & 0x100))
2743 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2744 Inst.addOperand(MCOperand::CreateImm(imm));
2745
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2746 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2747}
2748
2749
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2750static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2751 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2752 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2753
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2755 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2756
2757 // Some instructions always use an additive offset.
2758 switch (Inst.getOpcode()) {
2759 case ARM::t2LDRT:
2760 case ARM::t2LDRBT:
2761 case ARM::t2LDRHT:
2762 case ARM::t2LDRSBT:
2763 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame^]2764 case ARM::t2STRT:
2765 case ARM::t2STRBT:
2766 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767 imm |= 0x100;
2768 break;
2769 default:
2770 break;
2771 }
2772
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2774 return MCDisassembler::Fail;
2775 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2776 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2777
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2778 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2779}
2780
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2781static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2782 uint64_t Address, const void *Decoder) {
2783 DecodeStatus S = MCDisassembler::Success;
2784
2785 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2786 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2787 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2788 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2789 addr |= Rn << 9;
2790 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2791
2792 if (!load) {
2793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2794 return MCDisassembler::Fail;
2795 }
2796
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2797 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2798 return MCDisassembler::Fail;
2799
2800 if (load) {
2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2802 return MCDisassembler::Fail;
2803 }
2804
2805 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2806 return MCDisassembler::Fail;
2807
2808 return S;
2809}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2810
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2811static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2812 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2814
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2816 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2817
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2819 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820 Inst.addOperand(MCOperand::CreateImm(imm));
2821
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2822 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823}
2824
2825
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2826static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2827 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2828 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2829
2830 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2831 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2832 Inst.addOperand(MCOperand::CreateImm(imm));
2833
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2834 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2835}
2836
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2837static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2838 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2840
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2841 if (Inst.getOpcode() == ARM::tADDrSP) {
2842 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2843 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2844
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2846 return MCDisassembler::Fail;
2847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2848 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2849 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2850 } else if (Inst.getOpcode() == ARM::tADDspr) {
2851 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2852
2853 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2854 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2856 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2857 }
2858
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2859 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2860}
2861
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2862static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2863 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2865 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2866
2867 Inst.addOperand(MCOperand::CreateImm(imod));
2868 Inst.addOperand(MCOperand::CreateImm(flags));
2869
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2870 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2871}
2872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2873static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2874 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2875 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2876 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2877 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2878
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2880 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2881 Inst.addOperand(MCOperand::CreateImm(add));
2882
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2883 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884}
2885
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2886static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2887 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2888 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2889 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890}
2891
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2892static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893 uint64_t Address, const void *Decoder) {
2894 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2895 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896
2897 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2898 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2899}
2900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2901static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2902DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2905
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2906 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2907 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2908 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2909 switch (opc) {
2910 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2911 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2912 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913 Inst.setOpcode(ARM::t2DSB);
2914 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2915 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2916 Inst.setOpcode(ARM::t2DMB);
2917 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2918 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2919 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2920 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921 }
2922
2923 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2924 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925 }
2926
2927 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2928 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2929 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2930 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2931 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2932
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2933 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2934 return MCDisassembler::Fail;
2935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2936 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2938 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939}
2940
2941// Decode a shifted immediate operand. These basically consist
2942// of an 8-bit value, and a 4-bit directive that specifies either
2943// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2944static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2945 uint64_t Address, const void *Decoder) {
2946 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2947 if (ctrl == 0) {
2948 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2949 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2950 switch (byte) {
2951 case 0:
2952 Inst.addOperand(MCOperand::CreateImm(imm));
2953 break;
2954 case 1:
2955 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2956 break;
2957 case 2:
2958 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2959 break;
2960 case 3:
2961 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2962 (imm << 8) | imm));
2963 break;
2964 }
2965 } else {
2966 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2967 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2968 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2969 Inst.addOperand(MCOperand::CreateImm(imm));
2970 }
2971
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2972 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2973}
2974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2975static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2976DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2977 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2979 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2980}
2981
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2982static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2983 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2984 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2985 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2986}
2987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2988static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2989 uint64_t Address, const void *Decoder) {
2990 switch (Val) {
2991 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2992 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2993 case 0xF: // SY
2994 case 0xE: // ST
2995 case 0xB: // ISH
2996 case 0xA: // ISHST
2997 case 0x7: // NSH
2998 case 0x6: // NSHST
2999 case 0x3: // OSH
3000 case 0x2: // OSHST
3001 break;
3002 }
3003
3004 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3005 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3006}
3007
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3008static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3009 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3010 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3011 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3012 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3013}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3015static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3016 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3017 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3018
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3019 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3020 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3021 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3022
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3023 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3024
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3026 return MCDisassembler::Fail;
3027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3028 return MCDisassembler::Fail;
3029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3030 return MCDisassembler::Fail;
3031 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3032 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3033
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3034 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3035}
3036
3037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3038static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3039 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3040 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3041
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3042 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3043 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3044 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3045 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3046
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3047 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3048 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3049
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3050 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3051 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3052
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3054 return MCDisassembler::Fail;
3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3056 return MCDisassembler::Fail;
3057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3058 return MCDisassembler::Fail;
3059 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3060 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3061
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3062 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3063}
3064
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3065static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3066 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3067 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3068
3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3070 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3071 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3072 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3073 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3074 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3075
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3076 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3077
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3079 return MCDisassembler::Fail;
3080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3081 return MCDisassembler::Fail;
3082 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3083 return MCDisassembler::Fail;
3084 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3085 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3086
3087 return S;
3088}
3089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3090static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3093
3094 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3095 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3096 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3097 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3098 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3099 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3101
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3102 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3103 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3104
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3106 return MCDisassembler::Fail;
3107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3108 return MCDisassembler::Fail;
3109 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3110 return MCDisassembler::Fail;
3111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3112 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3113
3114 return S;
3115}
3116
3117
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3118static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3119 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3120 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3121
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3122 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3123 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3124 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3125 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3126 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3127 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3128
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3129 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3130
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3132 return MCDisassembler::Fail;
3133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3134 return MCDisassembler::Fail;
3135 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3136 return MCDisassembler::Fail;
3137 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3138 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3139
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3140 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3141}
3142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3143static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3144 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3145 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3146
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3147 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3148 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3149 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3150 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3151 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3152 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3153
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3154 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3155
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3157 return MCDisassembler::Fail;
3158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3159 return MCDisassembler::Fail;
3160 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3161 return MCDisassembler::Fail;
3162 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3163 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3164
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3165 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3166}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3168static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3169 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3170 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3171
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3172 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3173 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3174 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3175 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3176 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3177
3178 unsigned align = 0;
3179 unsigned index = 0;
3180 switch (size) {
3181 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3182 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3183 case 0:
3184 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3185 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3186 index = fieldFromInstruction32(Insn, 5, 3);
3187 break;
3188 case 1:
3189 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3190 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3191 index = fieldFromInstruction32(Insn, 6, 2);
3192 if (fieldFromInstruction32(Insn, 4, 1))
3193 align = 2;
3194 break;
3195 case 2:
3196 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3198 index = fieldFromInstruction32(Insn, 7, 1);
3199 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3200 align = 4;
3201 }
3202
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3204 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3205 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3207 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3208 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3210 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3211 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3212 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3213 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3215 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3216 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3217 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3218 }
3219
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3220 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3221 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3222 Inst.addOperand(MCOperand::CreateImm(index));
3223
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3224 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3225}
3226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3228 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3229 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3230
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3231 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3232 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3233 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3234 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3235 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3236
3237 unsigned align = 0;
3238 unsigned index = 0;
3239 switch (size) {
3240 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3241 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3242 case 0:
3243 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3244 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3245 index = fieldFromInstruction32(Insn, 5, 3);
3246 break;
3247 case 1:
3248 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3249 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3250 index = fieldFromInstruction32(Insn, 6, 2);
3251 if (fieldFromInstruction32(Insn, 4, 1))
3252 align = 2;
3253 break;
3254 case 2:
3255 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3256 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3257 index = fieldFromInstruction32(Insn, 7, 1);
3258 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3259 align = 4;
3260 }
3261
3262 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3264 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3265 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3267 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3268 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3269 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3270 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3272 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3273 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3274 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3275 }
3276
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3277 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3278 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3279 Inst.addOperand(MCOperand::CreateImm(index));
3280
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3281 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3282}
3283
3284
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3285static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3286 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3287 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3288
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3289 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3290 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3291 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3292 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3293 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3294
3295 unsigned align = 0;
3296 unsigned index = 0;
3297 unsigned inc = 1;
3298 switch (size) {
3299 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3300 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3301 case 0:
3302 index = fieldFromInstruction32(Insn, 5, 3);
3303 if (fieldFromInstruction32(Insn, 4, 1))
3304 align = 2;
3305 break;
3306 case 1:
3307 index = fieldFromInstruction32(Insn, 6, 2);
3308 if (fieldFromInstruction32(Insn, 4, 1))
3309 align = 4;
3310 if (fieldFromInstruction32(Insn, 5, 1))
3311 inc = 2;
3312 break;
3313 case 2:
3314 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3315 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3316 index = fieldFromInstruction32(Insn, 7, 1);
3317 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3318 align = 8;
3319 if (fieldFromInstruction32(Insn, 6, 1))
3320 inc = 2;
3321 break;
3322 }
3323
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3324 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3325 return MCDisassembler::Fail;
3326 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3327 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3328 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3330 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3331 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3333 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3334 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3335 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3336 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3338 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3339 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3340 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3341 }
3342
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3344 return MCDisassembler::Fail;
3345 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3346 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3347 Inst.addOperand(MCOperand::CreateImm(index));
3348
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3349 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3350}
3351
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3352static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3353 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3354 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3355
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3356 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3357 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3358 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3359 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3360 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3361
3362 unsigned align = 0;
3363 unsigned index = 0;
3364 unsigned inc = 1;
3365 switch (size) {
3366 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3367 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3368 case 0:
3369 index = fieldFromInstruction32(Insn, 5, 3);
3370 if (fieldFromInstruction32(Insn, 4, 1))
3371 align = 2;
3372 break;
3373 case 1:
3374 index = fieldFromInstruction32(Insn, 6, 2);
3375 if (fieldFromInstruction32(Insn, 4, 1))
3376 align = 4;
3377 if (fieldFromInstruction32(Insn, 5, 1))
3378 inc = 2;
3379 break;
3380 case 2:
3381 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3382 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3383 index = fieldFromInstruction32(Insn, 7, 1);
3384 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3385 align = 8;
3386 if (fieldFromInstruction32(Insn, 6, 1))
3387 inc = 2;
3388 break;
3389 }
3390
3391 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3393 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3394 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3396 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3397 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3398 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3401 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3403 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3404 }
3405
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3407 return MCDisassembler::Fail;
3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3409 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3410 Inst.addOperand(MCOperand::CreateImm(index));
3411
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3412 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3413}
3414
3415
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3416static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3417 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3418 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3419
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3420 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3421 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3422 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3423 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3424 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3425
3426 unsigned align = 0;
3427 unsigned index = 0;
3428 unsigned inc = 1;
3429 switch (size) {
3430 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3431 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3432 case 0:
3433 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3434 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3435 index = fieldFromInstruction32(Insn, 5, 3);
3436 break;
3437 case 1:
3438 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3439 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3440 index = fieldFromInstruction32(Insn, 6, 2);
3441 if (fieldFromInstruction32(Insn, 5, 1))
3442 inc = 2;
3443 break;
3444 case 2:
3445 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3446 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3447 index = fieldFromInstruction32(Insn, 7, 1);
3448 if (fieldFromInstruction32(Insn, 6, 1))
3449 inc = 2;
3450 break;
3451 }
3452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3454 return MCDisassembler::Fail;
3455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3456 return MCDisassembler::Fail;
3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3458 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3459
3460 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3462 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3463 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3465 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3466 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3467 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3468 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3470 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3471 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3472 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3473 }
3474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3476 return MCDisassembler::Fail;
3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3478 return MCDisassembler::Fail;
3479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3480 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3481 Inst.addOperand(MCOperand::CreateImm(index));
3482
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3483 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484}
3485
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3486static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3487 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3488 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3489
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3490 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3491 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3492 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3493 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3494 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3495
3496 unsigned align = 0;
3497 unsigned index = 0;
3498 unsigned inc = 1;
3499 switch (size) {
3500 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3501 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3502 case 0:
3503 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3504 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3505 index = fieldFromInstruction32(Insn, 5, 3);
3506 break;
3507 case 1:
3508 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3509 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3510 index = fieldFromInstruction32(Insn, 6, 2);
3511 if (fieldFromInstruction32(Insn, 5, 1))
3512 inc = 2;
3513 break;
3514 case 2:
3515 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3516 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3517 index = fieldFromInstruction32(Insn, 7, 1);
3518 if (fieldFromInstruction32(Insn, 6, 1))
3519 inc = 2;
3520 break;
3521 }
3522
3523 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3525 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3526 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3528 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3529 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3530 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3531 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3533 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3534 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3535 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3536 }
3537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3539 return MCDisassembler::Fail;
3540 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3541 return MCDisassembler::Fail;
3542 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3543 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3544 Inst.addOperand(MCOperand::CreateImm(index));
3545
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3546 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3547}
3548
3549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3550static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3551 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3552 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3553
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3554 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3556 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3557 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3558 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3559
3560 unsigned align = 0;
3561 unsigned index = 0;
3562 unsigned inc = 1;
3563 switch (size) {
3564 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3565 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3566 case 0:
3567 if (fieldFromInstruction32(Insn, 4, 1))
3568 align = 4;
3569 index = fieldFromInstruction32(Insn, 5, 3);
3570 break;
3571 case 1:
3572 if (fieldFromInstruction32(Insn, 4, 1))
3573 align = 8;
3574 index = fieldFromInstruction32(Insn, 6, 2);
3575 if (fieldFromInstruction32(Insn, 5, 1))
3576 inc = 2;
3577 break;
3578 case 2:
3579 if (fieldFromInstruction32(Insn, 4, 2))
3580 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3581 index = fieldFromInstruction32(Insn, 7, 1);
3582 if (fieldFromInstruction32(Insn, 6, 1))
3583 inc = 2;
3584 break;
3585 }
3586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3588 return MCDisassembler::Fail;
3589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3590 return MCDisassembler::Fail;
3591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3594 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3595
3596 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3598 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3599 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3601 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3603 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3604 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3606 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3607 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3608 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 }
3610
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3612 return MCDisassembler::Fail;
3613 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3614 return MCDisassembler::Fail;
3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3616 return MCDisassembler::Fail;
3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3618 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3619 Inst.addOperand(MCOperand::CreateImm(index));
3620
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3621 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622}
3623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3624static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3625 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3626 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3627
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3628 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3629 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3630 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3631 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3632 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3633
3634 unsigned align = 0;
3635 unsigned index = 0;
3636 unsigned inc = 1;
3637 switch (size) {
3638 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3639 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3640 case 0:
3641 if (fieldFromInstruction32(Insn, 4, 1))
3642 align = 4;
3643 index = fieldFromInstruction32(Insn, 5, 3);
3644 break;
3645 case 1:
3646 if (fieldFromInstruction32(Insn, 4, 1))
3647 align = 8;
3648 index = fieldFromInstruction32(Insn, 6, 2);
3649 if (fieldFromInstruction32(Insn, 5, 1))
3650 inc = 2;
3651 break;
3652 case 2:
3653 if (fieldFromInstruction32(Insn, 4, 2))
3654 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3655 index = fieldFromInstruction32(Insn, 7, 1);
3656 if (fieldFromInstruction32(Insn, 6, 1))
3657 inc = 2;
3658 break;
3659 }
3660
3661 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3663 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3666 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3667 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3668 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3669 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3671 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3672 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3673 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3674 }
3675
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3677 return MCDisassembler::Fail;
3678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3683 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3684 Inst.addOperand(MCOperand::CreateImm(index));
3685
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3686 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3687}
3688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3689static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3690 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3691 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3692 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3693 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3694 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3695 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3696 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3697
3698 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3699 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3701 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3702 return MCDisassembler::Fail;
3703 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3704 return MCDisassembler::Fail;
3705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3706 return MCDisassembler::Fail;
3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3708 return MCDisassembler::Fail;
3709 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3710 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3711
3712 return S;
3713}
3714
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3715static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3716 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3717 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3718 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3719 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3720 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3721 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3722 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3723
3724 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3725 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3726
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3728 return MCDisassembler::Fail;
3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3732 return MCDisassembler::Fail;
3733 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3734 return MCDisassembler::Fail;
3735 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3736 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3737
3738 return S;
3739}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3742 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3743 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3744 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3745 // The InstPrinter needs to have the low bit of the predicate in
3746 // the mask operand to be able to print it properly.
3747 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3748
3749 if (pred == 0xF) {
3750 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3751 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3752 }
3753
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3754 if ((mask & 0xF) == 0) {
3755 // Preserve the high bit of the mask, which is the low bit of
3756 // the predicate.
3757 mask &= 0x10;
3758 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3759 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3760 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3761
3762 Inst.addOperand(MCOperand::CreateImm(pred));
3763 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3764 return S;
3765}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3766
3767static DecodeStatus
3768DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3769 uint64_t Address, const void *Decoder) {
3770 DecodeStatus S = MCDisassembler::Success;
3771
3772 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3773 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3774 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3775 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3776 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3777 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3778 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3779 bool writeback = (W == 1) | (P == 0);
3780
3781 addr |= (U << 8) | (Rn << 9);
3782
3783 if (writeback && (Rn == Rt || Rn == Rt2))
3784 Check(S, MCDisassembler::SoftFail);
3785 if (Rt == Rt2)
3786 Check(S, MCDisassembler::SoftFail);
3787
3788 // Rt
3789 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3790 return MCDisassembler::Fail;
3791 // Rt2
3792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3793 return MCDisassembler::Fail;
3794 // Writeback operand
3795 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3796 return MCDisassembler::Fail;
3797 // addr
3798 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3799 return MCDisassembler::Fail;
3800
3801 return S;
3802}
3803
3804static DecodeStatus
3805DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3806 uint64_t Address, const void *Decoder) {
3807 DecodeStatus S = MCDisassembler::Success;
3808
3809 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3810 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3811 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3812 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3813 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3814 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3815 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3816 bool writeback = (W == 1) | (P == 0);
3817
3818 addr |= (U << 8) | (Rn << 9);
3819
3820 if (writeback && (Rn == Rt || Rn == Rt2))
3821 Check(S, MCDisassembler::SoftFail);
3822
3823 // Writeback operand
3824 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3825 return MCDisassembler::Fail;
3826 // Rt
3827 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3828 return MCDisassembler::Fail;
3829 // Rt2
3830 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3831 return MCDisassembler::Fail;
3832 // addr
3833 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3834 return MCDisassembler::Fail;
3835
3836 return S;
3837}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3838
3839static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3840 uint64_t Address, const void *Decoder) {
3841 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3842 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3843 if (sign1 != sign2) return MCDisassembler::Fail;
3844
3845 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3846 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3847 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3848 Val |= sign1 << 12;
3849 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3850
3851 return MCDisassembler::Success;
3852}
3853