Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 1 | //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Duraid Madina and is distributed under the |
| 6 | // University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the IA64 implementation of the MRegisterInfo class. This |
| 11 | // file is responsible for the frame pointer elimination optimization on IA64. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "IA64.h" |
| 16 | #include "IA64RegisterInfo.h" |
| 17 | #include "IA64InstrBuilder.h" |
| 18 | #include "IA64MachineFunctionInfo.h" |
| 19 | #include "llvm/Constants.h" |
| 20 | #include "llvm/Type.h" |
| 21 | #include "llvm/CodeGen/ValueTypes.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineLocation.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetFrameInfo.h" |
| 27 | #include "llvm/Target/TargetMachine.h" |
| 28 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 29 | #include "llvm/Target/TargetInstrInfo.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 30 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/BitVector.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 32 | #include "llvm/ADT/STLExtras.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 33 | using namespace llvm; |
| 34 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 35 | IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii) |
| 36 | : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP), |
| 37 | TII(tii) {} |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 38 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 39 | void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 0ffb1a5 | 2005-09-30 01:30:55 +0000 | [diff] [blame] | 40 | MachineBasicBlock::iterator MI, |
| 41 | unsigned SrcReg, int FrameIdx, |
| 42 | const TargetRegisterClass *RC) const{ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 43 | |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 44 | if (RC == IA64::FPRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 45 | BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) |
| 46 | .addReg(SrcReg, false, false, true); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 47 | } else if (RC == IA64::GRRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 48 | BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx) |
| 49 | .addReg(SrcReg, false, false, true); |
| 50 | } else if (RC == IA64::PRRegisterClass) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 51 | /* we use IA64::r2 as a temporary register for doing this hackery. */ |
| 52 | // first we load 0: |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 53 | BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 54 | // then conditionally add 1: |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 55 | BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 56 | .addImm(1).addReg(SrcReg, false, false, true); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 57 | // and then store it to the stack |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 58 | BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 59 | } else assert(0 && |
| 60 | "sorry, I don't know how to store this sort of reg in the stack\n"); |
| 61 | } |
| 62 | |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 63 | void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 64 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 65 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 66 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 67 | unsigned Opc = 0; |
| 68 | if (RC == IA64::FPRegisterClass) { |
| 69 | Opc = IA64::STF8; |
| 70 | } else if (RC == IA64::GRRegisterClass) { |
| 71 | Opc = IA64::ST8; |
| 72 | } else if (RC == IA64::PRRegisterClass) { |
| 73 | Opc = IA64::ST1; |
| 74 | } else { |
| 75 | assert(0 && |
| 76 | "sorry, I don't know how to store this sort of reg\n"); |
| 77 | } |
| 78 | |
| 79 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); |
| 80 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 81 | MachineOperand &MO = Addr[i]; |
| 82 | if (MO.isRegister()) |
| 83 | MIB.addReg(MO.getReg()); |
| 84 | else if (MO.isImmediate()) |
| 85 | MIB.addImm(MO.getImmedValue()); |
| 86 | else |
| 87 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 88 | } |
| 89 | MIB.addReg(SrcReg, false, false, true); |
| 90 | NewMIs.push_back(MIB); |
| 91 | return; |
| 92 | |
| 93 | } |
| 94 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 95 | void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 0ffb1a5 | 2005-09-30 01:30:55 +0000 | [diff] [blame] | 96 | MachineBasicBlock::iterator MI, |
| 97 | unsigned DestReg, int FrameIdx, |
| 98 | const TargetRegisterClass *RC)const{ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 99 | |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 100 | if (RC == IA64::FPRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 101 | BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 102 | } else if (RC == IA64::GRRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 103 | BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 104 | } else if (RC == IA64::PRRegisterClass) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 105 | // first we load a byte from the stack into r2, our 'predicate hackery' |
| 106 | // scratch reg |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 107 | BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 108 | // then we compare it to zero. If it _is_ zero, compare-not-equal to |
| 109 | // r0 gives us 0, which is what we want, so that's nice. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 110 | BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 111 | } else assert(0 && |
| 112 | "sorry, I don't know how to load this sort of reg from the stack\n"); |
| 113 | } |
| 114 | |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 115 | void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 116 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 117 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 118 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 119 | unsigned Opc = 0; |
| 120 | if (RC == IA64::FPRegisterClass) { |
| 121 | Opc = IA64::LDF8; |
| 122 | } else if (RC == IA64::GRRegisterClass) { |
| 123 | Opc = IA64::LD8; |
| 124 | } else if (RC == IA64::PRRegisterClass) { |
| 125 | Opc = IA64::LD1; |
| 126 | } else { |
| 127 | assert(0 && |
| 128 | "sorry, I don't know how to store this sort of reg\n"); |
| 129 | } |
| 130 | |
| 131 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); |
| 132 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 133 | MachineOperand &MO = Addr[i]; |
| 134 | if (MO.isRegister()) |
| 135 | MIB.addReg(MO.getReg()); |
| 136 | else if (MO.isImmediate()) |
| 137 | MIB.addImm(MO.getImmedValue()); |
| 138 | else |
| 139 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 140 | } |
| 141 | NewMIs.push_back(MIB); |
| 142 | return; |
| 143 | } |
| 144 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 145 | void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 146 | MachineBasicBlock::iterator MI, |
| 147 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 148 | const TargetRegisterClass *DestRC, |
| 149 | const TargetRegisterClass *SrcRC) const { |
| 150 | if (DestRC != SrcRC) { |
| 151 | cerr << "Not yet supported!"; |
| 152 | abort(); |
| 153 | } |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 154 | |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 155 | if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 156 | // (SrcReg) DestReg = cmp.eq.unc(r0, r0) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 157 | BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 158 | .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 159 | else // otherwise, MOV works (for both gen. regs and FP regs) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 160 | BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 161 | } |
| 162 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 163 | void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 164 | MachineBasicBlock::iterator I, |
| 165 | unsigned DestReg, |
| 166 | const MachineInstr *Orig) const { |
| 167 | MachineInstr *MI = Orig->clone(); |
| 168 | MI->getOperand(0).setReg(DestReg); |
| 169 | MBB.insert(I, MI); |
| 170 | } |
| 171 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 172 | const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) |
| 173 | const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 174 | static const unsigned CalleeSavedRegs[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 175 | IA64::r5, 0 |
| 176 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 177 | return CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 181 | IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 182 | static const TargetRegisterClass * const CalleeSavedRegClasses[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 183 | &IA64::GRRegClass, 0 |
| 184 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 185 | return CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 186 | } |
| 187 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 188 | BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 189 | BitVector Reserved(getNumRegs()); |
| 190 | Reserved.set(IA64::r0); |
| 191 | Reserved.set(IA64::r1); |
| 192 | Reserved.set(IA64::r2); |
| 193 | Reserved.set(IA64::r5); |
| 194 | Reserved.set(IA64::r12); |
| 195 | Reserved.set(IA64::r13); |
| 196 | Reserved.set(IA64::r22); |
| 197 | Reserved.set(IA64::rp); |
| 198 | return Reserved; |
| 199 | } |
| 200 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 201 | //===----------------------------------------------------------------------===// |
| 202 | // Stack Frame Processing methods |
| 203 | //===----------------------------------------------------------------------===// |
| 204 | |
| 205 | // hasFP - Return true if the specified function should have a dedicated frame |
| 206 | // pointer register. This is true if the function has variable sized allocas or |
| 207 | // if frame pointer elimination is disabled. |
| 208 | // |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 209 | bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 210 | return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); |
| 211 | } |
| 212 | |
| 213 | void IA64RegisterInfo:: |
| 214 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 215 | MachineBasicBlock::iterator I) const { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 216 | if (hasFP(MF)) { |
| 217 | // If we have a frame pointer, turn the adjcallstackup instruction into a |
| 218 | // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP, |
| 219 | // <amt>' |
| 220 | MachineInstr *Old = I; |
| 221 | unsigned Amount = Old->getOperand(0).getImmedValue(); |
| 222 | if (Amount != 0) { |
| 223 | // We need to keep the stack aligned properly. To do this, we round the |
| 224 | // amount of space needed for the outgoing arguments up to the next |
| 225 | // alignment boundary. |
| 226 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 227 | Amount = (Amount+Align-1)/Align*Align; |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 228 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 229 | MachineInstr *New; |
| 230 | if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 231 | New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 232 | .addImm(-Amount); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 233 | } else { |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 234 | assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 235 | New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 236 | .addImm(Amount); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | // Replace the pseudo instruction with a new instruction... |
| 240 | MBB.insert(I, New); |
| 241 | } |
| 242 | } |
| 243 | |
| 244 | MBB.erase(I); |
| 245 | } |
| 246 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 247 | void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 248 | int SPAdj, RegScavenger *RS)const{ |
| 249 | assert(SPAdj == 0 && "Unexpected"); |
| 250 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 251 | unsigned i = 0; |
| 252 | MachineInstr &MI = *II; |
| 253 | MachineBasicBlock &MBB = *MI.getParent(); |
| 254 | MachineFunction &MF = *MBB.getParent(); |
| 255 | |
| 256 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 257 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 258 | while (!MI.getOperand(i).isFrameIndex()) { |
| 259 | ++i; |
| 260 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 261 | } |
| 262 | |
| 263 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
| 264 | |
| 265 | // choose a base register: ( hasFP? framepointer : stack pointer ) |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 266 | unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 267 | // Add the base register |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 268 | MI.getOperand(i).ChangeToRegister(BaseRegister, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 269 | |
| 270 | // Now add the frame object offset to the offset from r1. |
| 271 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); |
| 272 | |
| 273 | // If we're not using a Frame Pointer that has been set to the value of the |
| 274 | // SP before having the stack size subtracted from it, then add the stack size |
| 275 | // to Offset to get the correct offset. |
| 276 | Offset += MF.getFrameInfo()->getStackSize(); |
| 277 | |
| 278 | // XXX: we use 'r22' as another hack+slash temporary register here :( |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 279 | if (Offset <= 8191 && Offset >= -8192) { // smallish offset |
| 280 | // Fix up the old: |
| 281 | MI.getOperand(i).ChangeToRegister(IA64::r22, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 282 | //insert the new |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 283 | MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 284 | .addReg(BaseRegister).addImm(Offset); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 285 | MBB.insert(II, nMI); |
| 286 | } else { // it's big |
| 287 | //fix up the old: |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 288 | MI.getOperand(i).ChangeToRegister(IA64::r22, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 289 | MachineInstr* nMI; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 290 | nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 291 | MBB.insert(II, nMI); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 292 | nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 293 | .addReg(IA64::r22); |
| 294 | MBB.insert(II, nMI); |
| 295 | } |
| 296 | |
| 297 | } |
| 298 | |
| 299 | void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { |
| 300 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 301 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 302 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 303 | MachineInstr *MI; |
| 304 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 305 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 306 | // first, we handle the 'alloc' instruction, that should be right up the |
| 307 | // top of any function |
| 308 | static const unsigned RegsInOrder[96] = { // there are 96 GPRs the |
| 309 | // RSE worries about |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 310 | IA64::r32, IA64::r33, IA64::r34, IA64::r35, |
| 311 | IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41, |
| 312 | IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47, |
| 313 | IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53, |
| 314 | IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59, |
| 315 | IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65, |
| 316 | IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71, |
| 317 | IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77, |
| 318 | IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83, |
| 319 | IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89, |
| 320 | IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95, |
| 321 | IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101, |
| 322 | IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107, |
| 323 | IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113, |
| 324 | IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119, |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 325 | IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125, |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 326 | IA64::r126, IA64::r127 }; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 327 | |
| 328 | unsigned numStackedGPRsUsed=0; |
| 329 | for(int i=0; i<96; i++) { |
| 330 | if(MF.isPhysRegUsed(RegsInOrder[i])) |
| 331 | numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int) |
| 332 | } |
| 333 | |
| 334 | unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; |
| 335 | |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 336 | // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ |
| 337 | // a pseudo_alloc in the MBB) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 338 | unsigned dstRegOfPseudoAlloc; |
| 339 | for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) { |
| 340 | assert(MBBI != MBB.end()); |
| 341 | if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) { |
| 342 | dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg(); |
| 343 | break; |
| 344 | } |
| 345 | } |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 346 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 347 | MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 348 | addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); |
| 349 | MBB.insert(MBBI, MI); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 350 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 351 | // Get the number of bytes to allocate from the FrameInfo |
| 352 | unsigned NumBytes = MFI->getStackSize(); |
| 353 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 354 | if(FP) |
| 355 | NumBytes += 8; // reserve space for the old FP |
| 356 | |
| 357 | // Do we need to allocate space on the stack? |
| 358 | if (NumBytes == 0) |
| 359 | return; |
| 360 | |
| 361 | // Add 16 bytes at the bottom of the stack (scratch area) |
| 362 | // and round the size to a multiple of the alignment. |
| 363 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 364 | unsigned Size = 16 + (FP ? 8 : 0); |
| 365 | NumBytes = (NumBytes+Size+Align-1)/Align*Align; |
| 366 | |
| 367 | // Update frame info to pretend that this is part of the stack... |
| 368 | MFI->setStackSize(NumBytes); |
| 369 | |
| 370 | // adjust stack pointer: r12 -= numbytes |
| 371 | if (NumBytes <= 8191) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 372 | MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 373 | addImm(-NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 374 | MBB.insert(MBBI, MI); |
| 375 | } else { // we use r22 as a scratch register here |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 376 | MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 377 | // FIXME: MOVLSI32 expects a _u_32imm |
| 378 | MBB.insert(MBBI, MI); // first load the decrement into r22 |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 379 | MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 380 | MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr) |
| 381 | } |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 382 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 383 | // now if we need to, save the old FP and set the new |
| 384 | if (FP) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 385 | MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 386 | MBB.insert(MBBI, MI); |
| 387 | // this must be the last instr in the prolog ? (XXX: why??) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 388 | MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 389 | MBB.insert(MBBI, MI); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 390 | } |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 391 | |
| 392 | } |
| 393 | |
| 394 | void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, |
| 395 | MachineBasicBlock &MBB) const { |
| 396 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 397 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
| 398 | MachineInstr *MI; |
| 399 | assert(MBBI->getOpcode() == IA64::RET && |
| 400 | "Can only insert epilog into returning blocks"); |
| 401 | |
| 402 | bool FP = hasFP(MF); |
| 403 | |
| 404 | // Get the number of bytes allocated from the FrameInfo... |
| 405 | unsigned NumBytes = MFI->getStackSize(); |
| 406 | |
| 407 | //now if we need to, restore the old FP |
| 408 | if (FP) |
| 409 | { |
| 410 | //copy the FP into the SP (discards allocas) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 411 | MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 412 | MBB.insert(MBBI, MI); |
| 413 | //restore the FP |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 414 | MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 415 | MBB.insert(MBBI, MI); |
| 416 | } |
| 417 | |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 418 | if (NumBytes != 0) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 419 | { |
| 420 | if (NumBytes <= 8191) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 421 | MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 422 | addImm(NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 423 | MBB.insert(MBBI, MI); |
| 424 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 425 | MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 426 | MBB.insert(MBBI, MI); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 427 | MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 428 | addReg(IA64::r22); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 429 | MBB.insert(MBBI, MI); |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | } |
| 434 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 435 | unsigned IA64RegisterInfo::getRARegister() const { |
| 436 | assert(0 && "What is the return address register"); |
| 437 | return 0; |
| 438 | } |
| 439 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 440 | unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 441 | return hasFP(MF) ? IA64::r5 : IA64::r12; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 442 | } |
| 443 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 444 | unsigned IA64RegisterInfo::getEHExceptionRegister() const { |
| 445 | assert(0 && "What is the exception register"); |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | unsigned IA64RegisterInfo::getEHHandlerRegister() const { |
| 450 | assert(0 && "What is the exception handler register"); |
| 451 | return 0; |
| 452 | } |
| 453 | |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame^] | 454 | int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const { |
| 455 | assert(0 && "What is the dwarf register number"); |
| 456 | return -1; |
| 457 | } |
| 458 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 459 | #include "IA64GenRegisterInfo.inc" |
| 460 | |