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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a wrapper class for the 'Instruction' TableGen class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef CODEGEN_INSTRUCTION_H
15#define CODEGEN_INSTRUCTION_H
16
17#include "llvm/CodeGen/ValueTypes.h"
18#include <string>
19#include <vector>
20#include <utility>
21
22namespace llvm {
23 class Record;
24 class DagInit;
25
26 class CodeGenInstruction {
27 public:
28 Record *TheDef; // The actual record defining this instruction.
29 std::string Name; // Contents of the 'Name' field.
30 std::string Namespace; // The namespace the instruction is in.
31
32 /// AsmString - The format string used to emit a .s file for the
33 /// instruction.
34 std::string AsmString;
35
36 /// OperandInfo - The information we keep track of for each operand in the
37 /// operand list for a tablegen instruction.
38 struct OperandInfo {
39 /// Rec - The definition this operand is declared as.
40 ///
41 Record *Rec;
42
43 /// Name - If this operand was assigned a symbolic name, this is it,
44 /// otherwise, it's empty.
45 std::string Name;
46
47 /// PrinterMethodName - The method used to print operands of this type in
48 /// the asmprinter.
49 std::string PrinterMethodName;
50
51 /// MIOperandNo - Currently (this is meant to be phased out), some logical
52 /// operands correspond to multiple MachineInstr operands. In the X86
53 /// target for example, one address operand is represented as 4
54 /// MachineOperands. Because of this, the operand number in the
55 /// OperandList may not match the MachineInstr operand num. Until it
56 /// does, this contains the MI operand index of this operand.
57 unsigned MIOperandNo;
58 unsigned MINumOperands; // The number of operands.
59
60 /// DoNotEncode - Bools are set to true in this vector for each operand in
61 /// the DisableEncoding list. These should not be emitted by the code
62 /// emitter.
63 std::vector<bool> DoNotEncode;
64
65 /// MIOperandInfo - Default MI operand type. Note an operand may be made
66 /// up of multiple MI operands.
67 DagInit *MIOperandInfo;
68
69 /// Constraint info for this operand. This operand can have pieces, so we
70 /// track constraint info for each.
71 std::vector<std::string> Constraints;
72
73 OperandInfo(Record *R, const std::string &N, const std::string &PMN,
74 unsigned MION, unsigned MINO, DagInit *MIOI)
75 : Rec(R), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
76 MINumOperands(MINO), MIOperandInfo(MIOI) {}
77 };
78
Evan Chengb783fa32007-07-19 01:14:50 +000079 /// NumDefs - Number of def operands declared.
80 ///
81 unsigned NumDefs;
82
Dan Gohmanf17a25c2007-07-18 16:29:46 +000083 /// OperandList - The list of declared operands, along with their declared
84 /// type (which is a record).
85 std::vector<OperandInfo> OperandList;
86
87 // Various boolean values we track for the instruction.
88 bool isReturn;
89 bool isBranch;
90 bool isBarrier;
91 bool isCall;
92 bool isLoad;
93 bool isStore;
94 bool isPredicable;
95 bool isConvertibleToThreeAddress;
96 bool isCommutable;
97 bool isTerminator;
98 bool isReMaterializable;
99 bool hasDelaySlot;
100 bool usesCustomDAGSchedInserter;
101 bool hasVariableNumberOfOperands;
102 bool hasCtrlDep;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000103 bool isNotDuplicable;
104 bool hasOptionalDef;
105
106 /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
107 /// where $foo is a whole operand and $foo.bar refers to a suboperand.
108 /// This throws an exception if the name is invalid. If AllowWholeOp is
109 /// true, references to operands with suboperands are allowed, otherwise
110 /// not.
111 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
112 bool AllowWholeOp = true);
113
114 /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
115 /// flat machineinstr operand #.
116 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
117 return OperandList[Op.first].MIOperandNo + Op.second;
118 }
119
120 /// getSubOperandNumber - Unflatten a operand number into an
121 /// operand/suboperand pair.
122 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
123 for (unsigned i = 0; ; ++i) {
124 assert(i < OperandList.size() && "Invalid flat operand #");
125 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
126 return std::make_pair(i, Op-OperandList[i].MIOperandNo);
127 }
128 }
129
130
131 /// isFlatOperandNotEmitted - Return true if the specified flat operand #
132 /// should not be emitted with the code emitter.
133 bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
134 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
135 if (OperandList[Op.first].DoNotEncode.size() > Op.second)
136 return OperandList[Op.first].DoNotEncode[Op.second];
137 return false;
138 }
139
140 CodeGenInstruction(Record *R, const std::string &AsmStr);
141
142 /// getOperandNamed - Return the index of the operand with the specified
143 /// non-empty name. If the instruction does not have an operand with the
144 /// specified name, throw an exception.
145 unsigned getOperandNamed(const std::string &Name) const;
146 };
147}
148
149#endif