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gerrit-public.fairphone.software / platform / external / llvm / fa1ebc6abe95b79b7f82030eea53586a8704eb7e / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 87a5f019d4a937946478f5841c872b685c6c08c7 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]48 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]54 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]73 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]79 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]99 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]128static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]130static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]131 unsigned RegNo, uint64_t Address,
132 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]133
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]134static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]136static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]138static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]140static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]142static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]144static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]146
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]147static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]148 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]149static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]150 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]151static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]152 unsigned Insn,
153 uint64_t Address,
154 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]155static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]157static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
163
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 unsigned Insn,
166 uint64_t Adddress,
167 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]184static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
185 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]202static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]204static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]210static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]212static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]214static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]216static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]218static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
262
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
326
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]327static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]328 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame^]329static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331#include "ARMGenDisassemblerTables.inc"
332#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]333#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]334
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]335static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
336 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]337}
338
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]339static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
340 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]341}
342
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]343const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]344 return instInfoARM;
345}
346
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]347const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]348 return instInfoARM;
349}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]351DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]352 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]353 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]354 raw_ostream &os,
355 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]356 CommentStream = &cs;
357
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 uint8_t bytes[4];
359
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]360 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
361 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
362
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]364 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
365 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]366 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]367 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]368
369 // Encoded as a small-endian 32-bit word in the stream.
370 uint32_t insn = (bytes[3] << 24) |
371 (bytes[2] << 16) |
372 (bytes[1] << 8) |
373 (bytes[0] << 0);
374
375 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]376 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]377 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]378 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]379 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]380 }
381
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // VFP and NEON instructions, similarly, are shared between ARM
383 // and Thumb modes.
384 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]385 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]386 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]387 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]388 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]389 }
390
391 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]392 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]393 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]394 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]395 // Add a fake predicate operand, because we share these instruction
396 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]397 if (!DecodePredicateOperand(MI, 0xE, Address, this))
398 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]399 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]400 }
401
402 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]403 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]404 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]405 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]406 // Add a fake predicate operand, because we share these instruction
407 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]408 if (!DecodePredicateOperand(MI, 0xE, Address, this))
409 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]410 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]411 }
412
413 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]414 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]415 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]416 Size = 4;
417 // Add a fake predicate operand, because we share these instruction
418 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]419 if (!DecodePredicateOperand(MI, 0xE, Address, this))
420 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]421 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]422 }
423
424 MI.clear();
425
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]426 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]427 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]428}
429
430namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]431extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]432}
433
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]434/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
435/// immediate Value in the MCInst. The immediate Value has had any PC
436/// adjustment made by the caller. If the instruction is a branch instruction
437/// then isBranch is true, else false. If the getOpInfo() function was set as
438/// part of the setupForSymbolicDisassembly() call then that function is called
439/// to get any symbolic information at the Address for this instruction. If
440/// that returns non-zero then the symbolic information it returns is used to
441/// create an MCExpr and that is added as an operand to the MCInst. If
442/// getOpInfo() returns zero and isBranch is true then a symbol look up for
443/// Value is done and if a symbol is found an MCExpr is created with that, else
444/// an MCExpr with Value is created. This function returns true if it adds an
445/// operand to the MCInst and false otherwise.
446static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
447 bool isBranch, uint64_t InstSize,
448 MCInst &MI, const void *Decoder) {
449 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
450 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]451 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]452 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]453 SymbolicOp.Value = Value;
454 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]455
456 if (!getOpInfo ||
457 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
458 // Clear SymbolicOp.Value from above and also all other fields.
459 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
460 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
461 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]462 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]463 uint64_t ReferenceType;
464 if (isBranch)
465 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
466 else
467 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
468 const char *ReferenceName;
469 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
470 &ReferenceName);
471 if (Name) {
472 SymbolicOp.AddSymbol.Name = Name;
473 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]474 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]475 // For branches always create an MCExpr so it gets printed as hex address.
476 else if (isBranch) {
477 SymbolicOp.Value = Value;
478 }
479 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
480 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
481 if (!Name && !isBranch)
482 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]483 }
484
485 MCContext *Ctx = Dis->getMCContext();
486 const MCExpr *Add = NULL;
487 if (SymbolicOp.AddSymbol.Present) {
488 if (SymbolicOp.AddSymbol.Name) {
489 StringRef Name(SymbolicOp.AddSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Sub = NULL;
498 if (SymbolicOp.SubtractSymbol.Present) {
499 if (SymbolicOp.SubtractSymbol.Name) {
500 StringRef Name(SymbolicOp.SubtractSymbol.Name);
501 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
502 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
503 } else {
504 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
505 }
506 }
507
508 const MCExpr *Off = NULL;
509 if (SymbolicOp.Value != 0)
510 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
511
512 const MCExpr *Expr;
513 if (Sub) {
514 const MCExpr *LHS;
515 if (Add)
516 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
517 else
518 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
519 if (Off != 0)
520 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
521 else
522 Expr = LHS;
523 } else if (Add) {
524 if (Off != 0)
525 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
526 else
527 Expr = Add;
528 } else {
529 if (Off != 0)
530 Expr = Off;
531 else
532 Expr = MCConstantExpr::Create(0, *Ctx);
533 }
534
535 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
536 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
537 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
538 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
539 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
540 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]541 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]542 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]543
544 return true;
545}
546
547/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
548/// referenced by a load instruction with the base register that is the Pc.
549/// These can often be values in a literal pool near the Address of the
550/// instruction. The Address of the instruction and its immediate Value are
551/// used as a possible literal pool entry. The SymbolLookUp call back will
552/// return the name of a symbol referenced by the the literal pool's entry if
553/// the referenced address is that of a symbol. Or it will return a pointer to
554/// a literal 'C' string if the referenced address of the literal pool's entry
555/// is an address into a section with 'C' string literals.
556static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]557 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
559 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
560 if (SymbolLookUp) {
561 void *DisInfo = Dis->getDisInfoBlock();
562 uint64_t ReferenceType;
563 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
564 const char *ReferenceName;
565 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
566 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
567 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
568 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
569 }
570}
571
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]572// Thumb1 instructions don't have explicit S bits. Rather, they
573// implicitly set CPSR. Since it's not represented in the encoding, the
574// auto-generated decoder won't inject the CPSR operand. We need to fix
575// that as a post-pass.
576static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
577 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]580 for (unsigned i = 0; i < NumOps; ++i, ++I) {
581 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]583 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]584 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
585 return;
586 }
587 }
588
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]589 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590}
591
592// Most Thumb instructions don't have explicit predicates in the
593// encoding, but rather get their predicates from IT context. We need
594// to fix up the predicate operands using this context information as a
595// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]596MCDisassembler::DecodeStatus
597ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]598 MCDisassembler::DecodeStatus S = Success;
599
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]600 // A few instructions actually have predicates encoded in them. Don't
601 // try to overwrite it if we're seeing one of those.
602 switch (MI.getOpcode()) {
603 case ARM::tBcc:
604 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]605 case ARM::tCBZ:
606 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]607 case ARM::tCPS:
608 case ARM::t2CPS3p:
609 case ARM::t2CPS2p:
610 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]611 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]612 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]613 // Some instructions (mostly conditional branches) are not
614 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]615 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]616 S = SoftFail;
617 else
618 return Success;
619 break;
620 case ARM::tB:
621 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]622 case ARM::t2TBB:
623 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]624 // Some instructions (mostly unconditional branches) can
625 // only appears at the end of, or outside of, an IT.
626 if (ITBlock.size() > 1)
627 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]628 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 default:
630 break;
631 }
632
633 // If we're in an IT block, base the predicate on that. Otherwise,
634 // assume a predicate of AL.
635 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]636 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]638 if (CC == 0xF)
639 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]640 ITBlock.pop_back();
641 } else
642 CC = ARMCC::AL;
643
644 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]645 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]646 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]647 for (unsigned i = 0; i < NumOps; ++i, ++I) {
648 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]649 if (OpInfo[i].isPredicate()) {
650 I = MI.insert(I, MCOperand::CreateImm(CC));
651 ++I;
652 if (CC == ARMCC::AL)
653 MI.insert(I, MCOperand::CreateReg(0));
654 else
655 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]656 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]657 }
658 }
659
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]660 I = MI.insert(I, MCOperand::CreateImm(CC));
661 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]662 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]663 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]664 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]665 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]666
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]667 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]668}
669
670// Thumb VFP instructions are a special case. Because we share their
671// encodings between ARM and Thumb modes, and they are predicable in ARM
672// mode, the auto-generated decoder will give them an (incorrect)
673// predicate operand. We need to rewrite these operands based on the IT
674// context as a post-pass.
675void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
676 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]677 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]678 CC = ITBlock.back();
679 ITBlock.pop_back();
680 } else
681 CC = ARMCC::AL;
682
683 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
684 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]685 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
686 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]687 if (OpInfo[i].isPredicate() ) {
688 I->setImm(CC);
689 ++I;
690 if (CC == ARMCC::AL)
691 I->setReg(0);
692 else
693 I->setReg(ARM::CPSR);
694 return;
695 }
696 }
697}
698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]699DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]700 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]701 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]702 raw_ostream &os,
703 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]704 CommentStream = &cs;
705
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706 uint8_t bytes[4];
707
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]708 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
709 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
710
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]711 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]712 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
713 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]714 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]715 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]716
717 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]718 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]719 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]721 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]722 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]723 }
724
725 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]726 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]727 if (result) {
728 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]729 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]730 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]731 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]732 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]733 }
734
735 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]736 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]737 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]739
740 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
741 // the Thumb predicate.
742 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
743 result = MCDisassembler::SoftFail;
744
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]745 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]746
747 // If we find an IT instruction, we need to parse its condition
748 // code and mask operands so that we can apply them correctly
749 // to the subsequent instructions.
750 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]751
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]752 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]754 unsigned Mask = MI.getOperand(1).getImm();
755 unsigned CondBit0 = Mask >> 4 & 1;
756 unsigned NumTZ = CountTrailingZeros_32(Mask);
757 assert(NumTZ <= 3 && "Invalid IT mask!");
758 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
759 bool T = ((Mask >> Pos) & 1) == CondBit0;
760 if (T)
761 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]763 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]764 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]765
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766 ITBlock.push_back(firstcond);
767 }
768
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]769 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 }
771
772 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]773 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
774 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]775 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]776 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777
778 uint32_t insn32 = (bytes[3] << 8) |
779 (bytes[2] << 0) |
780 (bytes[1] << 24) |
781 (bytes[0] << 16);
782 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]783 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]784 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]785 Size = 4;
786 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]787 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]789 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]790 }
791
792 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]793 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]794 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]795 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]796 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]797 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]798 }
799
800 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]801 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]802 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]803 Size = 4;
804 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]805 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 }
807
808 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]809 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]810 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]811 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]812 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]813 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 }
815
816 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
817 MI.clear();
818 uint32_t NEONLdStInsn = insn32;
819 NEONLdStInsn &= 0xF0FFFFFF;
820 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]821 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]823 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]824 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]825 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]826 }
827 }
828
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]829 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]830 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]831 uint32_t NEONDataInsn = insn32;
832 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
833 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
834 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]835 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]836 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]837 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]838 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]839 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]840 }
841 }
842
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]843 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]844 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]845}
846
847
848extern "C" void LLVMInitializeARMDisassembler() {
849 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
850 createARMDisassembler);
851 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
852 createThumbDisassembler);
853}
854
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]855static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]856 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
857 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
858 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
859 ARM::R12, ARM::SP, ARM::LR, ARM::PC
860};
861
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]862static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]863 uint64_t Address, const void *Decoder) {
864 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]865 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]866
867 unsigned Register = GPRDecoderTable[RegNo];
868 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]869 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]870}
871
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]872static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]873DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]874 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]875 DecodeStatus S = MCDisassembler::Success;
876
877 if (RegNo == 15)
878 S = MCDisassembler::SoftFail;
879
880 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
881
882 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]883}
884
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]885static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]886 uint64_t Address, const void *Decoder) {
887 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]889 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
890}
891
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]892static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]893 uint64_t Address, const void *Decoder) {
894 unsigned Register = 0;
895 switch (RegNo) {
896 case 0:
897 Register = ARM::R0;
898 break;
899 case 1:
900 Register = ARM::R1;
901 break;
902 case 2:
903 Register = ARM::R2;
904 break;
905 case 3:
906 Register = ARM::R3;
907 break;
908 case 9:
909 Register = ARM::R9;
910 break;
911 case 12:
912 Register = ARM::R12;
913 break;
914 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]915 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]916 }
917
918 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]919 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]920}
921
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]922static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]923 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]924 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
926}
927
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]928static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
930 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
931 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
932 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
933 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
934 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
935 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
936 ARM::S28, ARM::S29, ARM::S30, ARM::S31
937};
938
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]939static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]940 uint64_t Address, const void *Decoder) {
941 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]942 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943
944 unsigned Register = SPRDecoderTable[RegNo];
945 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]946 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947}
948
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]949static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
951 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
952 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
953 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
954 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
955 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
956 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
957 ARM::D28, ARM::D29, ARM::D30, ARM::D31
958};
959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]960static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961 uint64_t Address, const void *Decoder) {
962 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]963 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964
965 unsigned Register = DPRDecoderTable[RegNo];
966 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]967 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968}
969
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]970static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]971 uint64_t Address, const void *Decoder) {
972 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]973 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]974 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
975}
976
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]977static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]978DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]979 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]981 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]982 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
983}
984
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]985static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]986 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
987 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
988 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
989 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
990};
991
992
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]993static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]994 uint64_t Address, const void *Decoder) {
995 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]996 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]997 RegNo >>= 1;
998
999 unsigned Register = QPRDecoderTable[RegNo];
1000 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1001 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002}
1003
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1004static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1005 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1006 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1007 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1008 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1009 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1010 ARM::Q15
1011};
1012
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1013static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1014 uint64_t Address, const void *Decoder) {
1015 if (RegNo > 30)
1016 return MCDisassembler::Fail;
1017
1018 unsigned Register = DPairDecoderTable[RegNo];
1019 Inst.addOperand(MCOperand::CreateReg(Register));
1020 return MCDisassembler::Success;
1021}
1022
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1023static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1024 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1025 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1026 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1027 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1028 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1029 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1030 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1031 ARM::D28_D30, ARM::D29_D31
1032};
1033
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1034static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1035 unsigned RegNo,
1036 uint64_t Address,
1037 const void *Decoder) {
1038 if (RegNo > 29)
1039 return MCDisassembler::Fail;
1040
1041 unsigned Register = DPairSpacedDecoderTable[RegNo];
1042 Inst.addOperand(MCOperand::CreateReg(Register));
1043 return MCDisassembler::Success;
1044}
1045
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1046static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1047 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1048 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1049 // AL predicate is not allowed on Thumb1 branches.
1050 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1051 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1052 Inst.addOperand(MCOperand::CreateImm(Val));
1053 if (Val == ARMCC::AL) {
1054 Inst.addOperand(MCOperand::CreateReg(0));
1055 } else
1056 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1057 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1058}
1059
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1060static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1061 uint64_t Address, const void *Decoder) {
1062 if (Val)
1063 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1064 else
1065 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1066 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1067}
1068
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1069static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1070 uint64_t Address, const void *Decoder) {
1071 uint32_t imm = Val & 0xFF;
1072 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1073 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1074 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1075 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1076}
1077
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1078static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1079 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1080 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1081
1082 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1083 unsigned type = fieldFromInstruction32(Val, 5, 2);
1084 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1085
1086 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1088 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1089
1090 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1091 switch (type) {
1092 case 0:
1093 Shift = ARM_AM::lsl;
1094 break;
1095 case 1:
1096 Shift = ARM_AM::lsr;
1097 break;
1098 case 2:
1099 Shift = ARM_AM::asr;
1100 break;
1101 case 3:
1102 Shift = ARM_AM::ror;
1103 break;
1104 }
1105
1106 if (Shift == ARM_AM::ror && imm == 0)
1107 Shift = ARM_AM::rrx;
1108
1109 unsigned Op = Shift | (imm << 3);
1110 Inst.addOperand(MCOperand::CreateImm(Op));
1111
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1112 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113}
1114
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1115static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1116 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1117 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1118
1119 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1120 unsigned type = fieldFromInstruction32(Val, 5, 2);
1121 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1122
1123 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1125 return MCDisassembler::Fail;
1126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1127 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1128
1129 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1130 switch (type) {
1131 case 0:
1132 Shift = ARM_AM::lsl;
1133 break;
1134 case 1:
1135 Shift = ARM_AM::lsr;
1136 break;
1137 case 2:
1138 Shift = ARM_AM::asr;
1139 break;
1140 case 3:
1141 Shift = ARM_AM::ror;
1142 break;
1143 }
1144
1145 Inst.addOperand(MCOperand::CreateImm(Shift));
1146
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1147 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1148}
1149
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1150static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1151 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1152 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1153
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1154 bool writebackLoad = false;
1155 unsigned writebackReg = 0;
1156 switch (Inst.getOpcode()) {
1157 default:
1158 break;
1159 case ARM::LDMIA_UPD:
1160 case ARM::LDMDB_UPD:
1161 case ARM::LDMIB_UPD:
1162 case ARM::LDMDA_UPD:
1163 case ARM::t2LDMIA_UPD:
1164 case ARM::t2LDMDB_UPD:
1165 writebackLoad = true;
1166 writebackReg = Inst.getOperand(0).getReg();
1167 break;
1168 }
1169
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1170 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1171 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1172 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1173 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1174 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1175 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1176 // Writeback not allowed if Rn is in the target list.
1177 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1178 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1179 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180 }
1181
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1182 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183}
1184
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1185static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1187 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1188
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1189 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1190 unsigned regs = Val & 0xFF;
1191
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1192 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1193 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1194 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1195 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1196 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1197 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1198
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1199 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200}
1201
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1202static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1204 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1205
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1206 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1207 unsigned regs = (Val & 0xFF) / 2;
1208
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1209 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1210 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1211 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1212 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1213 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1214 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1215
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1216 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1217}
1218
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1219static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1220 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1221 // This operand encodes a mask of contiguous zeros between a specified MSB
1222 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1223 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1224 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1225 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1226 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1227 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1228
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1229 DecodeStatus S = MCDisassembler::Success;
1230 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1231
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1232 uint32_t msb_mask = 0xFFFFFFFF;
1233 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1234 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1235
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1237 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238}
1239
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1240static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1241 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1242 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1243
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1244 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1245 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1246 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1247 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1248 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1249 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1250
1251 switch (Inst.getOpcode()) {
1252 case ARM::LDC_OFFSET:
1253 case ARM::LDC_PRE:
1254 case ARM::LDC_POST:
1255 case ARM::LDC_OPTION:
1256 case ARM::LDCL_OFFSET:
1257 case ARM::LDCL_PRE:
1258 case ARM::LDCL_POST:
1259 case ARM::LDCL_OPTION:
1260 case ARM::STC_OFFSET:
1261 case ARM::STC_PRE:
1262 case ARM::STC_POST:
1263 case ARM::STC_OPTION:
1264 case ARM::STCL_OFFSET:
1265 case ARM::STCL_PRE:
1266 case ARM::STCL_POST:
1267 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1268 case ARM::t2LDC_OFFSET:
1269 case ARM::t2LDC_PRE:
1270 case ARM::t2LDC_POST:
1271 case ARM::t2LDC_OPTION:
1272 case ARM::t2LDCL_OFFSET:
1273 case ARM::t2LDCL_PRE:
1274 case ARM::t2LDCL_POST:
1275 case ARM::t2LDCL_OPTION:
1276 case ARM::t2STC_OFFSET:
1277 case ARM::t2STC_PRE:
1278 case ARM::t2STC_POST:
1279 case ARM::t2STC_OPTION:
1280 case ARM::t2STCL_OFFSET:
1281 case ARM::t2STCL_PRE:
1282 case ARM::t2STCL_POST:
1283 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1285 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1286 break;
1287 default:
1288 break;
1289 }
1290
1291 Inst.addOperand(MCOperand::CreateImm(coproc));
1292 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1294 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1296 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1297 case ARM::t2LDC2_OFFSET:
1298 case ARM::t2LDC2L_OFFSET:
1299 case ARM::t2LDC2_PRE:
1300 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1301 case ARM::t2STC2_OFFSET:
1302 case ARM::t2STC2L_OFFSET:
1303 case ARM::t2STC2_PRE:
1304 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1305 case ARM::LDC2_OFFSET:
1306 case ARM::LDC2L_OFFSET:
1307 case ARM::LDC2_PRE:
1308 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1309 case ARM::STC2_OFFSET:
1310 case ARM::STC2L_OFFSET:
1311 case ARM::STC2_PRE:
1312 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1313 case ARM::t2LDC_OFFSET:
1314 case ARM::t2LDCL_OFFSET:
1315 case ARM::t2LDC_PRE:
1316 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1317 case ARM::t2STC_OFFSET:
1318 case ARM::t2STCL_OFFSET:
1319 case ARM::t2STC_PRE:
1320 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1321 case ARM::LDC_OFFSET:
1322 case ARM::LDCL_OFFSET:
1323 case ARM::LDC_PRE:
1324 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1325 case ARM::STC_OFFSET:
1326 case ARM::STCL_OFFSET:
1327 case ARM::STC_PRE:
1328 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1329 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1330 Inst.addOperand(MCOperand::CreateImm(imm));
1331 break;
1332 case ARM::t2LDC2_POST:
1333 case ARM::t2LDC2L_POST:
1334 case ARM::t2STC2_POST:
1335 case ARM::t2STC2L_POST:
1336 case ARM::LDC2_POST:
1337 case ARM::LDC2L_POST:
1338 case ARM::STC2_POST:
1339 case ARM::STC2L_POST:
1340 case ARM::t2LDC_POST:
1341 case ARM::t2LDCL_POST:
1342 case ARM::t2STC_POST:
1343 case ARM::t2STCL_POST:
1344 case ARM::LDC_POST:
1345 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1346 case ARM::STC_POST:
1347 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1348 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1349 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1351 // The 'option' variant doesn't encode 'U' in the immediate since
1352 // the immediate is unsigned [0,255].
1353 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1354 break;
1355 }
1356
1357 switch (Inst.getOpcode()) {
1358 case ARM::LDC_OFFSET:
1359 case ARM::LDC_PRE:
1360 case ARM::LDC_POST:
1361 case ARM::LDC_OPTION:
1362 case ARM::LDCL_OFFSET:
1363 case ARM::LDCL_PRE:
1364 case ARM::LDCL_POST:
1365 case ARM::LDCL_OPTION:
1366 case ARM::STC_OFFSET:
1367 case ARM::STC_PRE:
1368 case ARM::STC_POST:
1369 case ARM::STC_OPTION:
1370 case ARM::STCL_OFFSET:
1371 case ARM::STCL_PRE:
1372 case ARM::STCL_POST:
1373 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1374 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1375 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1376 break;
1377 default:
1378 break;
1379 }
1380
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1381 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1382}
1383
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1384static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1385DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1386 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1387 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1388
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1389 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1390 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1392 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1393 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1394 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1395 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1396 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1397
1398 // On stores, the writeback operand precedes Rt.
1399 switch (Inst.getOpcode()) {
1400 case ARM::STR_POST_IMM:
1401 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1402 case ARM::STRB_POST_IMM:
1403 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1404 case ARM::STRT_POST_REG:
1405 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1406 case ARM::STRBT_POST_REG:
1407 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1409 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1410 break;
1411 default:
1412 break;
1413 }
1414
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1416 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1417
1418 // On loads, the writeback operand comes after Rt.
1419 switch (Inst.getOpcode()) {
1420 case ARM::LDR_POST_IMM:
1421 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1422 case ARM::LDRB_POST_IMM:
1423 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1424 case ARM::LDRBT_POST_REG:
1425 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1426 case ARM::LDRT_POST_REG:
1427 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1429 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1430 break;
1431 default:
1432 break;
1433 }
1434
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1436 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1437
1438 ARM_AM::AddrOpc Op = ARM_AM::add;
1439 if (!fieldFromInstruction32(Insn, 23, 1))
1440 Op = ARM_AM::sub;
1441
1442 bool writeback = (P == 0) || (W == 1);
1443 unsigned idx_mode = 0;
1444 if (P && writeback)
1445 idx_mode = ARMII::IndexModePre;
1446 else if (!P && writeback)
1447 idx_mode = ARMII::IndexModePost;
1448
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1449 if (writeback && (Rn == 15 || Rn == Rt))
1450 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1451
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1452 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1454 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1455 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1456 switch( fieldFromInstruction32(Insn, 5, 2)) {
1457 case 0:
1458 Opc = ARM_AM::lsl;
1459 break;
1460 case 1:
1461 Opc = ARM_AM::lsr;
1462 break;
1463 case 2:
1464 Opc = ARM_AM::asr;
1465 break;
1466 case 3:
1467 Opc = ARM_AM::ror;
1468 break;
1469 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1470 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471 }
1472 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1473 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1474
1475 Inst.addOperand(MCOperand::CreateImm(imm));
1476 } else {
1477 Inst.addOperand(MCOperand::CreateReg(0));
1478 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1479 Inst.addOperand(MCOperand::CreateImm(tmp));
1480 }
1481
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1482 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1483 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1485 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1486}
1487
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1488static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1489 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1490 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1491
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1492 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1493 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1494 unsigned type = fieldFromInstruction32(Val, 5, 2);
1495 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1496 unsigned U = fieldFromInstruction32(Val, 12, 1);
1497
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1498 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1499 switch (type) {
1500 case 0:
1501 ShOp = ARM_AM::lsl;
1502 break;
1503 case 1:
1504 ShOp = ARM_AM::lsr;
1505 break;
1506 case 2:
1507 ShOp = ARM_AM::asr;
1508 break;
1509 case 3:
1510 ShOp = ARM_AM::ror;
1511 break;
1512 }
1513
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515 return MCDisassembler::Fail;
1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1517 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1518 unsigned shift;
1519 if (U)
1520 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1521 else
1522 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1523 Inst.addOperand(MCOperand::CreateImm(shift));
1524
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1525 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1526}
1527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1528static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1529DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1530 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1531 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1532
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1533 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1536 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1537 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1538 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1539 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1540 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1541 unsigned P = fieldFromInstruction32(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1542 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1543
1544 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1545
1546 // For {LD,ST}RD, Rt must be even, else undefined.
1547 switch (Inst.getOpcode()) {
1548 case ARM::STRD:
1549 case ARM::STRD_PRE:
1550 case ARM::STRD_POST:
1551 case ARM::LDRD:
1552 case ARM::LDRD_PRE:
1553 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1554 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1555 break;
1556 default:
1557 break;
1558 }
1559 switch (Inst.getOpcode()) {
1560 case ARM::STRD:
1561 case ARM::STRD_PRE:
1562 case ARM::STRD_POST:
1563 if (P == 0 && W == 1)
1564 S = MCDisassembler::SoftFail;
1565
1566 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1567 S = MCDisassembler::SoftFail;
1568 if (type && Rm == 15)
1569 S = MCDisassembler::SoftFail;
1570 if (Rt2 == 15)
1571 S = MCDisassembler::SoftFail;
1572 if (!type && fieldFromInstruction32(Insn, 8, 4))
1573 S = MCDisassembler::SoftFail;
1574 break;
1575 case ARM::STRH:
1576 case ARM::STRH_PRE:
1577 case ARM::STRH_POST:
1578 if (Rt == 15)
1579 S = MCDisassembler::SoftFail;
1580 if (writeback && (Rn == 15 || Rn == Rt))
1581 S = MCDisassembler::SoftFail;
1582 if (!type && Rm == 15)
1583 S = MCDisassembler::SoftFail;
1584 break;
1585 case ARM::LDRD:
1586 case ARM::LDRD_PRE:
1587 case ARM::LDRD_POST:
1588 if (type && Rn == 15){
1589 if (Rt2 == 15)
1590 S = MCDisassembler::SoftFail;
1591 break;
1592 }
1593 if (P == 0 && W == 1)
1594 S = MCDisassembler::SoftFail;
1595 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1596 S = MCDisassembler::SoftFail;
1597 if (!type && writeback && Rn == 15)
1598 S = MCDisassembler::SoftFail;
1599 if (writeback && (Rn == Rt || Rn == Rt2))
1600 S = MCDisassembler::SoftFail;
1601 break;
1602 case ARM::LDRH:
1603 case ARM::LDRH_PRE:
1604 case ARM::LDRH_POST:
1605 if (type && Rn == 15){
1606 if (Rt == 15)
1607 S = MCDisassembler::SoftFail;
1608 break;
1609 }
1610 if (Rt == 15)
1611 S = MCDisassembler::SoftFail;
1612 if (!type && Rm == 15)
1613 S = MCDisassembler::SoftFail;
1614 if (!type && writeback && (Rn == 15 || Rn == Rt))
1615 S = MCDisassembler::SoftFail;
1616 break;
1617 case ARM::LDRSH:
1618 case ARM::LDRSH_PRE:
1619 case ARM::LDRSH_POST:
1620 case ARM::LDRSB:
1621 case ARM::LDRSB_PRE:
1622 case ARM::LDRSB_POST:
1623 if (type && Rn == 15){
1624 if (Rt == 15)
1625 S = MCDisassembler::SoftFail;
1626 break;
1627 }
1628 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1629 S = MCDisassembler::SoftFail;
1630 if (!type && (Rt == 15 || Rm == 15))
1631 S = MCDisassembler::SoftFail;
1632 if (!type && writeback && (Rn == 15 || Rn == Rt))
1633 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1634 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1635 default:
1636 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1637 }
1638
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1639 if (writeback) { // Writeback
1640 if (P)
1641 U |= ARMII::IndexModePre << 9;
1642 else
1643 U |= ARMII::IndexModePost << 9;
1644
1645 // On stores, the writeback operand precedes Rt.
1646 switch (Inst.getOpcode()) {
1647 case ARM::STRD:
1648 case ARM::STRD_PRE:
1649 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1650 case ARM::STRH:
1651 case ARM::STRH_PRE:
1652 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1654 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1655 break;
1656 default:
1657 break;
1658 }
1659 }
1660
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1662 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1663 switch (Inst.getOpcode()) {
1664 case ARM::STRD:
1665 case ARM::STRD_PRE:
1666 case ARM::STRD_POST:
1667 case ARM::LDRD:
1668 case ARM::LDRD_PRE:
1669 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1671 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1672 break;
1673 default:
1674 break;
1675 }
1676
1677 if (writeback) {
1678 // On loads, the writeback operand comes after Rt.
1679 switch (Inst.getOpcode()) {
1680 case ARM::LDRD:
1681 case ARM::LDRD_PRE:
1682 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1683 case ARM::LDRH:
1684 case ARM::LDRH_PRE:
1685 case ARM::LDRH_POST:
1686 case ARM::LDRSH:
1687 case ARM::LDRSH_PRE:
1688 case ARM::LDRSH_POST:
1689 case ARM::LDRSB:
1690 case ARM::LDRSB_PRE:
1691 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1692 case ARM::LDRHTr:
1693 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1695 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1696 break;
1697 default:
1698 break;
1699 }
1700 }
1701
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1703 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1704
1705 if (type) {
1706 Inst.addOperand(MCOperand::CreateReg(0));
1707 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1708 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1710 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1711 Inst.addOperand(MCOperand::CreateImm(U));
1712 }
1713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1715 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1717 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718}
1719
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1720static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1722 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1723
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1725 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1726
1727 switch (mode) {
1728 case 0:
1729 mode = ARM_AM::da;
1730 break;
1731 case 1:
1732 mode = ARM_AM::ia;
1733 break;
1734 case 2:
1735 mode = ARM_AM::db;
1736 break;
1737 case 3:
1738 mode = ARM_AM::ib;
1739 break;
1740 }
1741
1742 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1744 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1745
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1746 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1747}
1748
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1749static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1750 unsigned Insn,
1751 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1752 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1753
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1754 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1755 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1756 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1757
1758 if (pred == 0xF) {
1759 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1760 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1761 Inst.setOpcode(ARM::RFEDA);
1762 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1763 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1764 Inst.setOpcode(ARM::RFEDA_UPD);
1765 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1766 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1767 Inst.setOpcode(ARM::RFEDB);
1768 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1769 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1770 Inst.setOpcode(ARM::RFEDB_UPD);
1771 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1772 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1773 Inst.setOpcode(ARM::RFEIA);
1774 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1775 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1776 Inst.setOpcode(ARM::RFEIA_UPD);
1777 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1778 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1779 Inst.setOpcode(ARM::RFEIB);
1780 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1781 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1782 Inst.setOpcode(ARM::RFEIB_UPD);
1783 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1784 case ARM::STMDA:
1785 Inst.setOpcode(ARM::SRSDA);
1786 break;
1787 case ARM::STMDA_UPD:
1788 Inst.setOpcode(ARM::SRSDA_UPD);
1789 break;
1790 case ARM::STMDB:
1791 Inst.setOpcode(ARM::SRSDB);
1792 break;
1793 case ARM::STMDB_UPD:
1794 Inst.setOpcode(ARM::SRSDB_UPD);
1795 break;
1796 case ARM::STMIA:
1797 Inst.setOpcode(ARM::SRSIA);
1798 break;
1799 case ARM::STMIA_UPD:
1800 Inst.setOpcode(ARM::SRSIA_UPD);
1801 break;
1802 case ARM::STMIB:
1803 Inst.setOpcode(ARM::SRSIB);
1804 break;
1805 case ARM::STMIB_UPD:
1806 Inst.setOpcode(ARM::SRSIB_UPD);
1807 break;
1808 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1809 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1810 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1811
1812 // For stores (which become SRS's, the only operand is the mode.
1813 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1814 Inst.addOperand(
1815 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1816 return S;
1817 }
1818
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1819 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1820 }
1821
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1823 return MCDisassembler::Fail;
1824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1825 return MCDisassembler::Fail; // Tied
1826 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1827 return MCDisassembler::Fail;
1828 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1829 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1831 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832}
1833
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1834static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 uint64_t Address, const void *Decoder) {
1836 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1837 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1838 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1839 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1840
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1841 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1842
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1843 // imod == '01' --> UNPREDICTABLE
1844 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1845 // return failure here. The '01' imod value is unprintable, so there's
1846 // nothing useful we could do even if we returned UNPREDICTABLE.
1847
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1848 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1849
1850 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1851 Inst.setOpcode(ARM::CPS3p);
1852 Inst.addOperand(MCOperand::CreateImm(imod));
1853 Inst.addOperand(MCOperand::CreateImm(iflags));
1854 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1855 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1856 Inst.setOpcode(ARM::CPS2p);
1857 Inst.addOperand(MCOperand::CreateImm(imod));
1858 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1859 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1860 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861 Inst.setOpcode(ARM::CPS1p);
1862 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1863 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1864 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1865 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1866 Inst.setOpcode(ARM::CPS1p);
1867 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1868 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1869 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1871 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1872}
1873
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1874static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1875 uint64_t Address, const void *Decoder) {
1876 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1877 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1878 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1879 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1882
1883 // imod == '01' --> UNPREDICTABLE
1884 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1885 // return failure here. The '01' imod value is unprintable, so there's
1886 // nothing useful we could do even if we returned UNPREDICTABLE.
1887
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1888 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1889
1890 if (imod && M) {
1891 Inst.setOpcode(ARM::t2CPS3p);
1892 Inst.addOperand(MCOperand::CreateImm(imod));
1893 Inst.addOperand(MCOperand::CreateImm(iflags));
1894 Inst.addOperand(MCOperand::CreateImm(mode));
1895 } else if (imod && !M) {
1896 Inst.setOpcode(ARM::t2CPS2p);
1897 Inst.addOperand(MCOperand::CreateImm(imod));
1898 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1899 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1900 } else if (!imod && M) {
1901 Inst.setOpcode(ARM::t2CPS1p);
1902 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1903 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1904 } else {
1905 // imod == '00' && M == '0' --> UNPREDICTABLE
1906 Inst.setOpcode(ARM::t2CPS1p);
1907 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1908 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1909 }
1910
1911 return S;
1912}
1913
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1914static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1915 uint64_t Address, const void *Decoder) {
1916 DecodeStatus S = MCDisassembler::Success;
1917
1918 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1919 unsigned imm = 0;
1920
1921 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1922 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1923 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1924 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1925
1926 if (Inst.getOpcode() == ARM::t2MOVTi16)
1927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1928 return MCDisassembler::Fail;
1929 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1930 return MCDisassembler::Fail;
1931
1932 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1933 Inst.addOperand(MCOperand::CreateImm(imm));
1934
1935 return S;
1936}
1937
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1938static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1939 uint64_t Address, const void *Decoder) {
1940 DecodeStatus S = MCDisassembler::Success;
1941
1942 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1943 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1944 unsigned imm = 0;
1945
1946 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1947 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1948
1949 if (Inst.getOpcode() == ARM::MOVTi16)
1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1951 return MCDisassembler::Fail;
1952 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1953 return MCDisassembler::Fail;
1954
1955 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1956 Inst.addOperand(MCOperand::CreateImm(imm));
1957
1958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1959 return MCDisassembler::Fail;
1960
1961 return S;
1962}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1963
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1964static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1965 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1966 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1967
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1968 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1969 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1970 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1971 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1972 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1973
1974 if (pred == 0xF)
1975 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1976
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1978 return MCDisassembler::Fail;
1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1980 return MCDisassembler::Fail;
1981 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1982 return MCDisassembler::Fail;
1983 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1984 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1986 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1987 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1988
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1989 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1990}
1991
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1992static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1993 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1994 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1995
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1996 unsigned add = fieldFromInstruction32(Val, 12, 1);
1997 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1998 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2001 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2002
2003 if (!add) imm *= -1;
2004 if (imm == 0 && !add) imm = INT32_MIN;
2005 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2006 if (Rn == 15)
2007 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2008
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2009 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2010}
2011
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2012static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2013 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2014 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2015
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2016 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2017 unsigned U = fieldFromInstruction32(Val, 8, 1);
2018 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2019
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2021 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2022
2023 if (U)
2024 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2025 else
2026 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2027
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2028 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2029}
2030
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2031static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2032 uint64_t Address, const void *Decoder) {
2033 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2034}
2035
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2036static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2037DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2038 uint64_t Address, const void *Decoder) {
2039 DecodeStatus S = MCDisassembler::Success;
2040 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2041 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2042 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2043 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2044 (fieldFromInstruction32(Insn, 26, 1) << 19);
2045 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2046 true, 4, Inst, Decoder))
2047 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2048 return S;
2049}
2050
2051static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2052DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2053 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2054 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2055
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2057 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2058
2059 if (pred == 0xF) {
2060 Inst.setOpcode(ARM::BLXi);
2061 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2062 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2063 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2064 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2065 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2066 }
2067
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2068 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2069 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2070 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2071 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2072 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2073
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2074 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2075}
2076
2077
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2078static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2079 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2080 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2081
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2082 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2083 unsigned align = fieldFromInstruction32(Val, 4, 2);
2084
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2086 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2087 if (!align)
2088 Inst.addOperand(MCOperand::CreateImm(0));
2089 else
2090 Inst.addOperand(MCOperand::CreateImm(4 << align));
2091
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2092 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2093}
2094
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2095static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2096 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2097 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2098
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2099 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2100 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2101 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2103 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2104 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2105
2106 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2107 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2108 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2109 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2110 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2111 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2112 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2113 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2114 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2115 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2116 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2117 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2118 return MCDisassembler::Fail;
2119 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2120 case ARM::VLD2b16:
2121 case ARM::VLD2b32:
2122 case ARM::VLD2b8:
2123 case ARM::VLD2b16wb_fixed:
2124 case ARM::VLD2b16wb_register:
2125 case ARM::VLD2b32wb_fixed:
2126 case ARM::VLD2b32wb_register:
2127 case ARM::VLD2b8wb_fixed:
2128 case ARM::VLD2b8wb_register:
2129 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2130 return MCDisassembler::Fail;
2131 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2132 default:
2133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2134 return MCDisassembler::Fail;
2135 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2136
2137 // Second output register
2138 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2139 case ARM::VLD3d8:
2140 case ARM::VLD3d16:
2141 case ARM::VLD3d32:
2142 case ARM::VLD3d8_UPD:
2143 case ARM::VLD3d16_UPD:
2144 case ARM::VLD3d32_UPD:
2145 case ARM::VLD4d8:
2146 case ARM::VLD4d16:
2147 case ARM::VLD4d32:
2148 case ARM::VLD4d8_UPD:
2149 case ARM::VLD4d16_UPD:
2150 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2151 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2152 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2153 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2154 case ARM::VLD3q8:
2155 case ARM::VLD3q16:
2156 case ARM::VLD3q32:
2157 case ARM::VLD3q8_UPD:
2158 case ARM::VLD3q16_UPD:
2159 case ARM::VLD3q32_UPD:
2160 case ARM::VLD4q8:
2161 case ARM::VLD4q16:
2162 case ARM::VLD4q32:
2163 case ARM::VLD4q8_UPD:
2164 case ARM::VLD4q16_UPD:
2165 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2166 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2167 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2168 default:
2169 break;
2170 }
2171
2172 // Third output register
2173 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2174 case ARM::VLD3d8:
2175 case ARM::VLD3d16:
2176 case ARM::VLD3d32:
2177 case ARM::VLD3d8_UPD:
2178 case ARM::VLD3d16_UPD:
2179 case ARM::VLD3d32_UPD:
2180 case ARM::VLD4d8:
2181 case ARM::VLD4d16:
2182 case ARM::VLD4d32:
2183 case ARM::VLD4d8_UPD:
2184 case ARM::VLD4d16_UPD:
2185 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2186 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2187 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2188 break;
2189 case ARM::VLD3q8:
2190 case ARM::VLD3q16:
2191 case ARM::VLD3q32:
2192 case ARM::VLD3q8_UPD:
2193 case ARM::VLD3q16_UPD:
2194 case ARM::VLD3q32_UPD:
2195 case ARM::VLD4q8:
2196 case ARM::VLD4q16:
2197 case ARM::VLD4q32:
2198 case ARM::VLD4q8_UPD:
2199 case ARM::VLD4q16_UPD:
2200 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2201 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2202 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2203 break;
2204 default:
2205 break;
2206 }
2207
2208 // Fourth output register
2209 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2210 case ARM::VLD4d8:
2211 case ARM::VLD4d16:
2212 case ARM::VLD4d32:
2213 case ARM::VLD4d8_UPD:
2214 case ARM::VLD4d16_UPD:
2215 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2216 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2217 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2218 break;
2219 case ARM::VLD4q8:
2220 case ARM::VLD4q16:
2221 case ARM::VLD4q32:
2222 case ARM::VLD4q8_UPD:
2223 case ARM::VLD4q16_UPD:
2224 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2225 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2226 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2227 break;
2228 default:
2229 break;
2230 }
2231
2232 // Writeback operand
2233 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2234 case ARM::VLD1d8wb_fixed:
2235 case ARM::VLD1d16wb_fixed:
2236 case ARM::VLD1d32wb_fixed:
2237 case ARM::VLD1d64wb_fixed:
2238 case ARM::VLD1d8wb_register:
2239 case ARM::VLD1d16wb_register:
2240 case ARM::VLD1d32wb_register:
2241 case ARM::VLD1d64wb_register:
2242 case ARM::VLD1q8wb_fixed:
2243 case ARM::VLD1q16wb_fixed:
2244 case ARM::VLD1q32wb_fixed:
2245 case ARM::VLD1q64wb_fixed:
2246 case ARM::VLD1q8wb_register:
2247 case ARM::VLD1q16wb_register:
2248 case ARM::VLD1q32wb_register:
2249 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2250 case ARM::VLD1d8Twb_fixed:
2251 case ARM::VLD1d8Twb_register:
2252 case ARM::VLD1d16Twb_fixed:
2253 case ARM::VLD1d16Twb_register:
2254 case ARM::VLD1d32Twb_fixed:
2255 case ARM::VLD1d32Twb_register:
2256 case ARM::VLD1d64Twb_fixed:
2257 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2258 case ARM::VLD1d8Qwb_fixed:
2259 case ARM::VLD1d8Qwb_register:
2260 case ARM::VLD1d16Qwb_fixed:
2261 case ARM::VLD1d16Qwb_register:
2262 case ARM::VLD1d32Qwb_fixed:
2263 case ARM::VLD1d32Qwb_register:
2264 case ARM::VLD1d64Qwb_fixed:
2265 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2266 case ARM::VLD2d8wb_fixed:
2267 case ARM::VLD2d16wb_fixed:
2268 case ARM::VLD2d32wb_fixed:
2269 case ARM::VLD2q8wb_fixed:
2270 case ARM::VLD2q16wb_fixed:
2271 case ARM::VLD2q32wb_fixed:
2272 case ARM::VLD2d8wb_register:
2273 case ARM::VLD2d16wb_register:
2274 case ARM::VLD2d32wb_register:
2275 case ARM::VLD2q8wb_register:
2276 case ARM::VLD2q16wb_register:
2277 case ARM::VLD2q32wb_register:
2278 case ARM::VLD2b8wb_fixed:
2279 case ARM::VLD2b16wb_fixed:
2280 case ARM::VLD2b32wb_fixed:
2281 case ARM::VLD2b8wb_register:
2282 case ARM::VLD2b16wb_register:
2283 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2284 Inst.addOperand(MCOperand::CreateImm(0));
2285 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2286 case ARM::VLD3d8_UPD:
2287 case ARM::VLD3d16_UPD:
2288 case ARM::VLD3d32_UPD:
2289 case ARM::VLD3q8_UPD:
2290 case ARM::VLD3q16_UPD:
2291 case ARM::VLD3q32_UPD:
2292 case ARM::VLD4d8_UPD:
2293 case ARM::VLD4d16_UPD:
2294 case ARM::VLD4d32_UPD:
2295 case ARM::VLD4q8_UPD:
2296 case ARM::VLD4q16_UPD:
2297 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2298 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2299 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2300 break;
2301 default:
2302 break;
2303 }
2304
2305 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2306 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2307 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2308
2309 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2310 switch (Inst.getOpcode()) {
2311 default:
2312 // The below have been updated to have explicit am6offset split
2313 // between fixed and register offset. For those instructions not
2314 // yet updated, we need to add an additional reg0 operand for the
2315 // fixed variant.
2316 //
2317 // The fixed offset encodes as Rm == 0xd, so we check for that.
2318 if (Rm == 0xd) {
2319 Inst.addOperand(MCOperand::CreateReg(0));
2320 break;
2321 }
2322 // Fall through to handle the register offset variant.
2323 case ARM::VLD1d8wb_fixed:
2324 case ARM::VLD1d16wb_fixed:
2325 case ARM::VLD1d32wb_fixed:
2326 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2327 case ARM::VLD1d8Twb_fixed:
2328 case ARM::VLD1d16Twb_fixed:
2329 case ARM::VLD1d32Twb_fixed:
2330 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2331 case ARM::VLD1d8Qwb_fixed:
2332 case ARM::VLD1d16Qwb_fixed:
2333 case ARM::VLD1d32Qwb_fixed:
2334 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2335 case ARM::VLD1d8wb_register:
2336 case ARM::VLD1d16wb_register:
2337 case ARM::VLD1d32wb_register:
2338 case ARM::VLD1d64wb_register:
2339 case ARM::VLD1q8wb_fixed:
2340 case ARM::VLD1q16wb_fixed:
2341 case ARM::VLD1q32wb_fixed:
2342 case ARM::VLD1q64wb_fixed:
2343 case ARM::VLD1q8wb_register:
2344 case ARM::VLD1q16wb_register:
2345 case ARM::VLD1q32wb_register:
2346 case ARM::VLD1q64wb_register:
2347 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2348 // variant encodes Rm == 0xf. Anything else is a register offset post-
2349 // increment and we need to add the register operand to the instruction.
2350 if (Rm != 0xD && Rm != 0xF &&
2351 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2352 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2353 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2354 case ARM::VLD2d8wb_fixed:
2355 case ARM::VLD2d16wb_fixed:
2356 case ARM::VLD2d32wb_fixed:
2357 case ARM::VLD2b8wb_fixed:
2358 case ARM::VLD2b16wb_fixed:
2359 case ARM::VLD2b32wb_fixed:
2360 case ARM::VLD2q8wb_fixed:
2361 case ARM::VLD2q16wb_fixed:
2362 case ARM::VLD2q32wb_fixed:
2363 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2364 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2365
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2366 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2367}
2368
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2369static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2370 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2371 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2372
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2373 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2374 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2375 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2377 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2378 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2379
2380 // Writeback Operand
2381 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2382 case ARM::VST1d8wb_fixed:
2383 case ARM::VST1d16wb_fixed:
2384 case ARM::VST1d32wb_fixed:
2385 case ARM::VST1d64wb_fixed:
2386 case ARM::VST1d8wb_register:
2387 case ARM::VST1d16wb_register:
2388 case ARM::VST1d32wb_register:
2389 case ARM::VST1d64wb_register:
2390 case ARM::VST1q8wb_fixed:
2391 case ARM::VST1q16wb_fixed:
2392 case ARM::VST1q32wb_fixed:
2393 case ARM::VST1q64wb_fixed:
2394 case ARM::VST1q8wb_register:
2395 case ARM::VST1q16wb_register:
2396 case ARM::VST1q32wb_register:
2397 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2398 case ARM::VST1d8Twb_fixed:
2399 case ARM::VST1d16Twb_fixed:
2400 case ARM::VST1d32Twb_fixed:
2401 case ARM::VST1d64Twb_fixed:
2402 case ARM::VST1d8Twb_register:
2403 case ARM::VST1d16Twb_register:
2404 case ARM::VST1d32Twb_register:
2405 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2406 case ARM::VST1d8Qwb_fixed:
2407 case ARM::VST1d16Qwb_fixed:
2408 case ARM::VST1d32Qwb_fixed:
2409 case ARM::VST1d64Qwb_fixed:
2410 case ARM::VST1d8Qwb_register:
2411 case ARM::VST1d16Qwb_register:
2412 case ARM::VST1d32Qwb_register:
2413 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2414 case ARM::VST2d8wb_fixed:
2415 case ARM::VST2d16wb_fixed:
2416 case ARM::VST2d32wb_fixed:
2417 case ARM::VST2d8wb_register:
2418 case ARM::VST2d16wb_register:
2419 case ARM::VST2d32wb_register:
2420 case ARM::VST2q8wb_fixed:
2421 case ARM::VST2q16wb_fixed:
2422 case ARM::VST2q32wb_fixed:
2423 case ARM::VST2q8wb_register:
2424 case ARM::VST2q16wb_register:
2425 case ARM::VST2q32wb_register:
2426 case ARM::VST2b8wb_fixed:
2427 case ARM::VST2b16wb_fixed:
2428 case ARM::VST2b32wb_fixed:
2429 case ARM::VST2b8wb_register:
2430 case ARM::VST2b16wb_register:
2431 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2432 if (Rm == 0xF)
2433 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2434 Inst.addOperand(MCOperand::CreateImm(0));
2435 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436 case ARM::VST3d8_UPD:
2437 case ARM::VST3d16_UPD:
2438 case ARM::VST3d32_UPD:
2439 case ARM::VST3q8_UPD:
2440 case ARM::VST3q16_UPD:
2441 case ARM::VST3q32_UPD:
2442 case ARM::VST4d8_UPD:
2443 case ARM::VST4d16_UPD:
2444 case ARM::VST4d32_UPD:
2445 case ARM::VST4q8_UPD:
2446 case ARM::VST4q16_UPD:
2447 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2448 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2449 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450 break;
2451 default:
2452 break;
2453 }
2454
2455 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2456 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2457 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2458
2459 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2460 switch (Inst.getOpcode()) {
2461 default:
2462 if (Rm == 0xD)
2463 Inst.addOperand(MCOperand::CreateReg(0));
2464 else if (Rm != 0xF) {
2465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2466 return MCDisassembler::Fail;
2467 }
2468 break;
2469 case ARM::VST1d8wb_fixed:
2470 case ARM::VST1d16wb_fixed:
2471 case ARM::VST1d32wb_fixed:
2472 case ARM::VST1d64wb_fixed:
2473 case ARM::VST1q8wb_fixed:
2474 case ARM::VST1q16wb_fixed:
2475 case ARM::VST1q32wb_fixed:
2476 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2477 case ARM::VST1d8Twb_fixed:
2478 case ARM::VST1d16Twb_fixed:
2479 case ARM::VST1d32Twb_fixed:
2480 case ARM::VST1d64Twb_fixed:
2481 case ARM::VST1d8Qwb_fixed:
2482 case ARM::VST1d16Qwb_fixed:
2483 case ARM::VST1d32Qwb_fixed:
2484 case ARM::VST1d64Qwb_fixed:
2485 case ARM::VST2d8wb_fixed:
2486 case ARM::VST2d16wb_fixed:
2487 case ARM::VST2d32wb_fixed:
2488 case ARM::VST2q8wb_fixed:
2489 case ARM::VST2q16wb_fixed:
2490 case ARM::VST2q32wb_fixed:
2491 case ARM::VST2b8wb_fixed:
2492 case ARM::VST2b16wb_fixed:
2493 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2494 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2495 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2497
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2498 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2499 switch (Inst.getOpcode()) {
2500 case ARM::VST1q16:
2501 case ARM::VST1q32:
2502 case ARM::VST1q64:
2503 case ARM::VST1q8:
2504 case ARM::VST1q16wb_fixed:
2505 case ARM::VST1q16wb_register:
2506 case ARM::VST1q32wb_fixed:
2507 case ARM::VST1q32wb_register:
2508 case ARM::VST1q64wb_fixed:
2509 case ARM::VST1q64wb_register:
2510 case ARM::VST1q8wb_fixed:
2511 case ARM::VST1q8wb_register:
2512 case ARM::VST2d16:
2513 case ARM::VST2d32:
2514 case ARM::VST2d8:
2515 case ARM::VST2d16wb_fixed:
2516 case ARM::VST2d16wb_register:
2517 case ARM::VST2d32wb_fixed:
2518 case ARM::VST2d32wb_register:
2519 case ARM::VST2d8wb_fixed:
2520 case ARM::VST2d8wb_register:
2521 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2522 return MCDisassembler::Fail;
2523 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2524 case ARM::VST2b16:
2525 case ARM::VST2b32:
2526 case ARM::VST2b8:
2527 case ARM::VST2b16wb_fixed:
2528 case ARM::VST2b16wb_register:
2529 case ARM::VST2b32wb_fixed:
2530 case ARM::VST2b32wb_register:
2531 case ARM::VST2b8wb_fixed:
2532 case ARM::VST2b8wb_register:
2533 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2534 return MCDisassembler::Fail;
2535 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2536 default:
2537 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2538 return MCDisassembler::Fail;
2539 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2540
2541 // Second input register
2542 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2543 case ARM::VST3d8:
2544 case ARM::VST3d16:
2545 case ARM::VST3d32:
2546 case ARM::VST3d8_UPD:
2547 case ARM::VST3d16_UPD:
2548 case ARM::VST3d32_UPD:
2549 case ARM::VST4d8:
2550 case ARM::VST4d16:
2551 case ARM::VST4d32:
2552 case ARM::VST4d8_UPD:
2553 case ARM::VST4d16_UPD:
2554 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2555 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2556 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558 case ARM::VST3q8:
2559 case ARM::VST3q16:
2560 case ARM::VST3q32:
2561 case ARM::VST3q8_UPD:
2562 case ARM::VST3q16_UPD:
2563 case ARM::VST3q32_UPD:
2564 case ARM::VST4q8:
2565 case ARM::VST4q16:
2566 case ARM::VST4q32:
2567 case ARM::VST4q8_UPD:
2568 case ARM::VST4q16_UPD:
2569 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2570 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2571 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2572 break;
2573 default:
2574 break;
2575 }
2576
2577 // Third input register
2578 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2579 case ARM::VST3d8:
2580 case ARM::VST3d16:
2581 case ARM::VST3d32:
2582 case ARM::VST3d8_UPD:
2583 case ARM::VST3d16_UPD:
2584 case ARM::VST3d32_UPD:
2585 case ARM::VST4d8:
2586 case ARM::VST4d16:
2587 case ARM::VST4d32:
2588 case ARM::VST4d8_UPD:
2589 case ARM::VST4d16_UPD:
2590 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2591 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2592 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2593 break;
2594 case ARM::VST3q8:
2595 case ARM::VST3q16:
2596 case ARM::VST3q32:
2597 case ARM::VST3q8_UPD:
2598 case ARM::VST3q16_UPD:
2599 case ARM::VST3q32_UPD:
2600 case ARM::VST4q8:
2601 case ARM::VST4q16:
2602 case ARM::VST4q32:
2603 case ARM::VST4q8_UPD:
2604 case ARM::VST4q16_UPD:
2605 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2606 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2607 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608 break;
2609 default:
2610 break;
2611 }
2612
2613 // Fourth input register
2614 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2615 case ARM::VST4d8:
2616 case ARM::VST4d16:
2617 case ARM::VST4d32:
2618 case ARM::VST4d8_UPD:
2619 case ARM::VST4d16_UPD:
2620 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2621 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2622 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2623 break;
2624 case ARM::VST4q8:
2625 case ARM::VST4q16:
2626 case ARM::VST4q32:
2627 case ARM::VST4q8_UPD:
2628 case ARM::VST4q16_UPD:
2629 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2630 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2631 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2632 break;
2633 default:
2634 break;
2635 }
2636
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2637 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638}
2639
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2640static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2642 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2643
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2644 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2645 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2646 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2647 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2648 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2649 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650
2651 align *= (1 << size);
2652
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2653 switch (Inst.getOpcode()) {
2654 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2655 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2656 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2657 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2658 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2659 return MCDisassembler::Fail;
2660 break;
2661 default:
2662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2663 return MCDisassembler::Fail;
2664 break;
2665 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2666 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2668 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2669 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2672 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673 Inst.addOperand(MCOperand::CreateImm(align));
2674
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2675 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2676 // variant encodes Rm == 0xf. Anything else is a register offset post-
2677 // increment and we need to add the register operand to the instruction.
2678 if (Rm != 0xD && Rm != 0xF &&
2679 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2680 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2682 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2683}
2684
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2685static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2686 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2687 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2688
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2689 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2690 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2692 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2693 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2694 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2695 align *= 2*size;
2696
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2697 switch (Inst.getOpcode()) {
2698 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2699 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2700 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2701 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2702 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2703 return MCDisassembler::Fail;
2704 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2705 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2706 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2707 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2708 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2709 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2710 return MCDisassembler::Fail;
2711 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2712 default:
2713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2714 return MCDisassembler::Fail;
2715 break;
2716 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2717
2718 if (Rm != 0xF)
2719 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2722 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2723 Inst.addOperand(MCOperand::CreateImm(align));
2724
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2725 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2727 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2728 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2730 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2731}
2732
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2733static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2735 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2736
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2737 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2738 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2739 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2741 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2742
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2744 return MCDisassembler::Fail;
2745 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2746 return MCDisassembler::Fail;
2747 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2748 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2749 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2751 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2752 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2753
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2755 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756 Inst.addOperand(MCOperand::CreateImm(0));
2757
2758 if (Rm == 0xD)
2759 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2760 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2762 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2763 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2765 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2766}
2767
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2768static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2770 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2771
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2772 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2773 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2774 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2775 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2776 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2777 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2778 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2779
2780 if (size == 0x3) {
2781 size = 4;
2782 align = 16;
2783 } else {
2784 if (size == 2) {
2785 size = 1 << size;
2786 align *= 8;
2787 } else {
2788 size = 1 << size;
2789 align *= 4*size;
2790 }
2791 }
2792
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2794 return MCDisassembler::Fail;
2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2796 return MCDisassembler::Fail;
2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2798 return MCDisassembler::Fail;
2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2800 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2801 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2803 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2804 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2807 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808 Inst.addOperand(MCOperand::CreateImm(align));
2809
2810 if (Rm == 0xD)
2811 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2812 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2814 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2815 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2816
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2817 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2818}
2819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2820static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2821DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2822 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2824
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2826 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2827 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2828 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2829 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2830 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2831 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2832 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2833
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2834 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2835 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2836 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2837 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2839 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2840 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2841
2842 Inst.addOperand(MCOperand::CreateImm(imm));
2843
2844 switch (Inst.getOpcode()) {
2845 case ARM::VORRiv4i16:
2846 case ARM::VORRiv2i32:
2847 case ARM::VBICiv4i16:
2848 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2850 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2851 break;
2852 case ARM::VORRiv8i16:
2853 case ARM::VORRiv4i32:
2854 case ARM::VBICiv8i16:
2855 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2856 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2857 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2858 break;
2859 default:
2860 break;
2861 }
2862
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2863 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864}
2865
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2866static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2867 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2868 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2869
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2871 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2872 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2873 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2874 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2875
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2876 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2877 return MCDisassembler::Fail;
2878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2879 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2880 Inst.addOperand(MCOperand::CreateImm(8 << size));
2881
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2882 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883}
2884
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2885static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886 uint64_t Address, const void *Decoder) {
2887 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2888 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889}
2890
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2891static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2892 uint64_t Address, const void *Decoder) {
2893 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2894 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2895}
2896
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2897static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898 uint64_t Address, const void *Decoder) {
2899 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2900 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901}
2902
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2903static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904 uint64_t Address, const void *Decoder) {
2905 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2906 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907}
2908
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2909static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2911 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2912
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2914 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2915 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2916 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2917 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2918 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2919 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2920
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2922 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2923 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2925 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2926 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2927
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2928 switch (Inst.getOpcode()) {
2929 case ARM::VTBL2:
2930 case ARM::VTBX2:
2931 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2932 return MCDisassembler::Fail;
2933 break;
2934 default:
2935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2936 return MCDisassembler::Fail;
2937 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2941
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2942 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943}
2944
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2945static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2948
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2949 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2950 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2952 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2954
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2955 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2956 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2957 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2958 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2959 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2960 case ARM::tADDrSPi:
2961 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2962 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2963 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2964
2965 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2966 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967}
2968
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2969static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2970 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2971 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
2972 true, 2, Inst, Decoder))
2973 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2974 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2975}
2976
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2977static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2979 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
2980 true, 4, Inst, Decoder))
2981 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2982 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2983}
2984
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2985static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2986 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2987 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
2988 true, 2, Inst, Decoder))
2989 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2990 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2991}
2992
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2993static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2994 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2995 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2996
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2997 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2998 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3000 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3001 return MCDisassembler::Fail;
3002 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3003 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3005 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3006}
3007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3008static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3010 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3011
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3012 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3013 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3015 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3016 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3017 Inst.addOperand(MCOperand::CreateImm(imm));
3018
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3019 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3020}
3021
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3022static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3023 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3024 unsigned imm = Val << 2;
3025
3026 Inst.addOperand(MCOperand::CreateImm(imm));
3027 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3028
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3029 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3030}
3031
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3032static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3033 uint64_t Address, const void *Decoder) {
3034 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3035 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3036
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3037 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3038}
3039
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3040static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3041 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3042 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3043
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3044 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3045 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3046 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3047
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3049 return MCDisassembler::Fail;
3050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3051 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3052 Inst.addOperand(MCOperand::CreateImm(imm));
3053
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3054 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3055}
3056
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3057static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3058 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3059 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3060
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3061 switch (Inst.getOpcode()) {
3062 case ARM::t2PLDs:
3063 case ARM::t2PLDWs:
3064 case ARM::t2PLIs:
3065 break;
3066 default: {
3067 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3068 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3069 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3070 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3071 }
3072
3073 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3074 if (Rn == 0xF) {
3075 switch (Inst.getOpcode()) {
3076 case ARM::t2LDRBs:
3077 Inst.setOpcode(ARM::t2LDRBpci);
3078 break;
3079 case ARM::t2LDRHs:
3080 Inst.setOpcode(ARM::t2LDRHpci);
3081 break;
3082 case ARM::t2LDRSHs:
3083 Inst.setOpcode(ARM::t2LDRSHpci);
3084 break;
3085 case ARM::t2LDRSBs:
3086 Inst.setOpcode(ARM::t2LDRSBpci);
3087 break;
3088 case ARM::t2PLDs:
3089 Inst.setOpcode(ARM::t2PLDi12);
3090 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3091 break;
3092 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3093 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3094 }
3095
3096 int imm = fieldFromInstruction32(Insn, 0, 12);
3097 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3098 Inst.addOperand(MCOperand::CreateImm(imm));
3099
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3100 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3101 }
3102
3103 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3104 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3105 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3106 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3107 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3108
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3109 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3110}
3111
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3112static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3113 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3114 int imm = Val & 0xFF;
3115 if (!(Val & 0x100)) imm *= -1;
3116 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3117
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3118 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3119}
3120
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3121static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3122 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3123 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3124
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3125 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3126 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3127
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3129 return MCDisassembler::Fail;
3130 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3131 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3132
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3133 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134}
3135
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3136static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3137 uint64_t Address, const void *Decoder) {
3138 DecodeStatus S = MCDisassembler::Success;
3139
3140 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3141 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3142
3143 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3144 return MCDisassembler::Fail;
3145
3146 Inst.addOperand(MCOperand::CreateImm(imm));
3147
3148 return S;
3149}
3150
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3151static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3152 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3153 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3154 if (Val == 0)
3155 imm = INT32_MIN;
3156 else if (!(Val & 0x100))
3157 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3158 Inst.addOperand(MCOperand::CreateImm(imm));
3159
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3160 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3161}
3162
3163
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3164static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3165 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3166 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3167
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3168 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3169 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3170
3171 // Some instructions always use an additive offset.
3172 switch (Inst.getOpcode()) {
3173 case ARM::t2LDRT:
3174 case ARM::t2LDRBT:
3175 case ARM::t2LDRHT:
3176 case ARM::t2LDRSBT:
3177 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3178 case ARM::t2STRT:
3179 case ARM::t2STRBT:
3180 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3181 imm |= 0x100;
3182 break;
3183 default:
3184 break;
3185 }
3186
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3188 return MCDisassembler::Fail;
3189 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3190 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3191
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3192 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3193}
3194
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3195static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3196 uint64_t Address, const void *Decoder) {
3197 DecodeStatus S = MCDisassembler::Success;
3198
3199 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3200 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3201 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3202 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3203 addr |= Rn << 9;
3204 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3205
3206 if (!load) {
3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3208 return MCDisassembler::Fail;
3209 }
3210
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3211 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3212 return MCDisassembler::Fail;
3213
3214 if (load) {
3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3216 return MCDisassembler::Fail;
3217 }
3218
3219 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3220 return MCDisassembler::Fail;
3221
3222 return S;
3223}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3224
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3225static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3226 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3228
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3229 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3230 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3231
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3233 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3234 Inst.addOperand(MCOperand::CreateImm(imm));
3235
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3236 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3237}
3238
3239
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3240static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3241 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3242 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3243
3244 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3245 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3246 Inst.addOperand(MCOperand::CreateImm(imm));
3247
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3248 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3249}
3250
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3251static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3252 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3253 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3254
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3255 if (Inst.getOpcode() == ARM::tADDrSP) {
3256 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3257 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3260 return MCDisassembler::Fail;
3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3262 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3263 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3264 } else if (Inst.getOpcode() == ARM::tADDspr) {
3265 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3266
3267 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3268 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3270 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3271 }
3272
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3273 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3274}
3275
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3276static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3277 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3278 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3279 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3280
3281 Inst.addOperand(MCOperand::CreateImm(imod));
3282 Inst.addOperand(MCOperand::CreateImm(flags));
3283
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3284 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3285}
3286
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3287static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3288 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3289 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3290 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3291 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3292
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3293 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3294 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3295 Inst.addOperand(MCOperand::CreateImm(add));
3296
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3297 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3298}
3299
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3300static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3301 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3302 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3303 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3304 true, 4, Inst, Decoder))
3305 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3306 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3307}
3308
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3309static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3310 uint64_t Address, const void *Decoder) {
3311 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3312 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3313
3314 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3315 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3316}
3317
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3318static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3319DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3320 uint64_t Address, const void *Decoder) {
3321 DecodeStatus S = MCDisassembler::Success;
3322
3323 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3324 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3325
3326 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3328 return MCDisassembler::Fail;
3329 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3330 return MCDisassembler::Fail;
3331 return S;
3332}
3333
3334static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3335DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3336 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3337 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3338
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3339 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3340 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3341 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3342 switch (opc) {
3343 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3344 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3345 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3346 Inst.setOpcode(ARM::t2DSB);
3347 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3348 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3349 Inst.setOpcode(ARM::t2DMB);
3350 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3351 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3352 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3353 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3354 }
3355
3356 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3357 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3358 }
3359
3360 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3361 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3362 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3363 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3364 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3365
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3366 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3367 return MCDisassembler::Fail;
3368 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3369 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3370
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3371 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3372}
3373
3374// Decode a shifted immediate operand. These basically consist
3375// of an 8-bit value, and a 4-bit directive that specifies either
3376// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3377static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3378 uint64_t Address, const void *Decoder) {
3379 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3380 if (ctrl == 0) {
3381 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3382 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3383 switch (byte) {
3384 case 0:
3385 Inst.addOperand(MCOperand::CreateImm(imm));
3386 break;
3387 case 1:
3388 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3389 break;
3390 case 2:
3391 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3392 break;
3393 case 3:
3394 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3395 (imm << 8) | imm));
3396 break;
3397 }
3398 } else {
3399 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3400 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3401 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3402 Inst.addOperand(MCOperand::CreateImm(imm));
3403 }
3404
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3405 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3406}
3407
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3408static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3409DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3410 uint64_t Address, const void *Decoder){
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3411 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3412 true, 2, Inst, Decoder))
3413 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3414 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3415}
3416
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3417static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3418 uint64_t Address, const void *Decoder){
Kevin Enderby09433032012-02-27 18:15:15 +0000[diff] [blame]3419 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3420 true, 4, Inst, Decoder))
3421 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3422 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3423}
3424
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3425static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3426 uint64_t Address, const void *Decoder) {
3427 switch (Val) {
3428 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3429 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3430 case 0xF: // SY
3431 case 0xE: // ST
3432 case 0xB: // ISH
3433 case 0xA: // ISHST
3434 case 0x7: // NSH
3435 case 0x6: // NSHST
3436 case 0x3: // OSH
3437 case 0x2: // OSHST
3438 break;
3439 }
3440
3441 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3442 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3443}
3444
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3445static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3446 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3447 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3448 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3449 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3450}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3451
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3452static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3453 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3454 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3455
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3456 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3457 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3458 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3459
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3460 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3461
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3463 return MCDisassembler::Fail;
3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3465 return MCDisassembler::Fail;
3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3467 return MCDisassembler::Fail;
3468 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3469 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3470
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3471 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3472}
3473
3474
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3475static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3476 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3477 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3478
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3479 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3480 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3481 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3482 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3483
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3484 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3485 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3486
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3487 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3488 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3489
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3491 return MCDisassembler::Fail;
3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3493 return MCDisassembler::Fail;
3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3495 return MCDisassembler::Fail;
3496 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3497 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3498
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3499 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3500}
3501
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3502static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3503 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3504 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3505
3506 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3507 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3508 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3509 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3510 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3511 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3512
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3513 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3514
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3516 return MCDisassembler::Fail;
3517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3518 return MCDisassembler::Fail;
3519 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3520 return MCDisassembler::Fail;
3521 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3522 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3523
3524 return S;
3525}
3526
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3527static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3528 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3529 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3530
3531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3532 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3533 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3534 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3535 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3536 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3537 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3538
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3539 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3540 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3541
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3545 return MCDisassembler::Fail;
3546 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3547 return MCDisassembler::Fail;
3548 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3549 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3550
3551 return S;
3552}
3553
3554
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3555static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3556 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3557 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3558
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3559 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3560 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3561 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3562 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3563 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3564 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3565
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3566 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3567
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3569 return MCDisassembler::Fail;
3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3571 return MCDisassembler::Fail;
3572 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3573 return MCDisassembler::Fail;
3574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3575 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3576
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3577 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3578}
3579
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3580static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3581 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3582 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3583
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3584 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3585 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3586 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3587 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3588 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3589 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3590
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3591 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3592
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3600 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3601
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3602 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3603}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3604
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3605static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3606 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3607 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3608
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3610 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3611 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3612 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3613 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3614
3615 unsigned align = 0;
3616 unsigned index = 0;
3617 switch (size) {
3618 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3619 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3620 case 0:
3621 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3622 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3623 index = fieldFromInstruction32(Insn, 5, 3);
3624 break;
3625 case 1:
3626 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3627 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3628 index = fieldFromInstruction32(Insn, 6, 2);
3629 if (fieldFromInstruction32(Insn, 4, 1))
3630 align = 2;
3631 break;
3632 case 2:
3633 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3634 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3635 index = fieldFromInstruction32(Insn, 7, 1);
3636 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3637 align = 4;
3638 }
3639
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3641 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3642 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3644 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3645 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3647 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3648 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3649 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3650 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3652 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3653 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3654 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3655 }
3656
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3658 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3659 Inst.addOperand(MCOperand::CreateImm(index));
3660
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3661 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3662}
3663
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3664static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3665 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3666 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3667
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3669 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3670 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3671 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3672 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3673
3674 unsigned align = 0;
3675 unsigned index = 0;
3676 switch (size) {
3677 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3678 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3679 case 0:
3680 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3681 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3682 index = fieldFromInstruction32(Insn, 5, 3);
3683 break;
3684 case 1:
3685 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3686 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3687 index = fieldFromInstruction32(Insn, 6, 2);
3688 if (fieldFromInstruction32(Insn, 4, 1))
3689 align = 2;
3690 break;
3691 case 2:
3692 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3693 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3694 index = fieldFromInstruction32(Insn, 7, 1);
3695 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3696 align = 4;
3697 }
3698
3699 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3701 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3702 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3704 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3706 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3707 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3709 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3710 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3711 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3712 }
3713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3715 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3716 Inst.addOperand(MCOperand::CreateImm(index));
3717
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3718 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3719}
3720
3721
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3722static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3723 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3724 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3725
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3726 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3727 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3728 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3729 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3730 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3731
3732 unsigned align = 0;
3733 unsigned index = 0;
3734 unsigned inc = 1;
3735 switch (size) {
3736 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3737 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3738 case 0:
3739 index = fieldFromInstruction32(Insn, 5, 3);
3740 if (fieldFromInstruction32(Insn, 4, 1))
3741 align = 2;
3742 break;
3743 case 1:
3744 index = fieldFromInstruction32(Insn, 6, 2);
3745 if (fieldFromInstruction32(Insn, 4, 1))
3746 align = 4;
3747 if (fieldFromInstruction32(Insn, 5, 1))
3748 inc = 2;
3749 break;
3750 case 2:
3751 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3752 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3753 index = fieldFromInstruction32(Insn, 7, 1);
3754 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3755 align = 8;
3756 if (fieldFromInstruction32(Insn, 6, 1))
3757 inc = 2;
3758 break;
3759 }
3760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3762 return MCDisassembler::Fail;
3763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3764 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3765 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3767 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3768 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3770 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3771 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3772 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3773 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3775 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3776 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3777 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3778 }
3779
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3781 return MCDisassembler::Fail;
3782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3783 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3784 Inst.addOperand(MCOperand::CreateImm(index));
3785
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3786 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3787}
3788
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3789static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3790 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3791 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3792
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3793 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3795 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3796 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3797 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3798
3799 unsigned align = 0;
3800 unsigned index = 0;
3801 unsigned inc = 1;
3802 switch (size) {
3803 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3804 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3805 case 0:
3806 index = fieldFromInstruction32(Insn, 5, 3);
3807 if (fieldFromInstruction32(Insn, 4, 1))
3808 align = 2;
3809 break;
3810 case 1:
3811 index = fieldFromInstruction32(Insn, 6, 2);
3812 if (fieldFromInstruction32(Insn, 4, 1))
3813 align = 4;
3814 if (fieldFromInstruction32(Insn, 5, 1))
3815 inc = 2;
3816 break;
3817 case 2:
3818 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3819 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3820 index = fieldFromInstruction32(Insn, 7, 1);
3821 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3822 align = 8;
3823 if (fieldFromInstruction32(Insn, 6, 1))
3824 inc = 2;
3825 break;
3826 }
3827
3828 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3830 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3833 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3834 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3835 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3836 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3838 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3839 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3840 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3841 }
3842
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3844 return MCDisassembler::Fail;
3845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3846 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3847 Inst.addOperand(MCOperand::CreateImm(index));
3848
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3849 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3850}
3851
3852
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3853static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3854 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3855 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3856
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3858 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3859 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3860 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3861 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3862
3863 unsigned align = 0;
3864 unsigned index = 0;
3865 unsigned inc = 1;
3866 switch (size) {
3867 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3868 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3869 case 0:
3870 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3871 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 index = fieldFromInstruction32(Insn, 5, 3);
3873 break;
3874 case 1:
3875 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3876 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3877 index = fieldFromInstruction32(Insn, 6, 2);
3878 if (fieldFromInstruction32(Insn, 5, 1))
3879 inc = 2;
3880 break;
3881 case 2:
3882 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3883 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3884 index = fieldFromInstruction32(Insn, 7, 1);
3885 if (fieldFromInstruction32(Insn, 6, 1))
3886 inc = 2;
3887 break;
3888 }
3889
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3893 return MCDisassembler::Fail;
3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3895 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3896
3897 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3899 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3900 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3902 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3903 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3904 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3905 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3907 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3908 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3909 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3910 }
3911
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3915 return MCDisassembler::Fail;
3916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3917 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3918 Inst.addOperand(MCOperand::CreateImm(index));
3919
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3920 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3921}
3922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3923static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3924 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3925 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3926
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3929 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3930 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3931 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3932
3933 unsigned align = 0;
3934 unsigned index = 0;
3935 unsigned inc = 1;
3936 switch (size) {
3937 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3938 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3939 case 0:
3940 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3941 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3942 index = fieldFromInstruction32(Insn, 5, 3);
3943 break;
3944 case 1:
3945 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3946 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3947 index = fieldFromInstruction32(Insn, 6, 2);
3948 if (fieldFromInstruction32(Insn, 5, 1))
3949 inc = 2;
3950 break;
3951 case 2:
3952 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3953 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3954 index = fieldFromInstruction32(Insn, 7, 1);
3955 if (fieldFromInstruction32(Insn, 6, 1))
3956 inc = 2;
3957 break;
3958 }
3959
3960 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3962 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3963 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3965 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3966 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3967 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3968 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3970 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3971 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3972 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3973 }
3974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3976 return MCDisassembler::Fail;
3977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3978 return MCDisassembler::Fail;
3979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3980 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3981 Inst.addOperand(MCOperand::CreateImm(index));
3982
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3983 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3984}
3985
3986
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3987static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3988 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3989 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3990
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3991 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3992 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3993 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3994 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3995 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3996
3997 unsigned align = 0;
3998 unsigned index = 0;
3999 unsigned inc = 1;
4000 switch (size) {
4001 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4002 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4003 case 0:
4004 if (fieldFromInstruction32(Insn, 4, 1))
4005 align = 4;
4006 index = fieldFromInstruction32(Insn, 5, 3);
4007 break;
4008 case 1:
4009 if (fieldFromInstruction32(Insn, 4, 1))
4010 align = 8;
4011 index = fieldFromInstruction32(Insn, 6, 2);
4012 if (fieldFromInstruction32(Insn, 5, 1))
4013 inc = 2;
4014 break;
4015 case 2:
4016 if (fieldFromInstruction32(Insn, 4, 2))
4017 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4018 index = fieldFromInstruction32(Insn, 7, 1);
4019 if (fieldFromInstruction32(Insn, 6, 1))
4020 inc = 2;
4021 break;
4022 }
4023
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4025 return MCDisassembler::Fail;
4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4027 return MCDisassembler::Fail;
4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4029 return MCDisassembler::Fail;
4030 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4031 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4032
4033 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4035 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4036 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4038 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4039 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4040 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4041 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4043 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4044 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4045 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4046 }
4047
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4049 return MCDisassembler::Fail;
4050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4051 return MCDisassembler::Fail;
4052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4053 return MCDisassembler::Fail;
4054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4055 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4056 Inst.addOperand(MCOperand::CreateImm(index));
4057
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4058 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4059}
4060
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4061static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4062 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4063 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4064
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4065 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4066 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4067 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4068 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4069 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4070
4071 unsigned align = 0;
4072 unsigned index = 0;
4073 unsigned inc = 1;
4074 switch (size) {
4075 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4076 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4077 case 0:
4078 if (fieldFromInstruction32(Insn, 4, 1))
4079 align = 4;
4080 index = fieldFromInstruction32(Insn, 5, 3);
4081 break;
4082 case 1:
4083 if (fieldFromInstruction32(Insn, 4, 1))
4084 align = 8;
4085 index = fieldFromInstruction32(Insn, 6, 2);
4086 if (fieldFromInstruction32(Insn, 5, 1))
4087 inc = 2;
4088 break;
4089 case 2:
4090 if (fieldFromInstruction32(Insn, 4, 2))
4091 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4092 index = fieldFromInstruction32(Insn, 7, 1);
4093 if (fieldFromInstruction32(Insn, 6, 1))
4094 inc = 2;
4095 break;
4096 }
4097
4098 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4100 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4101 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4103 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4104 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4105 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4106 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4108 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4109 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4110 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4111 }
4112
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4114 return MCDisassembler::Fail;
4115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4120 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4121 Inst.addOperand(MCOperand::CreateImm(index));
4122
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4123 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4124}
4125
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4126static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4127 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4128 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4129 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4130 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4131 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4132 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4133 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4134
4135 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4136 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4137
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4138 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4139 return MCDisassembler::Fail;
4140 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4141 return MCDisassembler::Fail;
4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4143 return MCDisassembler::Fail;
4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4145 return MCDisassembler::Fail;
4146 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4147 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4148
4149 return S;
4150}
4151
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4152static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4153 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4154 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4155 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4156 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4157 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4158 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4159 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4160
4161 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4162 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4163
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4165 return MCDisassembler::Fail;
4166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4167 return MCDisassembler::Fail;
4168 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4169 return MCDisassembler::Fail;
4170 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4171 return MCDisassembler::Fail;
4172 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4173 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4174
4175 return S;
4176}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4177
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4178static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4179 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4180 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4181 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4182 // The InstPrinter needs to have the low bit of the predicate in
4183 // the mask operand to be able to print it properly.
4184 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4185
4186 if (pred == 0xF) {
4187 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4188 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4189 }
4190
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4191 if ((mask & 0xF) == 0) {
4192 // Preserve the high bit of the mask, which is the low bit of
4193 // the predicate.
4194 mask &= 0x10;
4195 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4196 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4197 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4198
4199 Inst.addOperand(MCOperand::CreateImm(pred));
4200 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4201 return S;
4202}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4203
4204static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4205DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4206 uint64_t Address, const void *Decoder) {
4207 DecodeStatus S = MCDisassembler::Success;
4208
4209 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4210 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4212 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4213 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4214 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4215 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4216 bool writeback = (W == 1) | (P == 0);
4217
4218 addr |= (U << 8) | (Rn << 9);
4219
4220 if (writeback && (Rn == Rt || Rn == Rt2))
4221 Check(S, MCDisassembler::SoftFail);
4222 if (Rt == Rt2)
4223 Check(S, MCDisassembler::SoftFail);
4224
4225 // Rt
4226 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4227 return MCDisassembler::Fail;
4228 // Rt2
4229 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4230 return MCDisassembler::Fail;
4231 // Writeback operand
4232 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 // addr
4235 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4236 return MCDisassembler::Fail;
4237
4238 return S;
4239}
4240
4241static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4242DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4243 uint64_t Address, const void *Decoder) {
4244 DecodeStatus S = MCDisassembler::Success;
4245
4246 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4247 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4248 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4249 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4250 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4251 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4252 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4253 bool writeback = (W == 1) | (P == 0);
4254
4255 addr |= (U << 8) | (Rn << 9);
4256
4257 if (writeback && (Rn == Rt || Rn == Rt2))
4258 Check(S, MCDisassembler::SoftFail);
4259
4260 // Writeback operand
4261 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4262 return MCDisassembler::Fail;
4263 // Rt
4264 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4265 return MCDisassembler::Fail;
4266 // Rt2
4267 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4268 return MCDisassembler::Fail;
4269 // addr
4270 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4271 return MCDisassembler::Fail;
4272
4273 return S;
4274}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4275
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4276static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4277 uint64_t Address, const void *Decoder) {
4278 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4279 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4280 if (sign1 != sign2) return MCDisassembler::Fail;
4281
4282 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4283 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4284 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4285 Val |= sign1 << 12;
4286 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4287
4288 return MCDisassembler::Success;
4289}
4290
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4291static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4292 uint64_t Address,
4293 const void *Decoder) {
4294 DecodeStatus S = MCDisassembler::Success;
4295
4296 // Shift of "asr #32" is not allowed in Thumb2 mode.
4297 if (Val == 0x20) S = MCDisassembler::SoftFail;
4298 Inst.addOperand(MCOperand::CreateImm(Val));
4299 return S;
4300}
4301
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4302static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4303 uint64_t Address, const void *Decoder) {
4304 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4305 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4307 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4308
4309 if (pred == 0xF)
4310 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4311
4312 DecodeStatus S = MCDisassembler::Success;
4313 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4314 return MCDisassembler::Fail;
4315 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4320 return MCDisassembler::Fail;
4321
4322 return S;
4323}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4324
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4325static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4326 uint64_t Address, const void *Decoder) {
4327 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4328 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4329 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4330 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4331 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4332 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4333
4334 DecodeStatus S = MCDisassembler::Success;
4335
4336 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4337 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4338 Inst.setOpcode(ARM::VMOVv2f32);
4339 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4340 }
4341
4342 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4343
4344 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4345 return MCDisassembler::Fail;
4346 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4347 return MCDisassembler::Fail;
4348 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4349
4350 return S;
4351}
4352
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4353static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4354 uint64_t Address, const void *Decoder) {
4355 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4356 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4357 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4358 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4359 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4360 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4361
4362 DecodeStatus S = MCDisassembler::Success;
4363
4364 // VMOVv4f32 is ambiguous with these decodings.
4365 if (!(imm & 0x38) && cmode == 0xF) {
4366 Inst.setOpcode(ARM::VMOVv4f32);
4367 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4368 }
4369
4370 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4371
4372 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4373 return MCDisassembler::Fail;
4374 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4375 return MCDisassembler::Fail;
4376 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4377
4378 return S;
4379}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4380
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4381static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4382 uint64_t Address, const void *Decoder) {
4383 DecodeStatus S = MCDisassembler::Success;
4384
4385 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4386 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4387 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4388 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4389 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4390
4391 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4392 S = MCDisassembler::SoftFail;
4393
4394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4395 return MCDisassembler::Fail;
4396 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4397 return MCDisassembler::Fail;
4398 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4399 return MCDisassembler::Fail;
4400 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4401 return MCDisassembler::Fail;
4402 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404
4405 return S;
4406}
4407
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame^]4408static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4409 uint64_t Address, const void *Decoder) {
4410
4411 DecodeStatus S = MCDisassembler::Success;
4412
4413 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4414 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4415 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4416 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4417 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4418
4419 if ((cop & ~0x1) == 0xa)
4420 return MCDisassembler::Fail;
4421
4422 if (Rt == Rt2)
4423 S = MCDisassembler::SoftFail;
4424
4425 Inst.addOperand(MCOperand::CreateImm(cop));
4426 Inst.addOperand(MCOperand::CreateImm(opc1));
4427 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4428 return MCDisassembler::Fail;
4429 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4430 return MCDisassembler::Fail;
4431 Inst.addOperand(MCOperand::CreateImm(CRm));
4432
4433 return S;
4434}
4435