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gerrit-public.fairphone.software / platform / external / llvm / 1d7e8c6148a4356c16745f6496c38c737bd37c02
  1. 1d7e8c6 Fix a problem in the target detection for Debian GNU/kFreeBSD by Sylvestre Ledru · 13 years ago
  2. d7484e5 Treat f16 the same as f80/f128 for the purposes of generating constants during instruction selection. by Owen Anderson · 13 years ago
  3. 1c01249 Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. by Silviu Baranga · 13 years ago
  4. 82e1bba Added support for handling unpredictable arithmetic instructions on ARM. by Silviu Baranga · 13 years ago
  5. 940371b BBVectorize: Add the const modifier to the VectorizeConfig because we won't by Hongbin Zheng · 13 years ago
  6. bef377b Introduce the VectorizeConfig class, with which we can control the behavior by Hongbin Zheng · 13 years ago
  7. 17dcaf5 An oversight when applying the patches for r150956 and r150957 to a vanilla tree meant I forgot to svn add these testcases. by James Molloy · 13 years ago
  8. 87825e7 Add the function "vectorizeBasicBlock" which allow users vectorize a by Hongbin Zheng · 13 years ago
  9. 22378fd ARM assembly aliases for two-operand V[R]SHR instructions. by Jim Grosbach · 13 years ago
  10. 541b2a4 In MemoryBuffer::getOpenFile() make sure that the buffer is null-terminated if by Argyrios Kyrtzidis · 13 years ago
  11. b657a90 ARM assembly parsing for 'msr' plain 'cpsr' operand. by Jim Grosbach · 13 years ago
  12. 9243c4f Pass the right sign to TLI->isLegalICmpImmediate. by Jakob Stoklund Olesen · 13 years ago
  13. 63246de Do not include multiple -arch options in CPPFLAGS. by Bob Wilson · 13 years ago
  14. 68f404d Fix -Wnon-virtual-dtor warnings. by Michael J. Spencer · 13 years ago
  15. 56ce6b3 Reapply 154038 without the failing test. by Akira Hatanaka · 13 years ago
  16. 657a4e7 Revert r154038. It was causing make check failures. by Owen Anderson · 13 years ago
  17. ef74ca6 REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub register indices on the source registers. No simple test case by Pete Cooper · 13 years ago
  18. e25a2bd Fix a C++11 UDL conflict. by Benjamin Kramer · 13 years ago
  19. 9751b81 f16 FREM can now be legalized by promoting to f32 by Pete Cooper · 13 years ago
  20. e825fb3 Fix LowerGlobalAddress to produce instructions with the correct relocation by Akira Hatanaka · 13 years ago
  21. c75ceb7 Fix LowerJumpTable to produce instructions with the correct relocation by Akira Hatanaka · 13 years ago
  22. 86a2733 Fix LowerConstantPool to produce instructions with the correct relocation by Akira Hatanaka · 13 years ago
  23. c5041ca Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. by Jakob Stoklund Olesen · 13 years ago
  24. 1487cb3 Remove spurious debug output. by Jakob Stoklund Olesen · 13 years ago
  25. 03d830e Fix LowerBlockAddress to produce instructions with the correct relocation by Akira Hatanaka · 13 years ago
  26. 99c8a5a Add testcase for r154007, when a function has the optsize attribute, by Hongbin Zheng · 13 years ago
  27. 26c8dcc Always compute all the bits in ComputeMaskedBits. by Rafael Espindola · 13 years ago
  28. 00b73a5 LoopUnrollPass: Use variable "Threshold" instead of "CurrentThreshold" when by Hongbin Zheng · 13 years ago
  29. a95b4eb Move yaml::Stream's dtor out of line so it can see Scanner's dtor. by Benjamin Kramer · 13 years ago
  30. 32d1774 Implement DwarfLLVMRegPair::operator< without violating asymmetry. by Benjamin Kramer · 13 years ago
  31. 58609b7 Convert assert(false) followed by a return to llvm_unreachable by Craig Topper · 13 years ago
  32. 8d41a1a Remove default case from switch that was already covering all cases. by Craig Topper · 13 years ago
  33. e5ae51a Removed useless switch for default case when switch was covering all the enum values by Pete Cooper · 13 years ago
  34. a348fec Fix the install location for the Embedded makefile target. by Bob Wilson · 13 years ago
  35. c35146b Sorry about that. MSVC seems to accept just about any random string you give it ;/ by Michael J. Spencer · 13 years ago
  36. d13af63 Remove dead code for installing libLTO when building llvmCore. by Bob Wilson · 13 years ago
  37. 93210e8 Add YAML parser to Support. by Michael J. Spencer · 13 years ago
  38. 2ce63c7 Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095> by Pete Cooper · 13 years ago
  39. dda3a09 Removed one last bad continue statement meant to be removed in r153914. by Pete Cooper · 13 years ago
  40. 585d580 When building llvmCore, pass the SDKROOT and -arch setting to configure. by Bob Wilson · 13 years ago
  41. ac07407 Remove a reference to the C backend. by Bob Wilson · 13 years ago
  42. 9dbb018 Fix an issue in SimplifySetCC() specific to vector comparisons. by Chad Rosier · 13 years ago
  43. 1895fc9 Set soname for FreeBSD as well. Patch by Bernard Cafarelli! by Anton Korobeynikov · 13 years ago
  44. fa5b050 Fix thinko check for number of operands to be the one that actually by Eric Christopher · 13 years ago
  45. d5be48a Matrix simplification in PBQP may push infinite costs onto register options. by Lang Hames · 13 years ago
  46. 75e3b7f ARMDisassembler: drop bogus dependency on ARMCodeGen by Dylan Noblesmith · 13 years ago
  47. 70debec Object: drop bogus VMCore dependency by Dylan Noblesmith · 13 years ago
  48. 5fdf475 The speedup doesn't appear to have been from this, but was an anomaly of my testing machine. by Bill Wendling · 13 years ago
  49. f563fc3 Reserve space for the eventual filling of the vector. This gives a small speedup. by Bill Wendling · 13 years ago
  50. 43b32e0 Add an additional testcase which checks ops with multiple users. by Nadav Rotem · 13 years ago
  51. 9cd5e7a Make PPCCompilationCallbackC function to be static, so there will be no need to issue call via by Anton Korobeynikov · 13 years ago
  52. 9b1b25f Tidy up spacing in some tablegen outputs. by Craig Topper · 13 years ago
  53. 769bbfd Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. by Craig Topper · 13 years ago
  54. 90e7d4f Reformatting. No functionality change. by Bill Wendling · 13 years ago
  55. cbece8c As Eric pointed out, even a Debug build should be equal. Leave the flag that can turn off comparisons though. by Bill Wendling · 13 years ago
  56. 9dd16d4 Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler. by Akira Hatanaka · 13 years ago
  57. 0236594 Revert r153924. There were buildbot failures. by Akira Hatanaka · 13 years ago
  58. 885020a MIPS disassembler support. by Akira Hatanaka · 13 years ago
  59. 5aeda3f Cleanup set_union usage. The same thing but a bit cleaner now. by Andrew Trick · 13 years ago
  60. f127595 Use std::set_union instead of nasty custom code. by Andrew Trick · 13 years ago
  61. 6126a1e Add a line number for the scope of the function (starting at the first by Eric Christopher · 13 years ago
  62. 2e267ae Fixes to r153903. Added missing explanation of behaviour when the VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created by Pete Cooper · 13 years ago
  63. 1adc215 Compare the .o files only for release builds. Add an option to bypass the comparison altogether. by Bill Wendling · 13 years ago
  64. 789d5d8 Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen by Pete Cooper · 13 years ago
  65. 1c8cf21 Make dominatedBySlowTreeWalk private and assert cases handled by the caller. by Rafael Espindola · 13 years ago
  66. e3b23cd Allocate virtual registers in ascending order. by Jakob Stoklund Olesen · 13 years ago
  67. 8a06af9 Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. by Pete Cooper · 13 years ago
  68. 3197b44 Add an option to turn off the expensive GVN load PRE part of GVN. by Bill Wendling · 13 years ago
  69. 29f60f3 Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. by Owen Anderson · 13 years ago
  70. be9fe49 During two-address lowering, rescheduling an instruction does not untie by Lang Hames · 13 years ago
  71. ce16784 No need to run llvm-as. by Rafael Espindola · 13 years ago
  72. a551a48 Initial 64 bit direct object support. by Akira Hatanaka · 13 years ago
  73. 70272aa The binutils for the IBM BG/P are too old to support CFI. by Hal Finkel · 13 years ago
  74. a47406c Add triple support for the IBM BG/P and BG/Q supercomputers. by Hal Finkel · 13 years ago
  75. 60777d8 Turn on the accelerator tables for Darwin. by Eric Christopher · 13 years ago
  76. aad9c3f Fast fix for PR12343: http://llvm.org/bugs/show_bug.cgi?id=12343 by Stepan Dyatkovskiy · 13 years ago
  77. 466958c Implement the SVR4 byval alignment for aggregates. Fixing a FIXME. by Roman Divacky · 13 years ago
  78. 545b962 Second part for the 153874 one by Silviu Baranga · 13 years ago
  79. 50ac2e9 Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. by Silviu Baranga · 13 years ago
  80. 5004e98 Add missing 'd'. by Rafael Espindola · 13 years ago
  81. 8ba9405 Hack the hack. If we have a situation where an ASM object is defined but isn't by Bill Wendling · 13 years ago
  82. 9433859 Emit the asm writer's mnemonic table with SequenceToOffsetTable. by Benjamin Kramer · 13 years ago
  83. c97ef61 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. by Benjamin Kramer · 13 years ago
  84. fab3f7e Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. by Craig Topper · 13 years ago
  85. 44b5e6d Optimizing swizzles of complex shuffles may generate additional complex shuffles. by Nadav Rotem · 13 years ago
  86. 7c0b3c1 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. by Craig Topper · 13 years ago
  87. 79e22d8 Fix CXXFLAGS for huge_val.m4. by Eric Christopher · 13 years ago
  88. 17463b3 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. by Craig Topper · 13 years ago
  89. 1fcbca0 It could come about that we parse the inline ASM before we get a potential by Bill Wendling · 13 years ago
  90. a4bd58b Use SequenceToOffsetTable to generate instruction name table for AsmWriter. by Craig Topper · 13 years ago
  91. caa2c40 Start cleaning up the InlineCost class. This switches to sentinel values by Chandler Carruth · 13 years ago
  92. b66e943 Fix some 80-col. violations I introduced with the A2 PPC64 core. by Hal Finkel · 13 years ago
  93. 19aa2b5 Enable prefetch generation on PPC64. by Hal Finkel · 13 years ago
  94. 730acfb Add LdStSTD* itin. for the PPC64 A2 core. by Hal Finkel · 13 years ago
  95. 4ac9081 This commit contains a few changes that had to go in together. by Nadav Rotem · 13 years ago
  96. 16d6eae Fix typo. by Lang Hames · 13 years ago
  97. 3f31d49 Set the default PPC node scheduling preference to ILP (for the embedded cores). by Hal Finkel · 13 years ago
  98. 800125f Add ppc440 itin. entries for LdStSTD* by Hal Finkel · 13 years ago
  99. 97c9d4c Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores. by Hal Finkel · 13 years ago
  100. 4d989ac Add instruction itinerary for the PPC64 A2 core. by Hal Finkel · 13 years ago