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gerrit-public.fairphone.software / platform / external / llvm / 34c4485b7479a12b5ef1cb15d27e96277e8a499a / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. a1c1100 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. by Owen Anderson · 14 years ago
  2. a680444 Fix 80 columns violations. by Owen Anderson · 14 years ago
  3. c047dca Fix up r137380 based on post-commit review by Jim Grosbach. by James Molloy · 14 years ago
  4. b45b11b The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. by Owen Anderson · 14 years ago
  5. eaca928 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. by Owen Anderson · 14 years ago
  6. f1eab59 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. by Owen Anderson · 14 years ago
  7. 9f7e831 Spelling fail. by Owen Anderson · 14 years ago
  8. 9ab0f25 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. by Owen Anderson · 14 years ago
  9. 1af7f72 Update for feedback from Jim. by Owen Anderson · 14 years ago
  10. 86ce852 ARMDisassembler: Always return a size, even when disassembling fails. by Benjamin Kramer · 14 years ago
  11. 96425c8 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. by Owen Anderson · 14 years ago
  12. 9bd655d Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. by Owen Anderson · 14 years ago
  13. 9990683 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. by Owen Anderson · 14 years ago
  14. f440820 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. by Owen Anderson · 14 years ago
  15. 12a1e3b Be careful not to walk off the end of the operand info list while updating VFP predicates. by Owen Anderson · 14 years ago
  16. 3e74d6f Move TargetRegistry and TargetSelect from Target to Support where they belong. by Evan Cheng · 14 years ago
  17. e234d02 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. by Owen Anderson · 14 years ago
  18. 82265a2 Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. by Owen Anderson · 14 years ago
  19. 6153a03 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. by Owen Anderson · 14 years ago
  20. 8e1e60b Reject invalid imod values in t2CPS instructions. by Owen Anderson · 14 years ago
  21. 357ec68 Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. by Owen Anderson · 14 years ago
  22. 2cbf210 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. by Owen Anderson · 14 years ago
  23. f1c8e3e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. by Owen Anderson · 14 years ago
  24. b113ec5 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. by Owen Anderson · 14 years ago
  25. 78affc9 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. by Owen Anderson · 14 years ago
  26. 846dd95 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. by Owen Anderson · 14 years ago
  27. 1dd56f0 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. by Owen Anderson · 14 years ago
  28. 14090bf Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. by Owen Anderson · 14 years ago
  29. c405782 Tidy up. 80 columns. by Jim Grosbach · 14 years ago
  30. 70939ee ARM clean up the imm_sr operand class representation. by Jim Grosbach · 14 years ago
  31. 0aa38ab Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. by Owen Anderson · 14 years ago
  32. 83e3f67 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. by Owen Anderson · 14 years ago
  33. 1628030 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. by Owen Anderson · 14 years ago
  34. ef2865a Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. by Owen Anderson · 14 years ago
  35. c537f3b Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. by Owen Anderson · 14 years ago
  36. 7a2e177 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. by Owen Anderson · 14 years ago
  37. 0d09499 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. by Owen Anderson · 14 years ago
  38. 79628e9 Fix decoding of ARM-mode STRH. by Owen Anderson · 14 years ago
  39. 7cdbf08 Fix decoding of pre-indexed stores. by Owen Anderson · 14 years ago
  40. 3f3570a Separate decoding for STREXD and LDREXD to make each work better. by Owen Anderson · 14 years ago
  41. 342ebd5 ARM STRT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  42. adf2b09 Add another accidentally omitted predicate operand. by Owen Anderson · 14 years ago
  43. 1fb6673 Add missing predicate operand on SMLA and friends. by Owen Anderson · 14 years ago
  44. cbfc044 Fix decoding support for STREXD and LDREXD. by Owen Anderson · 14 years ago
  45. 508e1d3 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. by Owen Anderson · 14 years ago
  46. 26d2f0a Continue to tighten decoding by performing more operand validation. by Owen Anderson · 14 years ago
  47. 10348e7 ARM STRBT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  48. 71156a6 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. by Owen Anderson · 14 years ago
  49. 2b7b238 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. by Owen Anderson · 14 years ago
  50. ae0bc5d Improve error checking in the new ARM disassembler. Patch by James Molloy. by Owen Anderson · 14 years ago
  51. 5999926 ARM LDRT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  52. 8533eba Add initial support for decoding NEON instructions in Thumb2 mode. by Owen Anderson · 14 years ago
  53. 10cbaab Cleanups based on Nick Lewycky's feedback. by Owen Anderson · 14 years ago
  54. 33e5751 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. by Owen Anderson · 14 years ago
  55. de317f4 Tighten operand checking of register-shifted-register operands. by Owen Anderson · 14 years ago
  56. c36481c Tighten operand checking on memory barrier instructions. by Owen Anderson · 14 years ago
  57. 35008c2 Tighten operand checking on CPS instructions. by Owen Anderson · 14 years ago
  58. 51c9805 Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. by Owen Anderson · 14 years ago
  59. 793b811 ARM Disassembler: sign extend branch immediates. by Benjamin Kramer · 14 years ago
  60. 51157d2 Silence an false-positive warning. by Owen Anderson · 14 years ago
  61. bd9091c Tighten Thumb1 branch predicate decoding. by Owen Anderson · 14 years ago
  62. 8d7d2e1 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. by Owen Anderson · 14 years ago
  63. 7ce0579 ARM refactoring assembly parsing of memory address operands. by Jim Grosbach · 14 years ago
  64. 4aaf346 Fix typo in the comment. by Johnny Chen · 14 years ago
  65. bd33276 Adding support for printing operands symbolically to llvm's public 'C' by Kevin Enderby · 14 years ago
  66. eca915f Fixed the t2PLD and friends disassembly and add two test cases. by Johnny Chen · 14 years ago
  67. 8cb9886 Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! by Johnny Chen · 14 years ago
  68. 83ccbff Plug a leak in the arm disassembler and put the tests back. by Benjamin Kramer · 14 years ago
  69. c59c87c For ARM Disassembler, start a newline to dump the opcode and friends for an instruction. by Johnny Chen · 14 years ago
  70. 18b475f LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. by Johnny Chen · 14 years ago
  71. 971b83b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. by Owen Anderson · 15 years ago
  72. eb6779c Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. by Owen Anderson · 15 years ago
  73. 9d63d90 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. by Owen Anderson · 15 years ago
  74. 80dd3e0 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the by Owen Anderson · 15 years ago
  75. bc7deb0 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. by Evan Cheng · 15 years ago
  76. 55561d1 Detabify and clean up 80 column violations. by Jim Grosbach · 15 years ago
  77. 38e1390 Add ARM Disassembler to the CMake build. by Oscar Fuentes · 15 years ago
  78. 186acea ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. by NAKAMURA Takumi · 15 years ago
  79. 270159f The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td by Johnny Chen · 15 years ago
  80. eaf1c98 Move the ARM SSAT and USAT optional shift amount operand out of the by Bob Wilson · 15 years ago
  81. ef37e3a For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', by Johnny Chen · 15 years ago
  82. 6bcf52f More IT instruction error-handling improvements from fuzzing. by Johnny Chen · 15 years ago
  83. d0f3c46 Better error handling of invalid IT mask '0000', instead of just asserting. by Johnny Chen · 15 years ago
  84. af5b0e8 Fixed logic error. Should check Builder for validity before calling SetSession by Johnny Chen · 15 years ago
  85. d907d25 Fixed another assert exposed by fuzzing. The utility function getRegisterEnum() by Johnny Chen · 15 years ago
  86. 9899f70 Fixed a nasty layering violation in the edis source by Sean Callanan · 15 years ago
  87. 7fb053d Get rid of traling whitespaces. No functionality change. by Johnny Chen · 15 years ago
  88. 9d563b6 The disassembler impl. of MCDisassembler::getInstruction() was using the pattern by Johnny Chen · 15 years ago
  89. b68a3ee Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen by Johnny Chen · 15 years ago
  90. 49d9dc4 --- Reverse-merging r98637 into '.': by Bob Wilson · 15 years ago
  91. d30a98e Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend by Johnny Chen · 15 years ago