- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 7c07aeb Bug fix. Must also match ResNo when matching an operand with a user. by Evan Cheng · 17 years ago
- eb57ea7 Make labels work in asm blocks; allow labels as by Dale Johannesen · 17 years ago
- 514ab34 Executive summary: getTypeSize -> getTypeStoreSize / getABITypeSize. by Duncan Sands · 17 years ago
- 32dfbea EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like by Evan Cheng · 17 years ago
- f10c973 If a node that defines a physical register that is expensive to copy. The by Evan Cheng · 17 years ago
- cb406c2 Use empty() member functions when that's what's being tested for instead by Dan Gohman · 17 years ago
- 22a5299 If two instructions are both two-address code, favors (schedule closer to by Evan Cheng · 17 years ago
- 74d2fd8 Trim some unneeded fields. by Evan Cheng · 17 years ago
- 42d6027 - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo. by Evan Cheng · 17 years ago
- 9efce63 Allow copyRegToReg to emit cross register classes copies. by Evan Cheng · 17 years ago
- a6fb1b6 Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. by Evan Cheng · 17 years ago
- 713a98d Use struct SDep instead of std::pair for SUnit pred and succ lists. First step by Evan Cheng · 17 years ago
- 6900132 Remove dead code. by Evan Cheng · 17 years ago
- 7df31dc Teach the dag scheduler to handle inline asm nodes with multi-value immediate operands. by Chris Lattner · 17 years ago
- 33d5595 Do not emit copies for physical register output if it's not used. by Evan Cheng · 17 years ago
- 8409747 Instead of adding copyfromreg's to handle physical definitions. Now isel can by Evan Cheng · 17 years ago
- e24f8f1 Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350 by Christopher Lamb · 17 years ago
- e7e7d0d Skeleton of post-RA scheduler; doesn't do anything yet. by Dale Johannesen · 17 years ago
- 5e2456c If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def. by Evan Cheng · 17 years ago
- af825c8 When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value. by Evan Cheng · 17 years ago
- 9912628 Change CalculateHeights and CalculateDepths to be non-recursive. by Evan Cheng · 17 years ago
- b5bec2b Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration by Dan Gohman · 17 years ago
- c01a530 Fix some VC++ warnings. by Jeff Cohen · 17 years ago
- a0a26b7 Code clean up. by Lauro Ramos Venancio · 17 years ago
- 8334b9f CopyToReg source operand can be a physical register. by Lauro Ramos Venancio · 17 years ago
- 95ad943 print target nodes nicely by Chris Lattner · 17 years ago
- 5d4a9f7 fix indentation by Chris Lattner · 17 years ago
- 0152829 Apply B Scott Michel's patch for PR1184, which improves diagnostics in an by Chris Lattner · 17 years ago
- ac9dcb9 For PR1195: by Reid Spencer · 17 years ago
- 831e037 switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This by Chris Lattner · 18 years ago
- 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
- de268f7 Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift(). by Evan Cheng · 18 years ago
- f6d039a Remove the DoubleTy special case. by Evan Cheng · 18 years ago
- e5530da Compensate for loss of DerivedTypes.h in TargetLowering.h by Reid Spencer · 18 years ago
- 489a87c CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg. by Evan Cheng · 18 years ago
- 832171c Removing even more <iostream> includes. by Bill Wendling · 18 years ago
- ba59a1e Match TargetInstrInfo changes. by Evan Cheng · 18 years ago
- c0f64ff Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead by Evan Cheng · 18 years ago
- 7ce4578 Matches MachineInstr changes. by Evan Cheng · 18 years ago
- 3ba433a Add methods to add implicit def use operands to a MI. by Evan Cheng · 18 years ago
- 438f7bc Add implicit def / use operands to MachineInstr. by Evan Cheng · 18 years ago
- 95f6ede Changes to use operand constraints to process two-address instructions. by Evan Cheng · 18 years ago
- efa46ce handle global address constant sdnodes by Chris Lattner · 18 years ago
- d42a523 Debug tweak. by Evan Cheng · 18 years ago
- d6594ae Added support for machine specific constantpool values. These are useful for by Evan Cheng · 18 years ago
- 09e4606 Completely eliminate def&use operands. Now a register operand is EITHER a by Chris Lattner · 18 years ago
- 228a18e switch the SUnit pred/succ sets from being std::sets to being smallvectors. by Chris Lattner · 18 years ago
- 3b97acd Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed. by Evan Cheng · 18 years ago
- 60f0992 Use an enumeration to eliminate data relocations. by Jim Laskey · 18 years ago
- 16d42c6 It was pointed out that DEBUG() is only available with -debug. by Jim Laskey · 18 years ago
- e37fe9b Ensure that dump calls that are associated with asserts are removed from by Jim Laskey · 18 years ago
- 8d3af5e Instructions with variable operands (variable_ops) can have a number required by Evan Cheng · 18 years ago
- 4c6f2f9 commuteInstruction() does not always create a new MI! by Evan Cheng · 18 years ago
- 16eee25 Eliminate a memory leak. by Evan Cheng · 18 years ago
- 21d03f2 lib/Target/Target.td by Evan Cheng · 18 years ago
- 9664541 Move function-live-in-handling code from the sdisel code to the scheduler. by Chris Lattner · 18 years ago
- 8820ad5 Fixing 2006-05-01-SchedCausingSpills.ll; some clean up by Evan Cheng · 18 years ago
- 07000c6 Refactor a bunch of includes so that TargetMachine.h doesn't have to include by Owen Anderson · 18 years ago
- 626da3d Duh. That could take a long time. by Evan Cheng · 18 years ago
- 13d41b9 Add capability to scheduler to commute nodes for profit. by Evan Cheng · 18 years ago
- e165a78 Refactor scheduler code. Move register-reduction list scheduler to a by Evan Cheng · 18 years ago
- 8b915b4 Remove and simplify some more machineinstr/machineoperand stuff. by Chris Lattner · 18 years ago
- 2d90ac7 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. by Chris Lattner · 18 years ago
- ea50fab Remove a bunch more SparcV9 specific stuff by Chris Lattner · 18 years ago
- a69571c Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. by Owen Anderson · 18 years ago
- 37efe67 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 18 years ago
- 45053fc fix spello by Chris Lattner · 18 years ago
- 54a30b9 TargetData doesn't know the alignment of vectors :( by Chris Lattner · 18 years ago
- 2f5806c Move some simple-sched-specific instance vars to the simple scheduler. by Chris Lattner · 18 years ago
- 1e433c5 prune #includes by Chris Lattner · 18 years ago
- e76074a move some simple scheduler methods into the simple scheduler by Chris Lattner · 18 years ago
- 8c7ef05 Make EmitNode take a SDNode instead of a NodeInfo* by Chris Lattner · 18 years ago
- df37506 Move the VRBase field from NodeInfo to being a separate, explicit, map. by Chris Lattner · 18 years ago
- be24e59 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy by Chris Lattner · 18 years ago
- b0d21ef Change the interface for getting a target HazardRecognizer to be more clean. by Chris Lattner · 18 years ago
- a93dfcd When a hazard recognizer needs noops to be inserted, do so. This represents by Chris Lattner · 18 years ago
- 404cb4f Added an offset field to ConstantPoolSDNode. by Evan Cheng · 18 years ago
- daf6bc6 Pass all the flags to the asm printer, not just the # operands. by Chris Lattner · 18 years ago
- fd6d282 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. by Chris Lattner · 18 years ago
- ed18b68 Refactor operand adding out to a new AddOperand method by Chris Lattner · 18 years ago
- c3a9f8d Record all of the expanded registers in the DAG and machine instr, fixing by Chris Lattner · 18 years ago
- 948d966 Make MachineConstantPool entries alignments explicit by Chris Lattner · 19 years ago
- f3afef3 Fix VC++ warning. by Jeff Cohen · 19 years ago
- cccf123 Get rid of some memory leaks identified by Valgrind by Evan Cheng · 19 years ago
- dc19b70 Add initial support for immediates. This allows us to compile this: by Chris Lattner · 19 years ago
- b8973bd Allow the specification of explicit alignments for constant pool entries. by Evan Cheng · 19 years ago
- 6656dd1 Handle physreg input/outputs. We now compile this: by Chris Lattner · 19 years ago
- acc43bf Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an by Chris Lattner · 19 years ago
- 46c01cf No need to keep track of top and bottom nodes in a group since the vector is by Evan Cheng · 19 years ago
- e0a5832 Keep track of bottom / top element of a set of flagged nodes. by Evan Cheng · 19 years ago
- 4ef1086 Factor out more instruction scheduler code to the base class. by Evan Cheng · 19 years ago
- a9c2091 Do some code refactoring on Jim's scheduler in preparation of the new list by Evan Cheng · 19 years ago
- f65d917 purity++ by Duraid Madina · 19 years ago
- e81aecb Disengage DEBUG_LOC from non-PPC targets. by Jim Laskey · 19 years ago
- d845582 Amend comment. by Jim Laskey · 19 years ago
- de48ee2 Create a strong dependency for loads following stores. This will leave a by Jim Laskey · 19 years ago
- 18840db Keep VC++ happy. by Jeff Cohen · 19 years ago
- bd2b621 Fix a bug Sabre was having where the DAG root was a group. The group dominator by Jim Laskey · 19 years ago
- 9022ed9 Groups were not emitted if the dominator node and the node in the ordering list by Jim Laskey · 19 years ago