Log - 4ee451de366474b9c228b4e5fa573795a715216d - platform/external/llvm

4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
180c210 More accurate checks for two-address constraints. by Evan Cheng · 17 years ago
d6c0758 Bring back a burr scheduling heuristic that's still needed. by Evan Cheng · 17 years ago
beec823 FIX for PR1799: When a load is unfolded from an instruction, check if it is a new node. If not, do not create a new SUnit. by Evan Cheng · 17 years ago
7da8f39 Bug fix. Passive nodes are not in SUnitMap. by Evan Cheng · 17 years ago
1fd15ba Add pseudo dependency to force two-address instruction to be scheduled after by Evan Cheng · 17 years ago
01d029b One mundane change: Change ReplaceAllUsesOfValueWith to *optionally* by Chris Lattner · 17 years ago
32dfbea EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like by Evan Cheng · 17 years ago
2eb4ebd Fix a typo in a comment. by Dan Gohman · 17 years ago
d5cb5a4 Chain producing nodes cannot be moved, not chain reading nodes. by Evan Cheng · 17 years ago
117c366 Oops. Didn't mean to leave this in. by Evan Cheng · 17 years ago
f10c973 If a node that defines a physical register that is expensive to copy. The by Evan Cheng · 17 years ago
22a5299 If two instructions are both two-address code, favors (schedule closer to by Evan Cheng · 17 years ago
ddde335 Remove a poor scheduling heuristic. by Evan Cheng · 17 years ago
74d2fd8 Trim some unneeded fields. by Evan Cheng · 17 years ago
cd1c00c Avoid inserting a live register more than once. by Evan Cheng · 17 years ago
2dc7a0e Boogs. by Evan Cheng · 17 years ago
a2ee275 Be smarter about which node to force schedule. Reduce # of duplications + copies; Added statistics. by Evan Cheng · 17 years ago
6e4c46c Backtracking only when it won't create a cycle. by Evan Cheng · 17 years ago
42d6027 - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo. by Evan Cheng · 17 years ago
a6fb1b6 Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. by Evan Cheng · 17 years ago
713a98d Use struct SDep instead of std::pair for SUnit pred and succ lists. First step by Evan Cheng · 17 years ago
6600377 Bug fixes. by Evan Cheng · 17 years ago
8d1bfad Minor cleanups to reduce some spurious differences between different by Dan Gohman · 17 years ago
e7e7d0d Skeleton of post-RA scheduler; doesn't do anything yet. by Dale Johannesen · 17 years ago
8212629 Remove unused variables. by David Greene · 17 years ago
a2a4885 Remove unnecessary attributions in comments. by David Greene · 17 years ago
a4ab2e8 Remove the "special tie breaker" because it resulted in inconsistent by David Greene · 17 years ago
0b2ce1f std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec. by Evan Cheng · 17 years ago
edc1d15 Fix a typo in a comment. by Dan Gohman · 17 years ago
c6deb3d Estimate a cost using the possible number of scratch registers required and use by Evan Cheng · 17 years ago
61230d1 Try schedule def + use closer whne Sethi-Ullman numbers are the same. by Evan Cheng · 17 years ago
2ba528b switch the sched unit map over to use a DenseMap instead of std::map. This by Chris Lattner · 18 years ago
fea997a Fit in 80 columns by Chris Lattner · 18 years ago
c8edc64 Naming consistency. by Evan Cheng · 18 years ago
c62d4bb Fix for PR1075: bottom-up register-reduction scheduling actually increases register pressure. by Evan Cheng · 18 years ago
832171c Removing even more <iostream> includes. by Bill Wendling · 18 years ago
ba59a1e Match TargetInstrInfo changes. by Evan Cheng · 18 years ago
d5ad440 Remove dead code; added a missing null ptr check. by Evan Cheng · 18 years ago
95f6ede Changes to use operand constraints to process two-address instructions. by Evan Cheng · 18 years ago
02cb49e silence warning by Chris Lattner · 18 years ago
3ed469c For PR786: by Reid Spencer · 18 years ago
1dabb68 Clean up. by Evan Cheng · 18 years ago
93467e7 CopyFromReg starts a live range so its use should not be considered a floater. by Evan Cheng · 18 years ago
d42a523 Debug tweak. by Evan Cheng · 18 years ago
a4f0b3a s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| by Chris Lattner · 18 years ago
228a18e switch the SUnit pred/succ sets from being std::sets to being smallvectors. by Chris Lattner · 18 years ago
eb577ba Final polish on machine pass registries. by Jim Laskey · 18 years ago
9ff542f 1. Change use of "Cache" to "Default". by Jim Laskey · 18 years ago
13ec702 Introducing plugable register allocators and instruction schedulers. by Jim Laskey · 18 years ago
60f0992 Use an enumeration to eliminate data relocations. by Jim Laskey · 18 years ago
9525528 Use hidden visibility to make symbols in an anonymous namespace get by Chris Lattner · 18 years ago
f8c68f6 Shave another 27K off libllvmgcc.dylib with visibility hidden by Chris Lattner · 18 years ago
6b8e5a9 Make sure the register pressure reduction schedulers work for non-uniform by Evan Cheng · 18 years ago
3b78823 Turn on -sched-commute-nodes by default. by Evan Cheng · 18 years ago
8820ad5 Fixing 2006-05-01-SchedCausingSpills.ll; some clean up by Evan Cheng · 18 years ago
07000c6 Refactor a bunch of includes so that TargetMachine.h doesn't have to include by Owen Anderson · 18 years ago
13d41b9 Add capability to scheduler to commute nodes for profit. by Evan Cheng · 18 years ago
e165a78 Refactor scheduler code. Move register-reduction list scheduler to a by Evan Cheng · 18 years ago