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gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / lib / Target / ARM / ARMInstrInfo.h
  1. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  2. a4c7910 Fix a misnamed parameter. by Christopher Lamb · 17 years ago
  3. 8c13263 Instruction formats added used to generate multiply instructions of V5TE. by Raul Herbster · 17 years ago
  4. 0ff94f7 Initial JIT support for ARM by Raul Fernandes Herbster. by Evan Cheng · 17 years ago
  5. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 17 years ago
  6. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  7. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
  8. eaa91b0 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 17 years ago
  9. d42e56e Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. by Evan Cheng · 17 years ago
  10. 62ccdbf Add missing const qualifiers. by Evan Cheng · 17 years ago
  11. 69d5556 Hooks for predication support. by Evan Cheng · 17 years ago
  12. 6ae3626 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. by Evan Cheng · 17 years ago
  13. 02c602b PredicateInstruction returns true if the operation was successful. by Evan Cheng · 17 years ago
  14. b5f8eff Removed isPredicable(). by Evan Cheng · 17 years ago
  15. 9307292 Hooks for predication support. by Evan Cheng · 17 years ago
  16. 29836c3 Factor GetInstSize() out of constpool island pass. by Evan Cheng · 18 years ago
  17. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
  18. a8e2989 ARM backend contribution from Apple. by Evan Cheng · 18 years ago
  19. 578e64a implement uncond branch insertion, mark branches with isBranch. by Chris Lattner · 18 years ago
  20. 46adf81 change the addressing mode of the str instruction to reg+imm by Rafael Espindola · 18 years ago
  21. aefe142 create the raddr addressing mode that matches any register and the frame index by Rafael Espindola · 18 years ago
  22. 7bc59bc added a skeleton of the ARM backend by Rafael Espindola · 18 years ago