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gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / lib / Target / ARM / ARMInstrInfo.td
  1. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  2. 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
  3. c69107c Unifacalize the CALLSEQ{START,END} stuff. by Bill Wendling · 17 years ago
  4. 0f8d9c0 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack by Bill Wendling · 17 years ago
  5. 20ab290 Add a flag for indirect branch instructions. by Owen Anderson · 17 years ago
  6. 071a279 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. by Evan Cheng · 17 years ago
  7. be36798 80 col. by Evan Cheng · 17 years ago
  8. 37fb5b1 ARM instruction table was modified by adding information to generate multiply instruction of V5TE. by Raul Herbster · 17 years ago
  9. 0ff94f7 Initial JIT support for ARM by Raul Fernandes Herbster. by Evan Cheng · 17 years ago
  10. 7fc7761 Indexed loads each has 2 outputs. by Evan Cheng · 17 years ago
  11. ffbacca No more noResults. by Evan Cheng · 17 years ago
  12. 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
  13. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 17 years ago
  14. 9ad6f03 No need for ccop anymore. by Evan Cheng · 17 years ago
  15. 06aae67 Do away with ImmutablePredicateOperand. by Evan Cheng · 17 years ago
  16. 04c813d PredicateDefOperand -> OptionalDefOperand. by Evan Cheng · 17 years ago
  17. d54874a Unbreak the build. by Evan Cheng · 17 years ago
  18. c85e832 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. by Evan Cheng · 17 years ago
  19. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  20. 0819a9d Fix the build. by Owen Anderson · 17 years ago
  21. 277f074 Allow predicated immediate ARM to ARM calls. by Evan Cheng · 17 years ago
  22. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
  23. eaa91b0 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 17 years ago
  24. 2c614c5 Mark these instructions clobbersPred. They modify the condition code register. by Evan Cheng · 17 years ago
  25. c354334 Opcode modifier s comes after condition code. e.g. addlts, not addslt. by Evan Cheng · 17 years ago
  26. df4da14 Make jumptable non-predicable for now. by Evan Cheng · 17 years ago
  27. fd488ed For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. by Evan Cheng · 17 years ago
  28. f23b8cf Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. by Dale Johannesen · 17 years ago
  29. 86d4069 Add some patterns for PIC PC-relative loads and stores. by Dale Johannesen · 17 years ago
  30. dcc50a4 Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. by Evan Cheng · 17 years ago
  31. 5ada199 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. by Evan Cheng · 17 years ago
  32. aeafca0 Conditional branch is not a barrier. by Evan Cheng · 17 years ago
  33. 44bec52 Add PredicateOperand to all ARM instructions that have the condition field. by Evan Cheng · 17 years ago
  34. 42d712b Switch BCC, MOVCCr, etc. to PredicateOperand. by Evan Cheng · 17 years ago
  35. caa8055 change per review by Dale Johannesen · 17 years ago
  36. 25c1f9e Prevent Thumb code from generating ARM instructions by Dale Johannesen · 17 years ago
  37. 64f4fa5 ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. by Lauro Ramos Venancio · 17 years ago
  38. 120fba9 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll by Chris Lattner · 17 years ago
  39. 9996663 - Divides the comparisons in two types: comparisons that only use N and Z by Lauro Ramos Venancio · 17 years ago
  40. b8a93a4 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. by Lauro Ramos Venancio · 17 years ago
  41. 64c88d7 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: by Lauro Ramos Venancio · 17 years ago
  42. c70d184 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. by Evan Cheng · 17 years ago
  43. 9f6636f Fix naming inconsistencies. by Evan Cheng · 17 years ago
  44. fa775d0 Special LDR instructions to load from non-pc-relative constantpools. These are by Evan Cheng · 17 years ago
  45. a251570 Constant generation instructions are re-materializable. by Evan Cheng · 17 years ago
  46. b38cba9 ARM callseq_end should have a input flag operand so it would be scheduled right after the call. by Evan Cheng · 18 years ago
  47. c60e76d - Fix codegen for pc relative constant (e.g. JT) in thumb mode: by Evan Cheng · 18 years ago
  48. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
  49. 34b12d2 Code clean up. Use def : pat instead of defining new instructions. by Evan Cheng · 18 years ago
  50. a8e2989 ARM backend contribution from Apple. by Evan Cheng · 18 years ago
  51. 9985f9f implement missing compares patch by Lauro bug fixed by me by Rafael Espindola · 18 years ago
  52. 301009a Implement SELECT_CC (f32/f64) for ARM. by Lauro Ramos Venancio · 18 years ago
  53. 6547c55 remove duplicated line bug noticed by Lauro by Rafael Espindola · 18 years ago
  54. a8f9f4a This patch defines extloadi1 and fixes an internal compiler error on arm. by Lauro Ramos Venancio · 18 years ago
  55. a898ce6 more general matching of the MVN instruction by Rafael Espindola · 18 years ago
  56. f64945d use MVN to handle small negative constants by Rafael Espindola · 18 years ago
  57. 450856d add mvn by Rafael Espindola · 18 years ago
  58. a43f3d4 fix truncstorei1 by Rafael Espindola · 18 years ago
  59. f819a49 implement load effective address similar to the alpha backend by Rafael Espindola · 18 years ago
  60. 6e8c649 initial implementation of addressing mode 2 TODO: fix lea_addri by Rafael Espindola · 18 years ago
  61. 3751844 remove dead/redundant vars by Chris Lattner · 18 years ago
  62. 9dca7ad implement zextload bool and truncstore bool by Rafael Espindola · 18 years ago
  63. 578e64a implement uncond branch insertion, mark branches with isBranch. by Chris Lattner · 18 years ago
  64. c391d16 implement STRB and STRH by Rafael Espindola · 18 years ago
  65. 2435786 use Pat to implement extloadi8 and extloadi16 by Rafael Espindola · 18 years ago
  66. 2079311 implement undef by Rafael Espindola · 18 years ago
  67. 3692c7a implement extloadi8 and extloadi16 by Rafael Espindola · 18 years ago
  68. 71d94d8 add blx by Rafael Espindola · 18 years ago
  69. 70673a1 add isTerminatortto b and bcond by Rafael Espindola · 18 years ago
  70. 04d88ff add the FPUnaryOp and DFPUnaryOp classes by Rafael Espindola · 18 years ago
  71. c01c87c add FABSS and FABSD by Rafael Espindola · 18 years ago
  72. 3f3a6f6 remove extra [] in stores by Rafael Espindola · 18 years ago
  73. 32bd5f4 initial implementation of addressing mode 5 by Rafael Espindola · 18 years ago
  74. f621abc add FSTD and FSTS by Rafael Espindola · 18 years ago
  75. 199dd67 add FCPYS and FCPYD by Rafael Espindola · 18 years ago
  76. a605be6 add fdivs e fdivd by Rafael Espindola · 18 years ago
  77. 0505be0 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS by Rafael Espindola · 18 years ago
  78. 27e469e define the DFPBinOp class by Rafael Espindola · 18 years ago
  79. a6f149d add the FPBinOp class by Rafael Espindola · 18 years ago
  80. 90057aa define the Addr1BinOp class by Rafael Espindola · 18 years ago
  81. 15a6c3e define the IntBinOp class and use it to implement the multiply instructions by Rafael Espindola · 18 years ago
  82. bb1e2fb fix assembly syntax by Rafael Espindola · 18 years ago
  83. 82c678b implement LDRB, LDRSB, LDRH and LDRSH by Rafael Espindola · 18 years ago
  84. bec2e38 implement smull and umull by Rafael Espindola · 18 years ago
  85. 6c5ae3e fix some fp condition codes use non trapping comparison instructions by Rafael Espindola · 18 years ago
  86. 33d06bc add FNEGS and FNEGD by Rafael Espindola · 18 years ago
  87. 5395538 add SBCS and SUBS by Rafael Espindola · 18 years ago
  88. 42b62f3 implement unordered floating point compares by Rafael Espindola · 18 years ago
  89. 65d8c1e mark call adjustments as modifying the SP by Chris Lattner · 18 years ago
  90. af9db75 Add properties to ComplexPattern. by Evan Cheng · 18 years ago
  91. 493a7fc uint <-> double conversion by Rafael Espindola · 18 years ago
  92. 667c349 add fp sub by Rafael Espindola · 18 years ago
  93. b47e1d0 add double <-> int conversion by Rafael Espindola · 18 years ago
  94. 0d9fe76 compare doubles by Rafael Espindola · 18 years ago
  95. 4b20fbc initial support for fp compares. Unordered compares not implemented yet by Rafael Espindola · 18 years ago
  96. 2dc0f2b add float -> double and double -> float conversion by Rafael Espindola · 18 years ago
  97. ecdb9f9 add ADDS and ADCS by Rafael Espindola · 18 years ago
  98. e5bbd6d implement FUITOS and FUITOD by Rafael Espindola · 18 years ago
  99. 5aca927 implement FLDD by Rafael Espindola · 18 years ago
  100. d9ae778 implement fadds, faddd, fmuls and fmuld by Rafael Espindola · 18 years ago