- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- ffbacca No more noResults. by Evan Cheng · 17 years ago
- 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
- 15b7823 Use this nifty Constraints thing and fix the inverted conditional moves by Andrew Lenharth · 17 years ago
- f81173f Add all that branch mangling niftiness by Andrew Lenharth · 18 years ago
- f2b806a Let the alpha breakage begin. First Formals and RET. next Calls by Andrew Lenharth · 18 years ago
- 017c556 Alpha Scheduling classes by Andrew Lenharth · 18 years ago
- 77f0885 Add immediate forms of cmov and remove some cruft by Andrew Lenharth · 19 years ago
- 9e23485 minor renaming by Andrew Lenharth · 19 years ago
- cd1544e allow R28 to be used for frame calculations without entirely removing it from circulation by Andrew Lenharth · 19 years ago
- 739027e stack and rpcc by Andrew Lenharth · 19 years ago
- feab2f8 Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. by Andrew Lenharth · 19 years ago
- eececba add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG by Andrew Lenharth · 19 years ago
- b671860 Unify the patterns for loads and stores. Now offset addressing should be by Andrew Lenharth · 19 years ago
- 9fa4d4c move loads and stores over. Smart addr selection comming by Andrew Lenharth · 19 years ago
- cfb2815 OK, this does wonders for broken stuff by Andrew Lenharth · 19 years ago
- eda80a0 added instructions with inverted immediates by Andrew Lenharth · 19 years ago
- 5de36f9 These never trigger, but whatever by Andrew Lenharth · 19 years ago
- 7f0db91 All sorts of stuff. by Andrew Lenharth · 19 years ago
- 50b3784 massive DAGISel patch. lots and lots more stuff compiles now by Andrew Lenharth · 19 years ago
- 51b8d54 continued readcyclecounter support by Andrew Lenharth · 19 years ago
- 5cefc5e whatever. Intermediate patch to see what breaks. Seems ok. by Andrew Lenharth · 19 years ago
- 641b64a Simplify instinfo, set random bits on more fp insts, and fix 1 opcode by Andrew Lenharth · 19 years ago
- 756fbeb Well, the Constant matching pattern works. Can't say much about calls or globals yet. by Andrew Lenharth · 19 years ago
- 1f347a3 Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight by Andrew Lenharth · 19 years ago
- 964b6aa added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh by Andrew Lenharth · 19 years ago
- 4907d22 ret 0; works, not much else by Andrew Lenharth · 19 years ago
- 98169be support bsr, and more .td simplification by Andrew Lenharth · 19 years ago
- f3f951a simpilfy instruction encoding (and make the lines way shorter, aka Misha happification) by Andrew Lenharth · 19 years ago
- 2a8350a Make the rest of file header comments consistent in format and style by Misha Brukman · 20 years ago
- 3e98fde initial fp support by Andrew Lenharth · 20 years ago
- 2d6f022 Clean ups, and taught the instruction selector about immediate forms by Andrew Lenharth · 20 years ago
- 304d0f3 Let me introduce you to the early stages of the llvm backend for the alpha processor by Andrew Lenharth · 20 years ago