- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
- ffbacca No more noResults. by Evan Cheng · 17 years ago
- 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
- 0d75f57 implement anyextend from i1 -> i64 by Chris Lattner · 17 years ago
- f525eb9 fix storing bools to mem and unordered FP ops by Duraid Madina · 18 years ago
- ca32028 Remove a duplicate pattern. by Evan Cheng · 18 years ago
- 1ffd41a doo de doo by Duraid Madina · 18 years ago
- 631a140 by Duraid Madina · 19 years ago
- cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
- d92f116 some hoovering by Duraid Madina · 19 years ago
- badf0d9 by Duraid Madina · 19 years ago
- bea9947 by Duraid Madina · 19 years ago
- a7fb5be by Duraid Madina · 19 years ago
- 12f1bea by Duraid Madina · 19 years ago
- 362071d by Duraid Madina · 19 years ago
- 0c81dc8 by Duraid Madina · 19 years ago
- eac2a1b this just might work by Duraid Madina · 19 years ago
- 07ac89f add support for selecting bools by Duraid Madina · 19 years ago
- 2b4ea79 Added field noResults to Instruction. by Evan Cheng · 19 years ago
- 806b893 we don't feed our call instructions extra operands by Duraid Madina · 19 years ago
- 3d821e2 oops, back this out by Duraid Madina · 19 years ago
- 0b3c4d8 we need to emit the getf.d instruction in lowering, so add it to IA64ISD by Duraid Madina · 19 years ago
- a0a11d2 update tablegen files - nothing to see here by Duraid Madina · 19 years ago
- b5d0143 Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. by Chris Lattner · 19 years ago
- 889649e add FP select. next up - divide! by Duraid Madina · 19 years ago
- 49fcc40 fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1) by Duraid Madina · 19 years ago
- 0e5e0d1 add pattern to load constant 0 into a predicate reg by Duraid Madina · 19 years ago
- 61bc60f Fix a bug that prevented this pattern from matching by Chris Lattner · 19 years ago
- cb2583e This works now by Chris Lattner · 19 years ago
- 5966955 add support for SELECT to TargetSelectionDAG.td, add support for by Duraid Madina · 19 years ago
- aba8457 so tablegen was thinking I might want to convert FPs to predicates. by Duraid Madina · 19 years ago
- e2fd9e2 add support for int->FP and FP->int ops, and add ia64 patterns for these by Duraid Madina · 19 years ago
- d1eda6d add zeroextend predicate->integer by Duraid Madina · 19 years ago
- 363aff2 add FP compares and implicit register defs to the dag isel by Duraid Madina · 19 years ago
- 5c2c64e fix some broken comparisons, this affected the Pattern isel too. by Duraid Madina · 19 years ago
- 25d0a88 add some FP stuff, some mix.* stuff, and constant pool support to the by Duraid Madina · 19 years ago
- 274ecfb add shladd by Duraid Madina · 19 years ago
- f2db9b8 DAG->DAG instruction selection for ia64! "hello world" works, not much else. by Duraid Madina · 19 years ago
- 2e3f5db Give all operands names by Chris Lattner · 19 years ago
- efc58be Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. by Chris Lattner · 19 years ago
- 63bbed5 add the popcount instruction and support this in the isel by Duraid Madina · 19 years ago
- 1ce0c01 print negative 64 bit immediates as negative numbers, makes things a little by Duraid Madina · 19 years ago
- ed09502 * add the shladd instruction * fold left shifts of 1, 2, 3 or 4 bits into adds by Duraid Madina · 19 years ago
- ea6f770 Make sure to realize that calls use their argument regs by Chris Lattner · 19 years ago
- 5ef2ec9 assorted fixes: by Duraid Madina · 19 years ago
- 6dcceb5 fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn) by Duraid Madina · 19 years ago
- 18c0c6b add immediate forms of add, sub, shift by Duraid Madina · 19 years ago
- b366a02 add fms instruction by Duraid Madina · 19 years ago
- 09c61b9 add implicit use op by Duraid Madina · 19 years ago
- 5c156b7 add fnegabs op by Duraid Madina · 19 years ago
- a7ee8b8 add support FNEG and FABS by Duraid Madina · 19 years ago
- 291e126 add what we need to fudge a 'floating point conditional move', this is by Duraid Madina · 19 years ago
- 9b9d45f and so it begins... by Duraid Madina · 19 years ago