- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- f191c80 Use TableGen to emit information for dwarf register numbers. by Anton Korobeynikov · 17 years ago
- 03494d7 Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. by Evan Cheng · 17 years ago
- 5ea64fd Constify some methods. Patch provided by Anton Vayvod, thanks! by Chris Lattner · 18 years ago
- ff70fe6 D'oh - should be even numbered. by Jim Laskey · 18 years ago
- 47622e3 Add dwarf register numbering to register data. by Jim Laskey · 18 years ago
- f613fcb Update to new-style flags usage, simplifying the .td file by Chris Lattner · 19 years ago
- 7c90f73 Rename SPARC V8 target to be the LLVM SPARC target. by Chris Lattner · 19 years ago
- 85e42b4 Reserve G1 for frame offset stuff and use it to handle large stack frames. by Chris Lattner · 19 years ago
- 8ba0423 Elimiante SP and FP, which weren't members of the IntRegs register class by Chris Lattner · 19 years ago
- 4d55aca Add initial conditional branch support. This doesn't actually work yet due by Chris Lattner · 19 years ago
- 37949f5 Add patterns for multiply, simplify Y register handling stuff, add RDY instruction by Chris Lattner · 19 years ago
- 6510b22 Support multiple ValueTypes per RegisterClass, needed for upcoming vector by Nate Begeman · 19 years ago
- ecbce61 Split RegisterClass 'Methods' into MethodProtos and MethodBodies by Chris Lattner · 19 years ago
- 28e728d put reg classes in namespaces by Chris Lattner · 19 years ago
- 8fe429d Make this file self-contained. by Brian Gaeke · 20 years ago
- 4b92ed6 Allocate fewer registers and tighten up alignment restrictions. by Brian Gaeke · 20 years ago
- f90a656 SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned! by Misha Brukman · 20 years ago
- c6e7430 Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64. by Misha Brukman · 20 years ago
- c95759c Use the V8/V9 shared register file description by Misha Brukman · 20 years ago
- 1002013 Changes to make this work with Jason's patch. I checked this by hand, but by Chris Lattner · 20 years ago
- 0e36277 Convert bytes to bits in alignment by Chris Lattner · 20 years ago
- 60c73e4 Make the double-fp pseudo registers be "NamedRegs". by Brian Gaeke · 20 years ago
- be81e82 The long integer pseudo-regs are history. So long, we hardly knew ye. by Brian Gaeke · 20 years ago
- f54d912 Add pseudo-registers and register class for 64-bit integer values. by Brian Gaeke · 20 years ago
- 4f217fd Mess around with allocation order. In particular, I think we ought to be by Brian Gaeke · 20 years ago
- f97b31e Merge my changes with brians by Chris Lattner · 20 years ago
- 59e04e4 Add support for the "Y" register, used by MUL & DIV. by Brian Gaeke · 20 years ago
- 9b3c702 Avoid allocating special registers a bit more robustly by Chris Lattner · 20 years ago
- bda4a3c Hack it so we do not try to allocate values to G0. by Brian Gaeke · 20 years ago
- da69e7d Double-FP pseudo-registers. by Brian Gaeke · 20 years ago
- e7173b7 Floating point regs by Brian Gaeke · 20 years ago
- e1274de Implement initial prolog/epilog code insertion methods. by Chris Lattner · 20 years ago
- 1c809c5 Add an instruction selector capable of selecting 'ret void' by Chris Lattner · 20 years ago
- a85d46e Tab completion is our friend. by Chris Lattner · 20 years ago[Renamed from lib/Target/Sparc/SparcV8Reg.td]
- 757df02 SparcV8 regs are really 32-bit, not 64! Thanks, Chris. by Misha Brukman · 20 years ago
- 5914bf6 Fix the SparcV8 register definitions that were imported from PPC template. by Misha Brukman · 20 years ago
- e785e53 SparcV8 skeleton by Brian Gaeke · 20 years ago