Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / lib / Target / Target.td
  1. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  2. 7d9e97c As per feedback, revised comments to (hopefully) make the different side effect by Bill Wendling · 17 years ago
  3. 6b1da9c Add flags to indicate that there are "never" side effects or that there "may be" by Bill Wendling · 17 years ago
  4. 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
  5. 20ab290 Add a flag for indirect branch instructions. by Owen Anderson · 17 years ago
  6. 2e7eedf Clarify the meaning of '-2' register number by Anton Korobeynikov · 17 years ago
  7. f191c80 Use TableGen to emit information for dwarf register numbers. by Anton Korobeynikov · 17 years ago
  8. a3ca314 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value by Evan Cheng · 17 years ago
  9. 071a279 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. by Evan Cheng · 17 years ago
  10. 08d5207 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 by Christopher Lamb · 17 years ago
  11. ffbacca No more noResults. by Evan Cheng · 17 years ago
  12. 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
  13. 2bf821c Remove clobbersPred. by Evan Cheng · 17 years ago
  14. 49ce02e Do away with ImmutablePredicateOperand. by Evan Cheng · 17 years ago
  15. e496d78 Add OptionalDefOperand to stand for optionally defined result. by Evan Cheng · 17 years ago
  16. 2aa133e - Added zero_reg def to stand for register 0. by Evan Cheng · 17 years ago
  17. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  18. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
  19. eaa91b0 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 17 years ago
  20. a321125 Add support to tablegen for specifying subregister classes on a per register class basis. by Christopher Lamb · 17 years ago
  21. c1d7384 Added clobbersPred. by Evan Cheng · 17 years ago
  22. 064d7cd Added isPredicable bit to class Instruction. by Evan Cheng · 17 years ago
  23. f88b3a5 PredicateOperand can be used as a normal operand for isel. by Evan Cheng · 17 years ago
  24. 4222d80 Add an "implies" field to features. This indicates that, if the current by Bill Wendling · 17 years ago
  25. a7ad3d1 expose HonorSignDependentRoundingFPMathOption to .td files by Chris Lattner · 17 years ago
  26. 7bf1c27 llvm bug #1350, parts 1, 2, and 3. by Nate Begeman · 17 years ago
  27. 3cafbf7 Add sub-registers sets. by Evan Cheng · 17 years ago
  28. e2e9e44 Added isReMaterializable. by Evan Cheng · 17 years ago
  29. d637a8b Add calling convention info by Chris Lattner · 17 years ago
  30. e26bff2 Fix typos in comments. by Dan Gohman · 17 years ago
  31. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
  32. e77d10d Comment. by Evan Cheng · 18 years ago
  33. fa326c7 add a new field needed by the code emitter generator. by Chris Lattner · 18 years ago
  34. 60a09a5 initial steps to getting the predicate on PPC::BLR right. by Chris Lattner · 18 years ago
  35. e69c436 remove dead var by Chris Lattner · 18 years ago
  36. 2f15c06 Add constraints to Instruction class. by Evan Cheng · 18 years ago
  37. 33e4869 Move the Imp tblgen class from the X86 backend to common code. by Chris Lattner · 18 years ago
  38. e6f3203 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. by Evan Cheng · 18 years ago
  39. ffd4364 Added a Flags field to TargetOperandInfo. Currently the only flag is by Evan Cheng · 18 years ago
  40. 0cfd73a Remove CalleeSavedRegisters from class Target. by Evan Cheng · 18 years ago
  41. c01d497 Remove PointerType from class Target by Evan Cheng · 18 years ago
  42. e438c2a Replace "../whatever.td" with "whatever.td", so that out-of-tree backends by Vladimir Prus · 18 years ago
  43. 94ae9d3 Improve comment, patch provided by Vladimir Prus! by Chris Lattner · 18 years ago
  44. 506efda Update comment. by Chris Lattner · 18 years ago
  45. de321a8 Put PHI/INLINEASM into the correct namespace. by Chris Lattner · 18 years ago
  46. f5e1dc2 Renamed AddedCost to AddedComplexity. by Evan Cheng · 18 years ago
  47. 5941320 Allow "let AddedCost = n in" to increase pattern complexity. by Evan Cheng · 18 years ago
  48. 8da17b2 Add support for dwarf register numbering. by Jim Laskey · 18 years ago
  49. da10f19 Shuffle some includes around by Chris Lattner · 18 years ago
  50. a8309ae Split the valuetypes out of Target.td into ValueTypes.td by Chris Lattner · 18 years ago
  51. f338dd8 New type v2f32. by Evan Cheng · 18 years ago
  52. aea20f5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit by Evan Cheng · 18 years ago
  53. 19c9550 Subtarget feature can now set any variable to any value by Evan Cheng · 19 years ago
  54. cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
  55. 6da8d99 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace by Evan Cheng · 19 years ago
  56. 2b4ea79 Added field noResults to Instruction. by Evan Cheng · 19 years ago
  57. 171049d * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. by Evan Cheng · 19 years ago
  58. 58e84a6 Added support to specify predicates. by Evan Cheng · 19 years ago
  59. f8ac814 * Added instruction property hasCtrlDep for those which r/w control-flow by Evan Cheng · 19 years ago
  60. 6510b22 Support multiple ValueTypes per RegisterClass, needed for upcoming vector by Nate Begeman · 19 years ago
  61. 6a64861 Add the majority of the vector machien value types we expect to support, by Nate Begeman · 19 years ago
  62. eedf3b5 refix typo by Chris Lattner · 19 years ago
  63. 46ec786 revert my change for the time being, which broke the build by Chris Lattner · 19 years ago
  64. 0ba7d71 fix a typo :) by Chris Lattner · 19 years ago
  65. be7a2ff Capture more operand info, patch by Evan Cheng by Chris Lattner · 19 years ago
  66. 69a2cf4 Also add the new vector value type here, for completeness. by Nate Begeman · 19 years ago
  67. f0c2be4 Add attribute name and type to SubtargetFeatures. by Jim Laskey · 19 years ago
  68. f5fc2cb Plugin new subtarget backend into the build. by Jim Laskey · 19 years ago
  69. 5384214 Added InstrSchedClass to each of the PowerPC Instructions. by Jim Laskey · 19 years ago
  70. 0de8796 Push processor descriptions to the top of target and add command line info. by Jim Laskey · 19 years ago
  71. 17f2cf0 Pull DAG ISel generation nodes out of the PowerPC backend to where they by Chris Lattner · 19 years ago
  72. ccc8ed7 Add a forward def by Chris Lattner · 19 years ago
  73. ef242b1 Now that self referential classes are supported, get rid of a work-around. by Chris Lattner · 19 years ago
  74. e3cbf82 spell this right by Chris Lattner · 19 years ago
  75. 0efa0f9 Add a flag by Chris Lattner · 19 years ago
  76. a64d4cd add an enum value by Chris Lattner · 19 years ago
  77. ecbce61 Split RegisterClass 'Methods' into MethodProtos and MethodBodies by Chris Lattner · 19 years ago
  78. 1ff9540 Require that targets specify a namespace for their register classes. by Chris Lattner · 19 years ago
  79. 329cdc3 Add a new flag by Chris Lattner · 19 years ago
  80. 273f228 Add some bits that can be set for instructions. by Chris Lattner · 20 years ago
  81. 99ee67a Add isLittleEndianEncoding to InstrInfo class, defaults to `off' by Misha Brukman · 20 years ago
  82. 0fa2066 Add initial support for variants by Chris Lattner · 20 years ago
  83. 8d5c503 Add support for the isLoad and isStore flags, needed by the instruction scheduler by Nate Begeman · 20 years ago
  84. 7baaf09 Capture delay slot info by Chris Lattner · 20 years ago
  85. b228657 Revamp the Register class, and allow the use of the RegisterGroup class to by Chris Lattner · 20 years ago
  86. b4d83c1 Add two values by Chris Lattner · 20 years ago
  87. dd43e34 isdummyclass goes away by Chris Lattner · 20 years ago
  88. 9222cde disable all of the pattern isel stuff by Chris Lattner · 20 years ago
  89. fa14683 Add i1imm by Chris Lattner · 20 years ago
  90. 175580c Make the AsmWriter a first-class tblgen object. Allow targets to specify by Chris Lattner · 20 years ago
  91. 52d2f14 Fill out immediate operand classes, add a new Operand class by Chris Lattner · 20 years ago
  92. 8124020 Remove ClassPrefix variable as it's no longer used. by Misha Brukman · 20 years ago
  93. 665235b Classes need to have a prefix name, so that they can be tacked on to the pieces by Misha Brukman · 20 years ago
  94. 33c23dd Add some immediate forms, make name optional by Chris Lattner · 20 years ago
  95. c139203 Add the 'ops' marker, add an AsmString initializer by Chris Lattner · 20 years ago
  96. bbe664c Move the 'Expander' node to later in the file, with the other experimental by Chris Lattner · 20 years ago
  97. 2a809f6 New flag by Chris Lattner · 20 years ago
  98. 6565043 Expose the "Other" value type to tablegen targets by Chris Lattner · 21 years ago
  99. 856ba76 Added LLVM copyright header. by John Criswell · 21 years ago
  100. b6ef5c8 Add a bunch of new node types, including a new Void dummy register class by Chris Lattner · 21 years ago