- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 48abc5c Corrected many typing errors. And removed 'nest' parameter handling by Arnold Schwaighofer · 17 years ago
- cd6cea0 We only need to specify the most-implied feature for an architecture. by Bill Wendling · 17 years ago
- 11d8fda 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. by Bill Wendling · 17 years ago
- 4222d80 Add an "implies" field to features. This indicates that, if the current by Bill Wendling · 17 years ago
- 3f3a17d Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers by Bill Wendling · 17 years ago
- bb1ee05 Add support for our first SSSE3 instruction "pmulhrsw". by Bill Wendling · 17 years ago
- 31c8a6d Add a description of the X86-64 calling convention and the return by Chris Lattner · 17 years ago
- a26eb5e Still need to support -mcpu=<> or cross compilation will fail. Doh. by Evan Cheng · 18 years ago
- abc346c Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support. by Evan Cheng · 18 years ago
- 25ab690 Committing X86-64 support. by Evan Cheng · 18 years ago
- 751458d ImmMask should be 3 for a two-bit field; Compact X86II by Evan Cheng · 18 years ago
- 0f3ac8d getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. by Evan Cheng · 18 years ago
- c01d497 Remove PointerType from class Target by Evan Cheng · 18 years ago
- 3c55c54 - Use xor to clear integer registers (set R, 0). by Evan Cheng · 19 years ago
- 259e97c * Fix 80-column violations by Chris Lattner · 19 years ago
- b8643ac Fix typo. by Jeff Cohen · 19 years ago
- 559806f x86 CPU detection and proper subtarget support by Evan Cheng · 19 years ago
- cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
- 97c7fc3 Added preliminary x86 subtarget support. by Evan Cheng · 19 years ago
- 16b04f3 Get closer to fully working scalar FP in SSE regs. This gets singlesource by Nate Begeman · 19 years ago
- f63be7d First round of support for doing scalar FP using the SSE2 ISA extension and by Nate Begeman · 19 years ago
- 9a3e49a Add support for the -x86-asm-syntax flag, which can be used to choose between by Chris Lattner · 20 years ago
- c96bb81 Remove a bunch of ad-hoc target-specific flags that were only used by the by Chris Lattner · 20 years ago
- a35ce87 Eliminate 3 of the X86 printImplicit* flags. by Chris Lattner · 20 years ago
- 2665383 Add support for the printImplicitDefsBefore flag by Chris Lattner · 20 years ago
- 4ffff9e Added the llvm.readport and llvm.writeport intrinsics for x86. These do by John Criswell · 20 years ago
- 1c54a85 Add FP conditional move instructions, which annoyingly have special properties by Chris Lattner · 20 years ago
- 5ab29b5 Each instruction now has both an ImmType and a MemType. This describes by Alkis Evlogimenos · 20 years ago
- 856ba76 Added LLVM copyright header. by John Criswell · 21 years ago
- 2959b6e Completely eliminate the isVoid TSFlag, shifting over all other fields by Chris Lattner · 21 years ago
- e5bb2d9 There is nothing special about noops anymore by Chris Lattner · 21 years ago
- c8f4587 transition to using let instead of set by Chris Lattner · 21 years ago
- 1cca5e3 Add new TableGen instruction definitions by Chris Lattner · 21 years ago
- b77eb78 Add Target class for X86 target by Chris Lattner · 21 years ago
- 762fb5f Initial checkin of X86.td file by Chris Lattner · 21 years ago