- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- 627c00b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I by Bill Wendling · 17 years ago
- 041b3f8 Reverting 44702. It wasn't correct to rename them. by Bill Wendling · 17 years ago
- 320c630 Renaming: by Bill Wendling · 17 years ago
- c85e171 Added tail call optimization to the x86 back end. It can be by Arnold Schwaighofer · 17 years ago
- b76143c Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. by Evan Cheng · 17 years ago
- d47c84c Allow x86 compare to be commutable by default. by Evan Cheng · 17 years ago
- 7ad42d9 Commute x86 cmove instructions by swapping the operands and change the condition by Evan Cheng · 17 years ago
- ecf80ac Enable convertToThreeAddress for X86 by default. by Evan Cheng · 17 years ago
- b75ed32 INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can by Evan Cheng · 17 years ago
- 559dc46 In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. by Evan Cheng · 17 years ago
- b952d1f Add support to convert more 64-bit instructions to 3-address instructions. by Evan Cheng · 17 years ago
- 3f411c7 Testing convertToThreeeAddress as X86 llcbeta. by Evan Cheng · 17 years ago
- e5f6204 Enabling new condition code modeling scheme. by Evan Cheng · 17 years ago
- 0488db9 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after by Evan Cheng · 17 years ago
- a0a7c1d Add 64-bit jmp instructions to the list of instructions that by Dan Gohman · 17 years ago
- e47f1f9 Add patterns for SHLD64* and SHRD64*. by Dan Gohman · 17 years ago
- 24f2ea3 Add implicit def of EFLAGS on those instructions that may modify flags. by Evan Cheng · 17 years ago
- 718cb66 Add lengthof and endof templates that hide a lot of sizeof computations. by Owen Anderson · 17 years ago
- 61d9c86 Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: by Evan Cheng · 17 years ago
- b813371 Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. by Christopher Lamb · 17 years ago
- 85dce6c Don't pollute the meaning of isUnpredicatedTerminator. by Evan Cheng · 17 years ago
- 14c4655 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. by Evan Cheng · 17 years ago
- e377d4d Refactor X87 instructions. As a side effect, all their names are changed. by Dale Johannesen · 17 years ago
- 849f214 Fix for PR 1505 (and 1489). Rewrite X87 register by Dale Johannesen · 17 years ago
- d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
- 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
- 318093b Do not treat FP_REG_KILL as terminator in branch analysis (X86). by Dale Johannesen · 17 years ago
- c101e95 Add a target hook to allow loads from constant pools to be rematerialized, and an by Dan Gohman · 17 years ago
- 13e8b51 Handle blocks with 2 unconditional branches in AnalyzeBranch. by Dale Johannesen · 17 years ago
- bfd2ec4 Add a utility routine to check for unpredicated terminator instruction. by Evan Cheng · 17 years ago
- 126f17a BlockHasNoFallThrough() now returns true if block ends with a return instruction. by Evan Cheng · 17 years ago
- 6ae3626 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. by Evan Cheng · 17 years ago
- 1e341729 Relex assertions to account for additional implicit def / use operands. by Evan Cheng · 17 years ago
- 6dd29e0 Remove some invalid instructions from this check. by Bill Wendling · 17 years ago
- 71bfd11 Adding more MMX instructions. by Bill Wendling · 17 years ago
- 823efee Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. by Bill Wendling · 17 years ago
- 995f550 Compile CodeGen/X86/lea-3.ll:test2 to: by Chris Lattner · 17 years ago
- f2177b8 Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the by Chris Lattner · 17 years ago
- a16b7cb Two changes: by Chris Lattner · 17 years ago
- 2f88dcd Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that by Bill Wendling · 17 years ago
- 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
- 258ff67 convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. by Evan Cheng · 18 years ago
- c0f64ff Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead by Evan Cheng · 18 years ago
- e23fc60 Fix a potential bug: MOVPDI2DI, etc. are not copy instructions. by Evan Cheng · 18 years ago
- 6ce7dc2 Properly transfer kill / dead info. by Evan Cheng · 18 years ago
- 7ce4578 Matches MachineInstr changes. by Evan Cheng · 18 years ago
- 6ce6443 fix wonky indentation by Chris Lattner · 18 years ago
- c24ff8e add another target hook for branch folding. by Chris Lattner · 18 years ago
- 9cd6875 Implement support for branch condition reversal. by Chris Lattner · 18 years ago
- 879d09c Simplify code, no functionality change by Chris Lattner · 18 years ago
- 34a84ac allow insertion of a conditional branch with fall-through by Chris Lattner · 18 years ago
- 2a445ad update assert message by Chris Lattner · 18 years ago
- 5860715 bugfix by Chris Lattner · 18 years ago
- 7fbe972 Implement branch analysis/xform hooks required by the branch folding pass. by Chris Lattner · 18 years ago
- ae1dc40 expose DWARF_LABEL opcode# so the branch folder can update debug info properly. by Chris Lattner · 18 years ago
- d77ddbc remove some dead code by Chris Lattner · 18 years ago
- 6458f18 update comments by Chris Lattner · 18 years ago
- 25ab690 Committing X86-64 support. by Evan Cheng · 18 years ago
- 2926869 Fix a long-standing wart in the code generator: two-address instruction lowering by Chris Lattner · 18 years ago
- 5537173 Can't commute shufps. The high / low parts elements come from different vectors. by Evan Cheng · 18 years ago
- efeaed8 Commute shufps / shufpd. by Evan Cheng · 18 years ago
- a0eaf2d Somehow I lost a condition when I was shuffling some code around. Anyway, by Evan Cheng · 18 years ago
- aa3c141 Fix a build breaker. by Evan Cheng · 18 years ago
- 51da42c Oops. PSHUFD is only available with SSE2. by Evan Cheng · 18 years ago
- ccba76b Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. by Evan Cheng · 18 years ago
- 6de0163 These can be transformed into lea as well. Not that we use this feature by Evan Cheng · 18 years ago
- f4df680 Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot by Evan Cheng · 18 years ago
- 403be7e Fixing truncate. Previously we were emitting truncate from r16 to r8 as by Evan Cheng · 18 years ago
- 993c897 Teach the codegen about instructions used for SSE spill code, allowing it by Chris Lattner · 18 years ago
- 11e15b3 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. by Evan Cheng · 18 years ago
- bc4832b Support for scalar to vector with zero extension. by Evan Cheng · 18 years ago
- 82521dd - Remove scalar to vector pseudo ops. They are just wrong. by Evan Cheng · 18 years ago
- fe5cb19 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This by Evan Cheng · 18 years ago
- 1c07e72 fix operand numbers by Chris Lattner · 19 years ago
- 4083960 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) by Chris Lattner · 19 years ago
- bda54cd Tell codegen MOVAPSrr and MOVAPDrr are copies. by Evan Cheng · 19 years ago
- 14e2cf6 Properly split f32 and f64 into separate register classes for scalar sse fp by Nate Begeman · 19 years ago
- 11cefd9 Teach the register allocator that movaps is also a move instruction by Nate Begeman · 19 years ago
- f63be7d First round of support for doing scalar FP using the SSE2 ISA extension and by Nate Begeman · 19 years ago
- 0e0a7a45 * Remove trailing whitespace * Convert tabs to spaces by Misha Brukman · 19 years ago
- a76f048 When commuting these instructions, make sure to actually swap the operands too. by Chris Lattner · 20 years ago
- 0df53d2 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. by Chris Lattner · 20 years ago
- 41e431b Teach the code generator that shrd/shld is commutable if it has an immediate. by Chris Lattner · 20 years ago
- 5aee0b9 Disable 2->3 address promotion of add and inc instructions to LEA's. In by Chris Lattner · 20 years ago
- bcea4d6 Implement the convertToThreeAddress method, add support for inverting JP/JNP by Chris Lattner · 20 years ago
- bcdda01 Fix a warning by Chris Lattner · 20 years ago
- 31e155e Align breaks. by Alkis Evlogimenos · 20 years ago
- 167cf33 Add breaks by Chris Lattner · 20 years ago
- 6103c17 Simplify code a bit. by Alkis Evlogimenos · 20 years ago
- 02a4530 Correctly spell 'unconditional'. by Alkis Evlogimenos · 20 years ago
- 36f506e Implement insertGoto and reverseBranchCondition for the X86. by Alkis Evlogimenos · 20 years ago
- 8295f20 A big X86 instruction rename. The instructions are renamed to make by Alkis Evlogimenos · 20 years ago
- dce363d Adjust to change in TII ctor arguments by Chris Lattner · 20 years ago
- 1ddf475 These two virtual methods are never called. by Chris Lattner · 20 years ago
- 890f923 Move MOTy::UseType enum into MachineOperand. This eliminates the by Alkis Evlogimenos · 20 years ago
- be766c7 Remove getAllocatedRegNum(). Use getReg() instead. by Alkis Evlogimenos · 21 years ago
- 6d21518 Don't use MachineOperator::is(Phys|Virt)Register by Chris Lattner · 21 years ago
- 0bbf305 Tighten up checks by Chris Lattner · 21 years ago
- a1b6f95 FpMOV is also a move instruction. by Alkis Evlogimenos · 21 years ago