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gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / lib / Target / X86 / X86InstrInfo.td
  1. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  2. f02ca69 Fix JIT code emission of X86::MovePCtoStack. by Evan Cheng · 17 years ago
  3. 627c00b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I by Bill Wendling · 17 years ago
  4. fd9e473 Fix bsf / bsr jit encoding. by Evan Cheng · 17 years ago
  5. 1a8001e Fix Intel asm syntax for the bsr and bsf instructions. by Dan Gohman · 17 years ago
  6. 152804e Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero. by Evan Cheng · 17 years ago
  7. 18efe26 Implement ctlz and cttz with bsr and bsf. by Evan Cheng · 17 years ago
  8. 1314b00 Fold some and + shift in x86 addressing mode. by Evan Cheng · 17 years ago
  9. 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
  10. c69107c Unifacalize the CALLSEQ{START,END} stuff. by Bill Wendling · 17 years ago
  11. 0f8d9c0 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack by Bill Wendling · 17 years ago
  12. 20ab290 Add a flag for indirect branch instructions. by Owen Anderson · 17 years ago
  13. 66f7163 Local spiller optimization: by Evan Cheng · 17 years ago
  14. 48abc5c Corrected many typing errors. And removed 'nest' parameter handling by Arnold Schwaighofer · 17 years ago
  15. c85e171 Added tail call optimization to the x86 back end. It can be by Arnold Schwaighofer · 17 years ago
  16. 7ad42d9 Commute x86 cmove instructions by swapping the operands and change the condition by Evan Cheng · 17 years ago
  17. 3154cb6 ADC and SBB uses EFLAGS. by Evan Cheng · 17 years ago
  18. e5f6204 Enabling new condition code modeling scheme. by Evan Cheng · 17 years ago
  19. fa00feb Stop inventing new words. :-) by Evan Cheng · 17 years ago
  20. 8decf6b Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS. by Evan Cheng · 17 years ago
  21. bf4f89d Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. by Evan Cheng · 17 years ago
  22. 8d5562b Typos: POPQ -> POPFQ, POPD -> POPFD. by Evan Cheng · 17 years ago
  23. 2f245ba Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. by Evan Cheng · 17 years ago
  24. 0488db9 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after by Evan Cheng · 17 years ago
  25. 6b5766e Fix the syntax for the .loc directive in preparation for using it. by Dan Gohman · 17 years ago
  26. f1fc3a8 Fix PR 1681. When X86 target uses +sse -sse2, by Dale Johannesen · 17 years ago
  27. 24f2ea3 Add implicit def of EFLAGS on those instructions that may modify flags. by Evan Cheng · 17 years ago
  28. 071a279 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. by Evan Cheng · 17 years ago
  29. ef61ed3 TableGen no longer emit CopyFromReg nodes for implicit results in physical by Evan Cheng · 17 years ago
  30. 1ab7989 Avoid storing and reloading zeros and other constants from stack slots by Dan Gohman · 17 years ago
  31. 2f39426 Mark load instructions with isLoad = 1. by Evan Cheng · 17 years ago
  32. 59a5873 Long double patch 4 of N: initial x87 implementation. by Dale Johannesen · 17 years ago
  33. 7afa166 Switch some multiplication instructions over to the new scheme for testing. by Evan Cheng · 17 years ago
  34. f6844ca Mac OS X X86-64 low 4G address not available. by Evan Cheng · 17 years ago
  35. 1c3017c Be more precise. by Evan Cheng · 17 years ago
  36. b1576f5 Change the x86 assembly output to use tab characters to separate the by Dan Gohman · 17 years ago
  37. c64a1a9 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) by Evan Cheng · 17 years ago
  38. 2dc6dc6 Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. by Christopher Lamb · 17 years ago
  39. b6bbe39 In the .loc directive, print the fields as "debug" fields, so they by Dan Gohman · 17 years ago
  40. ffbacca No more noResults. by Evan Cheng · 17 years ago
  41. 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
  42. 2365f51 Long live the exception handling! by Anton Korobeynikov · 17 years ago
  43. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
  44. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago
  45. 9a22530 Reference correct header by Nate Begeman · 17 years ago
  46. 3f3a17d Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers by Bill Wendling · 17 years ago
  47. ede1d78 X86 TLS: optimize the implementation of "local exec" model. by Lauro Ramos Venancio · 17 years ago
  48. 7d2cc2b X86 TLS: fix and optimize the implementation of "initial exec" model. by Lauro Ramos Venancio · 17 years ago
  49. b3a0417 Implement "general dynamic", "initial exec" and "local exec" TLS models for by Lauro Ramos Venancio · 17 years ago
  50. 57fc00d Implemented correct stack probing on mingw/cygwin for dynamic alloca's. by Anton Korobeynikov · 17 years ago
  51. bb1ee05 Add support for our first SSSE3 instruction "pmulhrsw". by Bill Wendling · 17 years ago
  52. 7681435 Mark re-materializable instructions. by Evan Cheng · 17 years ago
  53. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
  54. d06b2ab Fix a misencoding of CBW and CWD. This fixes PR1030. by Chris Lattner · 18 years ago
  55. 28b51439 - Switch X86-64 JIT to large code size model. by Evan Cheng · 18 years ago
  56. 0085a28 - Use a different wrapper node for RIP-relative GV, etc. by Evan Cheng · 18 years ago
  57. 3fa9dff Custom lower READCYCLECOUNTER for x86-64. by Evan Cheng · 18 years ago
  58. 3751844 remove dead/redundant vars by Chris Lattner · 18 years ago
  59. 02b8511 Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4 by Reid Spencer · 18 years ago
  60. 8b2794a Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. by Evan Cheng · 18 years ago
  61. 33e4869 Move the Imp tblgen class from the X86 backend to common code. by Chris Lattner · 18 years ago
  62. f18c074 Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice by Chris Lattner · 18 years ago
  63. af9db75 Add properties to ComplexPattern. by Evan Cheng · 18 years ago
  64. 466685d Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. by Evan Cheng · 18 years ago
  65. f10c17f Delete dead code; fix 80 col violations. by Evan Cheng · 18 years ago
  66. 734503b X86ISD::CMP now produces a chain as well as a flag. Make that the chain by Evan Cheng · 18 years ago
  67. 25ab690 Committing X86-64 support. by Evan Cheng · 18 years ago
  68. ffc0b26 Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns by Chris Lattner · 18 years ago
  69. ec3bc39 Consistency. by Evan Cheng · 18 years ago
  70. bb7b844 CALLSEQ_* produces chain even if that's not needed. by Evan Cheng · 18 years ago
  71. cbac2fa Clean up. by Evan Cheng · 18 years ago
  72. 1693e48 INC / DEC instructions have shorter code size than ADD32ri8, etc. by Evan Cheng · 18 years ago
  73. f7eb5d0 Emit inc / dec of registers as one byte instruction. by Evan Cheng · 18 years ago
  74. 09c5457 Add shift and rotate by 1 instructions / patterns. by Evan Cheng · 18 years ago
  75. 4df24f2 Remove dead code. by Evan Cheng · 18 years ago
  76. fae2994 X86 call instructions can take variable number of operands. Parameters of by Evan Cheng · 18 years ago
  77. 94b1453 Incorrect AT&T opcode. by Evan Cheng · 18 years ago
  78. cbe70e1 Rename ASM modifier trunc8, trunc16 to subreg8, subreg16. by Evan Cheng · 18 years ago
  79. f91c101 Sign extender by Evan Cheng · 18 years ago
  80. e6ad27e A addressing mode folding enhancement: by Evan Cheng · 18 years ago
  81. fb914c4 Remove unused patterns. by Evan Cheng · 18 years ago
  82. 09e3c80 - Use exact-width integer types, e.g. int32_t, to avoid confusion. by Evan Cheng · 18 years ago
  83. fc8feb1 Explicitly specify MOV32mi can only be used store 32-bit GV, etc. by Evan Cheng · 18 years ago
  84. af78ef5 Use generic iPTR instead i32 to represent pointer type. by Evan Cheng · 18 years ago
  85. 069287d X86 integer register classes naming changes. Make them consistent with FP, vector classes. by Evan Cheng · 18 years ago
  86. 403be7e Fixing truncate. Previously we were emitting truncate from r16 to r8 as by Evan Cheng · 18 years ago
  87. 4713724 Need extload patterns after Chris' DAG combiner changes by Evan Cheng · 18 years ago
  88. 8f7f712 Better implementation of truncate. ISel matches it to a pseudo instruction by Evan Cheng · 18 years ago
  89. fea89c1 Make x86 isel lowering produce tailcall nodes. They are match to normal calls by Evan Cheng · 18 years ago
  90. a766765 Optimized stores to the constant pool, while cool, are unnecessary. by Nate Begeman · 18 years ago
  91. 37efe67 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 18 years ago
  92. 11e15b3 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. by Evan Cheng · 18 years ago
  93. 6e16ee5 Added missing (any_extend (load ...)) patterns. by Evan Cheng · 18 years ago
  94. 29b4dd0 Fix the encodings of these new instructions, hopefully fixing the JIT by Chris Lattner · 18 years ago
  95. ce94482 Add support for 8 bit immediates with 16/32 bit cmp instructions by Nate Begeman · 18 years ago
  96. 2246f84 Use the generic vector register classes VR64 / VR128 rather than V4F32, by Evan Cheng · 18 years ago
  97. 06a8aa1 Move some pattern fragments to the right files. by Evan Cheng · 18 years ago
  98. 7f31ad3 - Nuke 16-bit SBB instructions. We'll never use them. - Nuke a bogus comment. by Evan Cheng · 18 years ago
  99. 9925642 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. by Evan Cheng · 18 years ago
  100. 3c992d2 Enable Dwarf debugging info. by Evan Cheng · 18 years ago