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gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / lib / Target / X86 / X86RegisterInfo.cpp
  1. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  2. 7a831ce Make better use of instructions that clear high bits; fix various 2-wide shuffle bugs. by Evan Cheng · 17 years ago
  3. 0c5a507 Actually, MOVPQIto64mr is a dup of MOVPQI2QImr, MOV64toPQIrm is a dup of MOVQI2PQIrm. by Evan Cheng · 17 years ago
  4. 6e041c2 Allow the JIT to encode MMX instructions by Nate Begeman · 17 years ago
  5. d64b5c8 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether by Evan Cheng · 17 years ago
  6. aee4af6 Remove redundant foldMemoryOperand variants and other code clean up. by Evan Cheng · 17 years ago
  7. e62f97c Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0. by Evan Cheng · 17 years ago
  8. c498b02 Clean up sub-register implementation by moving subReg information back to by Evan Cheng · 17 years ago
  9. b97aec6 Add parameter to getDwarfRegNum to permit targets by Dale Johannesen · 17 years ago
  10. e7c8754 Fix x86-64 jit: remove reliance on Dwarf numbers. by Evan Cheng · 17 years ago
  11. f191c80 Use TableGen to emit information for dwarf register numbers. by Anton Korobeynikov · 17 years ago
  12. 7a42f24 Revert previous rewrite per chris's comments. by Dale Johannesen · 17 years ago
  13. 3556bc1 Rewrite Dwarf number handling per review comments. by Dale Johannesen · 17 years ago
  14. 4542edc Complete conditionalization of Dwarf reg numbers. by Dale Johannesen · 17 years ago
  15. 483ec21 Interchange Dwarf numbers of ESP and EBP on x86 Darwin. by Dale Johannesen · 17 years ago
  16. db807ed Use movups to spill / restore SSE registers on targets where stacks alignment is by Evan Cheng · 17 years ago
  17. 8d9d74e Fix off-by-one stack offset computations (dwarf information) for callee-saved by Anton Korobeynikov · 17 years ago
  18. 42b08be Fix an unfolding bug. by Evan Cheng · 17 years ago
  19. f7c9695 Resolve unfold tables ambiguity. by Evan Cheng · 17 years ago
  20. 66f7163 Local spiller optimization: by Evan Cheng · 17 years ago
  21. f0a0cdd - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. by Evan Cheng · 17 years ago
  22. 58184e6 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. by Evan Cheng · 17 years ago
  23. 106e802 Change unfoldMemoryOperand(). User is now responsible for passing in the by Evan Cheng · 17 years ago
  24. f4a9c69 Fold load / store into MOV32to32_ and MOV16to16_. by Evan Cheng · 17 years ago
  25. c85e171 Added tail call optimization to the x86 back end. It can be by Arnold Schwaighofer · 17 years ago
  26. f443ba7 disable this entirely: it is causing use of invalidated iterators and infinite looping. by Chris Lattner · 17 years ago
  27. eac9385 Fix many regressions on x86 by avoiding dereferencing the end iterator. by Chris Lattner · 17 years ago
  28. 2508372 Oops, I really wanted to commit this part also :) by Anton Korobeynikov · 17 years ago
  29. 4f1c33f Move merge code into new helper function. by Anton Korobeynikov · 17 years ago
  30. 75b4e46 Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's. by Evan Cheng · 17 years ago
  31. 7f3394f Refactor code to add load / store folded instructions -> register only by Evan Cheng · 17 years ago
  32. e5f6204 Enabling new condition code modeling scheme. by Evan Cheng · 17 years ago
  33. 8248294 TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets by Dan Gohman · 17 years ago
  34. 3f2d9ec Use GR64 in 64-bit mode. by Evan Cheng · 17 years ago
  35. ff11026 - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). by Evan Cheng · 17 years ago
  36. 9efce63 Allow copyRegToReg to emit cross register classes copies. by Evan Cheng · 17 years ago
  37. 29be848 Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32 by Anton Korobeynikov · 17 years ago
  38. fdd0837 Missing load / store folding entries. by Evan Cheng · 17 years ago
  39. 0488db9 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after by Evan Cheng · 17 years ago
  40. 5e6e93e The code that used the StartLabelId label was removed, so remove the by Dan Gohman · 17 years ago
  41. a4ddacf Fix several more entries in the x86 reload/remat folding tables. by Dan Gohman · 17 years ago
  42. fab7eff PSHUFDmi, etc. are actually folding a load, not a store. by Evan Cheng · 17 years ago
  43. 869b2b2 Move the entries for 64-bit CMP, IMUL, and a few others into the correct by Dan Gohman · 17 years ago
  44. ca8035e Remove RSTRegClass case from loadRegFromStackSlot by Dale Johannesen · 17 years ago
  45. 9e3d3ab Remove the assumption that FP's are either float or by Dale Johannesen · 17 years ago
  46. 92dfe20 Remove isReg, isImm, and isMBB, and change all their users to use by Dan Gohman · 17 years ago
  47. b0869ed It's not safe to rematerialize MOV32r0 etc. by simply cloning the original by Evan Cheng · 17 years ago
  48. 718cb66 Add lengthof and endof templates that hide a lot of sizeof computations. by Owen Anderson · 17 years ago
  49. f4c3a59 Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. by Evan Cheng · 17 years ago
  50. ee46574 Move getX86RegNum into X86RegisterInfo and use it by Duncan Sands · 17 years ago
  51. fcc8793 Make sure epilogue esp adjustment is placed before any terminator and pop instructions. by Evan Cheng · 17 years ago
  52. d97b8cd Heal EH handling stuff by emitting correct offsets to callee-saved registers. by Anton Korobeynikov · 17 years ago
  53. 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
  54. 7e7bbf8 Only adjust esp around calls in presence of alloca. by Evan Cheng · 17 years ago
  55. 3c46eef Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. by Evan Cheng · 17 years ago
  56. 9b8c674 Fold prologue esp update when possible. by Evan Cheng · 17 years ago
  57. 5b3332c Make sure not to break eh_return. by Evan Cheng · 17 years ago
  58. f27795d Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. by Evan Cheng · 17 years ago
  59. 89d1659 Use push / pop for prologues and epilogues. by Evan Cheng · 17 years ago
  60. 2365f51 Long live the exception handling! by Anton Korobeynikov · 17 years ago
  61. 2038252 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, by Dan Gohman · 17 years ago
  62. e377d4d Refactor X87 instructions. As a side effect, all their names are changed. by Dale Johannesen · 17 years ago
  63. 849f214 Fix for PR 1505 (and 1489). Rewrite X87 register by Dale Johannesen · 17 years ago
  64. 0ff3ca4 More DWARF-related things cleanup: by Anton Korobeynikov · 17 years ago
  65. ce3b465 Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux by Anton Korobeynikov · 17 years ago
  66. 038082d Emit correct DWARF reg # for RA (return address) register by Anton Korobeynikov · 17 years ago
  67. 97de913 eliminateFrameIndex() change. by Evan Cheng · 17 years ago
  68. a24dddd Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of add / sub instructions. by Evan Cheng · 17 years ago
  69. 7c6eefa do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292 by Chris Lattner · 17 years ago
  70. ea84c5e support for >4G stack frames by Chris Lattner · 17 years ago
  71. 6180780 support >4G stack frames by Chris Lattner · 17 years ago
  72. b53e98e Add the PADDQ to the list. by Bill Wendling · 17 years ago
  73. d15dff2 rename X86FunctionInfo to X86MachineFunctionInfo to match the header file by Chris Lattner · 17 years ago
  74. 57fc00d Implemented correct stack probing on mingw/cygwin for dynamic alloca's. by Anton Korobeynikov · 17 years ago
  75. c9c9d2d Changed to new MMX_ recipes. by Bill Wendling · 17 years ago
  76. bf2c8b3 Added MRegisterInfo hook to re-materialize an instruction. by Evan Cheng · 17 years ago
  77. 2f88dcd Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that by Bill Wendling · 17 years ago
  78. 5e6df46 PEI now passes a RegScavenger ptr to eliminateFrameIndex. by Evan Cheng · 17 years ago
  79. 0fa1b6d By default, spills kills the register being stored. by Evan Cheng · 17 years ago
  80. 62819f3 Support to provide exception and selector registers. by Jim Laskey · 17 years ago
  81. b371f45 Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. by Evan Cheng · 17 years ago
  82. a284cbf For PR1207: by Reid Spencer · 17 years ago
  83. eceada6 Added getReservedRegs(). by Evan Cheng · 17 years ago
  84. e078d1a Only gather frame info if debug or eh. by Jim Laskey · 18 years ago
  85. 072200c Landing pad-less eh for PPC. by Jim Laskey · 18 years ago
  86. 44c3b9f Change the MachineDebugInfo to MachineModuleInfo to better reflect usage by Jim Laskey · 18 years ago
  87. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 18 years ago
  88. 0e41094 Call frames for intel. by Jim Laskey · 18 years ago
  89. 7ac947d 80 columns by Jim Laskey · 18 years ago
  90. 367372a PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary. by Evan Cheng · 18 years ago
  91. dc77540 hasFP() is now a virtual method of MRegisterInfo. by Evan Cheng · 18 years ago
  92. 2bd7b2b One more try... by Evan Cheng · 18 years ago
  93. 5ad334f Last check-in was bogus. There is no need to align the stack if the function is a leaf function (and without alloca). by Evan Cheng · 18 years ago
  94. 0327863 Backend is reponsible for aligning the stack. by Evan Cheng · 18 years ago
  95. 7f70559 * PIC codegen for X86/Linux has been implemented by Anton Korobeynikov · 18 years ago
  96. 317848f Really big cleanup. by Anton Korobeynikov · 18 years ago
  97. c2b861d Fix naming inconsistency. by Evan Cheng · 18 years ago
  98. 21b7612 f64 <-> i64 bit_convert using movq in 64-bit mode. by Evan Cheng · 18 years ago
  99. 0e8dbc6 Added MOVSS2DIrr and MOVDI2SSrr to foldMemeoryOperand(). by Evan Cheng · 18 years ago
  100. f5da133 What should be the last unnecessary <iostream>s in the library. by Bill Wendling · 18 years ago