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gerrit-public.fairphone.software / platform / external / llvm / 84defb51ca183d136e08e87d95e2c907654405f9 / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. 7b8e121 Remove unused variable by Matt Beaumont-Gay · 14 years ago
  2. 096334e ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 14 years ago
  3. 4c7edb3 ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 14 years ago
  4. d5ca201 ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 14 years ago
  5. 22925d9 Fix a misplaced paren bug. by Owen Anderson · 14 years ago
  6. b589be9 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 14 years ago
  7. 742c4ba Re-apply 144430, this time with the associated isel and disassmbler bits. by Jim Grosbach · 14 years ago
  8. eea66f6 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. by Benjamin Kramer · 14 years ago
  9. 244006d The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 14 years ago
  10. e31b42a Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 14 years ago
  11. 60cb643 Fix disassembly of some VST1 instructions. by Owen Anderson · 14 years ago
  12. 4334e03 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 14 years ago
  13. fb6ab2b More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 14 years ago
  14. cb9fed6 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 14 years ago
  15. 04b12a4 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 14 years ago
  16. 399cdca ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 14 years ago
  17. 5921675 ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 14 years ago
  18. 10b90a9 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 14 years ago
  19. a7c98f5 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 14 years ago
  20. 1a2f988 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 14 years ago
  21. 224180e Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  22. 4661d4c Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  23. b631031 Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 14 years ago
  24. cdcfa28 Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 14 years ago
  25. 280dfad ARM VLD parsing and encoding. by Jim Grosbach · 14 years ago
  26. 01817c3 Tidy up. Trailing whitespace. by Jim Grosbach · 14 years ago
  27. c378015 Removed set, but unused variables. by Chad Rosier · 14 years ago
  28. 8223e45 Fix a non-firing assert. Change: by Richard Trieu · 14 years ago
  29. ecb830e Fix undefined shift. Patch by Ahmed Charles. by Eli Friedman · 14 years ago
  30. c18e940 SETEND is not allowed in an IT block. by Owen Anderson · 14 years ago
  31. 81b2928 ARM addrmode5 represents the 'U' bit of the encoding backwards. by Jim Grosbach · 14 years ago
  32. c66e7af Thumb2 assembly parsing and encoding for LDC/STC. by Jim Grosbach · 14 years ago
  33. b0786b3 addrmode2 is gone from these, so no need for the reg0 operand. by Jim Grosbach · 14 years ago
  34. 7011eee Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. by Owen Anderson · 14 years ago
  35. 9e5887b Adding back support for printing operands symbolically to ARM's new disassembler by Kevin Enderby · 14 years ago
  36. 4ebbf7b ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. by Jim Grosbach · 14 years ago
  37. 0afa009 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. by Owen Anderson · 14 years ago
  38. 31d485e Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. by Owen Anderson · 14 years ago
  39. df0caeb Revert r140412. This affects more instructions than intended. by Owen Anderson · 14 years ago
  40. d256056 Thumb2 register-shifted-register loads cannot target the PC or the SP. by Owen Anderson · 14 years ago
  41. d9346fb tMOVSr is not allowed in an IT block either. by Owen Anderson · 14 years ago
  42. 9f666b5 CPS instructions are UNPREDICTABLE inside IT blocks. by Owen Anderson · 14 years ago
  43. 04c7877 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. by Owen Anderson · 14 years ago
  44. 7f739be Thumb2 assembly parsing and encoding for TBB/TBH. by Jim Grosbach · 14 years ago
  45. ecd1c55 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. by Owen Anderson · 14 years ago
  46. cb77551 Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. by Owen Anderson · 14 years ago
  47. 8b22778 Fix bitfield decoding based on Eli's feedback. by Owen Anderson · 14 years ago
  48. e4f2df9 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. by Owen Anderson · 14 years ago
  49. 89db0f6 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). by Owen Anderson · 14 years ago
  50. 705b48f Fix disassembly of Thumb2 LDRSH with a #-0 offset. by Owen Anderson · 14 years ago
  51. 98c5dda Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. by Owen Anderson · 14 years ago
  52. 34626ac Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. by Owen Anderson · 14 years ago
  53. a3157b4 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. by Owen Anderson · 14 years ago
  54. 921d01a LDM writeback is not allowed if Rn is in the target register list. by Owen Anderson · 14 years ago
  55. 08fef88 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. by Owen Anderson · 14 years ago
  56. 51f6a7a Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. by Owen Anderson · 14 years ago
  57. b6aed50 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. by Jim Grosbach · 14 years ago
  58. 441462f All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. by Owen Anderson · 14 years ago
  59. d2fc31b Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. by Owen Anderson · 14 years ago
  60. a77295d Thumb2 assembly parsing and encoding for LDRD(immediate). by Jim Grosbach · 14 years ago
  61. 170580e Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. by Owen Anderson · 14 years ago
  62. 8a83f71 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. by Owen Anderson · 14 years ago
  63. a5d5856 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. by James Molloy · 14 years ago
  64. 6de3c6f Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. by Owen Anderson · 14 years ago
  65. b950585 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. by James Molloy · 14 years ago
  66. a1c1100 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. by Owen Anderson · 14 years ago
  67. a680444 Fix 80 columns violations. by Owen Anderson · 14 years ago
  68. c047dca Fix up r137380 based on post-commit review by Jim Grosbach. by James Molloy · 14 years ago
  69. b45b11b The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. by Owen Anderson · 14 years ago
  70. eaca928 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. by Owen Anderson · 14 years ago
  71. f1eab59 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. by Owen Anderson · 14 years ago
  72. 9f7e831 Spelling fail. by Owen Anderson · 14 years ago
  73. 9ab0f25 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. by Owen Anderson · 14 years ago
  74. 1af7f72 Update for feedback from Jim. by Owen Anderson · 14 years ago
  75. 86ce852 ARMDisassembler: Always return a size, even when disassembling fails. by Benjamin Kramer · 14 years ago
  76. 96425c8 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. by Owen Anderson · 14 years ago
  77. 9bd655d Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. by Owen Anderson · 14 years ago
  78. 9990683 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. by Owen Anderson · 14 years ago
  79. f440820 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. by Owen Anderson · 14 years ago
  80. 12a1e3b Be careful not to walk off the end of the operand info list while updating VFP predicates. by Owen Anderson · 14 years ago
  81. 3e74d6f Move TargetRegistry and TargetSelect from Target to Support where they belong. by Evan Cheng · 14 years ago
  82. e234d02 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. by Owen Anderson · 14 years ago
  83. 82265a2 Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. by Owen Anderson · 14 years ago
  84. 6153a03 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. by Owen Anderson · 14 years ago
  85. 8e1e60b Reject invalid imod values in t2CPS instructions. by Owen Anderson · 14 years ago
  86. 357ec68 Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. by Owen Anderson · 14 years ago
  87. 2cbf210 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. by Owen Anderson · 14 years ago
  88. f1c8e3e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. by Owen Anderson · 14 years ago
  89. b113ec5 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. by Owen Anderson · 14 years ago
  90. 78affc9 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. by Owen Anderson · 14 years ago
  91. 846dd95 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. by Owen Anderson · 14 years ago
  92. 1dd56f0 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. by Owen Anderson · 14 years ago
  93. 14090bf Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. by Owen Anderson · 14 years ago
  94. c405782 Tidy up. 80 columns. by Jim Grosbach · 14 years ago
  95. 70939ee ARM clean up the imm_sr operand class representation. by Jim Grosbach · 14 years ago
  96. 0aa38ab Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. by Owen Anderson · 14 years ago
  97. 83e3f67 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. by Owen Anderson · 14 years ago
  98. 1628030 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. by Owen Anderson · 14 years ago
  99. ef2865a Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. by Owen Anderson · 14 years ago
  100. c537f3b Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. by Owen Anderson · 14 years ago