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gerrit-public.fairphone.software / platform / external / llvm / a3b8c57b9eb34af7f1677e3b002e6c8185891300 / lib / Target / X86
  1. a3b8c57 Eliminate the printCallOperand method, using a 'call' modifier on by Chris Lattner · 19 years ago
  2. 5e35168 - Update load folding checks to match those auto-generated by tblgen. by Evan Cheng · 19 years ago
  3. ba2f0a9 Use SelectRoot() as entry of any tblgen based isel. by Evan Cheng · 19 years ago
  4. 7dd281b Re-commit the last bit of change that was backed out. by Evan Cheng · 19 years ago
  5. ff805b5 Use getPreferredAlignmentLog. by Chris Lattner · 19 years ago
  6. b46ef67 Temporarily revert this patch, which probably breaks with the by Chris Lattner · 19 years ago
  7. 9c4815a Complex pattern's custom matcher should not call Select() on any operands. by Evan Cheng · 19 years ago
  8. 72f514c Remove an unnecessary predicate. by Evan Cheng · 19 years ago
  9. e3de85b Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a by Evan Cheng · 19 years ago
  10. 4efab05 remove an old comment by Chris Lattner · 19 years ago
  11. 299f9ba Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now by Chris Lattner · 19 years ago
  12. d77525d When rewriting frame instructions, emit the appropriate small-immediate by Chris Lattner · 19 years ago
  13. 33c1dab remove some target-indep and implemented notes by Chris Lattner · 19 years ago
  14. 018c02d the X86 backend no longer needs to delete its own noop copies by Chris Lattner · 19 years ago
  15. 1c07e72 fix operand numbers by Chris Lattner · 19 years ago
  16. 4083960 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) by Chris Lattner · 19 years ago
  17. 9c8dd97 implement isStoreToStackSlot by Chris Lattner · 19 years ago
  18. 1d6ecd0 add a method by Chris Lattner · 19 years ago
  19. d395d09 more notes by Chris Lattner · 19 years ago
  20. 9acddcd add a note, I have no idea how important this is. by Chris Lattner · 19 years ago
  21. 1bac941 implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll by Chris Lattner · 19 years ago
  22. 8b6e4e6 Update. by Evan Cheng · 19 years ago
  23. d25e9e8 Fix a erroneous comment. by Evan Cheng · 19 years ago
  24. 4d7db40 more notes by Chris Lattner · 19 years ago
  25. bda54cd Tell codegen MOVAPSrr and MOVAPDrr are copies. by Evan Cheng · 19 years ago
  26. b1b4e86 Added SSE entries to foldMemoryOperand(). by Evan Cheng · 19 years ago
  27. 78376d5 Rearrange code to my liking. :) by Evan Cheng · 19 years ago
  28. 3e2b94a another note by Chris Lattner · 19 years ago
  29. 750ac1b Fix some of the stuff in the PPC README file, and clean up legalization by Nate Begeman · 19 years ago
  30. 1f7c630 add a note, I'll take care of this after nate commits his big patch by Chris Lattner · 19 years ago
  31. 3c55c54 - Use xor to clear integer registers (set R, 0). by Evan Cheng · 19 years ago
  32. 214a794 Remove another entry. by Evan Cheng · 19 years ago
  33. 3e1d5e5 Another regression from the pattern isel by Chris Lattner · 19 years ago
  34. 760df29 Return's chain should be matching either the chain produced by the by Evan Cheng · 19 years ago
  35. 0d084c9 When folding a load into a return of SSE value, check the chain to by Evan Cheng · 19 years ago
  36. 4ccf4c0 Remove an item. It's done. by Evan Cheng · 19 years ago
  37. 0e8671b Be smarter about whether to store the SSE return value in memory. If by Evan Cheng · 19 years ago
  38. bb1d528 turning these into 'adds' would require extra copies by Chris Lattner · 19 years ago
  39. 223547a - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. by Evan Cheng · 19 years ago
  40. 598463f Remove entries on fabs and fneg. These are done. by Evan Cheng · 19 years ago
  41. 259e97c * Fix 80-column violations by Chris Lattner · 19 years ago
  42. ef6ffb1 Added custom lowering of fabs by Evan Cheng · 19 years ago
  43. 8e38ae6 Another high-prio selection performance bug by Chris Lattner · 19 years ago
  44. 594086d more mumbling by Chris Lattner · 19 years ago
  45. bdde465 add some notes by Chris Lattner · 19 years ago
  46. 6dfa999 Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip by Evan Cheng · 19 years ago
  47. 02568ff i64 -> f32, f32 -> i64 and some clean up. by Evan Cheng · 19 years ago
  48. 6dab053 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 by Evan Cheng · 19 years ago
  49. c6fd6cd Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. by Chris Lattner · 19 years ago
  50. 87c890a adjust prototype by Chris Lattner · 19 years ago
  51. c7097af add another note by Chris Lattner · 19 years ago
  52. 5164a31 add some performance notes from looking at sgefa by Chris Lattner · 19 years ago
  53. 6a28456 add a high-priority SSE issue from sgefa by Chris Lattner · 19 years ago
  54. b638cd8 add a missed optimization by Chris Lattner · 19 years ago
  55. 2ce5b26 Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a by Reid Spencer · 19 years ago
  56. 0fc9c26 remove now-dead code, the legalizer takes care of this for us by Chris Lattner · 19 years ago
  57. 44d9b9b The FP stack doesn't support UNDEF, ask the legalizer to legalize it by Chris Lattner · 19 years ago
  58. a54aa94 Targets all now request ConstantFP to be legalized into TargetConstantFP. by Chris Lattner · 19 years ago
  59. b8643ac Fix typo. by Jeff Cohen · 19 years ago
  60. c4013d6 Flesh out AMD family/models. by Jeff Cohen · 19 years ago
  61. 216d281 Correctly determine CPU vendor. by Jeff Cohen · 19 years ago
  62. a349640 Use union instead of reinterpret_cast. by Jeff Cohen · 19 years ago
  63. 7617717 Fix recognition of Intel CPUs. by Jeff Cohen · 19 years ago
  64. c2fad161 Is64Bit reflects the capability of the chip, not an aspect of the target os by Chris Lattner · 19 years ago
  65. dabbc98 Fix a bunch of JIT failures with the new isel by Chris Lattner · 19 years ago
  66. 41adb0d Improve X86 subtarget support for Windows and AMD. by Jeff Cohen · 19 years ago
  67. 6b2469c silence a warning by Chris Lattner · 19 years ago
  68. 1e39a15 make this work on non-native hosts by Chris Lattner · 19 years ago
  69. d41e9e5 A bit of wisdom from Chris on the last entry. by Evan Cheng · 19 years ago
  70. 85214ba AT&T assembly convention: registers are in lower case. by Evan Cheng · 19 years ago
  71. 104988a initialize all instance vars by Chris Lattner · 19 years ago
  72. e826a01 Added notes about a x86 isel deficiency. by Evan Cheng · 19 years ago
  73. dbd38d7 Added a temporary option -enable-x86-sse to enable sse support. It is used by by Evan Cheng · 19 years ago
  74. 8e44f07 Bye bye Pattern ISel, hello DAG ISel. by Evan Cheng · 19 years ago
  75. ee62557 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for by Nate Begeman · 19 years ago
  76. b3a7e21 A better workaround by Evan Cheng · 19 years ago
  77. 9f96a32 force sse/3dnow off until they work. This fixes all the x86 failures last night by Chris Lattner · 19 years ago
  78. c2493c4 Unbreak the JIT with SSE by Chris Lattner · 19 years ago
  79. 559806f x86 CPU detection and proper subtarget support by Evan Cheng · 19 years ago
  80. cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
  81. 9471c8a Improve compatibility with VC2005, patch by Morten Ofstad! by Jeff Cohen · 19 years ago
  82. 38f7373 Improve compatibility with VC2005, patch by Morten Ofstad! by Chris Lattner · 19 years ago
  83. 97c7fc3 Added preliminary x86 subtarget support. by Evan Cheng · 19 years ago
  84. 67caa39 Work around some x86 Darwin assembler bugs by Evan Cheng · 19 years ago
  85. 9bba894 When trying to fold X86::SETCC into a Select, make a copy if it has more than by Evan Cheng · 19 years ago
  86. 71fb9ad Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, by Evan Cheng · 19 years ago
  87. acc398c First part of bug 680: by Nate Begeman · 19 years ago
  88. 0b2afbd X86 prefer scheduling for reduced register pressure. by Evan Cheng · 19 years ago
  89. 0d718e9 Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it. by Evan Cheng · 19 years ago
  90. 31e6388 Loosen up these checks to allow direct uses of ESP by Chris Lattner · 19 years ago
  91. 91cacc8 use ESP directly, not a copy of ESP into some other register for fastcc calls by Chris Lattner · 19 years ago
  92. af63bb0 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END by Chris Lattner · 19 years ago
  93. 6da23db Allow jit-beta to work by Chris Lattner · 19 years ago
  94. 2c2c6c6 Add explicit #includes of <iostream> by Chris Lattner · 19 years ago
  95. 86556a5 Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual). by Evan Cheng · 19 years ago
  96. 1f16ff6 LowerReturn now doesn't have to handle f32 returns. by Chris Lattner · 19 years ago
  97. 98f5dab Stop doing that accidental commit. by Evan Cheng · 19 years ago
  98. 21d5443 A few more SH{L|R}D peepholes. by Evan Cheng · 19 years ago
  99. cce47fa Didn't mean to commit the last one. by Evan Cheng · 19 years ago
  100. 956044c Added i16 SH{L|R}D patterns. by Evan Cheng · 19 years ago