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gerrit-public.fairphone.software / platform / external / llvm / df5a7daff9c7664bff8b713e8ed5155319bc6041 / test / CodeGen / ARM
  1. 9f76ed5 Move thumb and thumb2 tests into separate directories. by Evan Cheng · 15 years ago
  2. a67efd1 Proper patterns for thumb2 shift and rotate instructions. by Evan Cheng · 15 years ago
  3. 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 15 years ago
  4. 524961e It's coalescer, not coaleser. by Evan Cheng · 15 years ago
  5. 54fc124 For Darwin on ARMv6 and newer, make register r9 available for use as a by Bob Wilson · 15 years ago
  6. 81909b7 Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. by Evan Cheng · 15 years ago
  7. 8dcbbdd hasFP should return true if frame address is taken. by Evan Cheng · 15 years ago
  8. 694f6c8 Fix PR4419: handle defs of partial uses. by Evan Cheng · 15 years ago
  9. ae69a2a Enable arm pre-allocation load / store multiple optimization pass. by Evan Cheng · 15 years ago
  10. 6b7bb42 Mark a few Thumb instructions commutable; just happened to spot this by Eli Friedman · 15 years ago
  11. 5223711 Initial support for some Thumb2 instructions. by Anton Korobeynikov · 15 years ago
  12. a4e968c Make the test target-neutral by Anton Korobeynikov · 15 years ago
  13. 2932795 GNU as refuses to assemble "pop {}" instruction. Do not emit such by Anton Korobeynikov · 15 years ago
  14. 67fcf56 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. by Evan Cheng · 15 years ago
  15. 2077e18 ifcvt should ignore cfg where true and false successors are the same. by Evan Cheng · 15 years ago
  16. 358dec5 Part 1. by Evan Cheng · 15 years ago
  17. e7d6df7 Add a ARM specific pre-allocation pass that re-schedule loads / stores from by Evan Cheng · 15 years ago
  18. 4a274e5 If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register. by Evan Cheng · 15 years ago
  19. cd799b9 Mark some pattern-less instructions as neverHasSideEffects. by Evan Cheng · 15 years ago
  20. f194b0e Add testcase for register scanveger assertion fix in r72755 by Anton Korobeynikov · 15 years ago
  21. 9254922 Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. by Evan Cheng · 15 years ago
  22. ae3a0be Split the Add, Sub, and Mul instruction opcodes into separate by Dan Gohman · 15 years ago
  23. cd0c4ac A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. by Evan Cheng · 15 years ago
  24. 1488326 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. by Evan Cheng · 15 years ago
  25. 70fd60b Temporarily revert 72756 for now. by Evan Cheng · 15 years ago
  26. 9d5fb98 Fold preceding / trailing base inc / dec into the single load / store as well. by Evan Cheng · 15 years ago
  27. 04746ea Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and by Bob Wilson · 15 years ago
  28. 224c244 Fix pr4091: Add support for "m" constraint in ARM inline assembly. by Bob Wilson · 15 years ago
  29. 0462327 Add nounwind to a few tests. by Dan Gohman · 15 years ago
  30. 74b0ccc Fix pr4195: When iterating through predecessor blocks, break out of the loop by Bob Wilson · 15 years ago
  31. 9d928c2 Fix pr4100. Do not remove no-op copies when they are dead. The register by Bob Wilson · 15 years ago
  32. caab129 Do not use register as base ptr of pre- and post- inc/dec load / store nodes. by Evan Cheng · 15 years ago
  33. afc36a9 Previously, RecursivelyDeleteDeadInstructions provided an option by Dan Gohman · 15 years ago
  34. 7eb793d Rename file to have the correct suffix. by Bob Wilson · 15 years ago
  35. 1f595bb Use CallConvLower.h and TableGen descriptions of the calling conventions by Bob Wilson · 15 years ago
  36. 2d1be87 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now by Dan Gohman · 15 years ago
  37. 442b7bf Use the output of the asm so the optimizer won't delete it. by Dale Johannesen · 15 years ago
  38. dbf1e2b move a target-specific test into its directory so it isn't run if you by Chris Lattner · 15 years ago
  39. d9df501 Fix pr3954. The register scavenger asserts for inline assembly with by Bob Wilson · 15 years ago
  40. 83593a3 Add testcase for PR3795. by Bob Wilson · 15 years ago
  41. 3d0355b Soft float support for FREM. by Duncan Sands · 15 years ago
  42. 7beb1ec Soft float support for undef. Reported by Xerxes Rånby. by Duncan Sands · 15 years ago
  43. 8f34346 Handle 'a' modifier in ARM inline assembly. Patch by Richard Pennington. by Bob Wilson · 15 years ago
  44. bf6396b Fix PR3862: Recognize some ARM-specific constraints for immediates in inline by Bob Wilson · 15 years ago
  45. f1c0ae9 Do not emit comments unless -asm-verbose. by Evan Cheng · 15 years ago
  46. 1285295 add no-unwind, remove duplicate run line. by Chris Lattner · 16 years ago
  47. 6501153 ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. by Evan Cheng · 16 years ago
  48. 4b17474 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. by Evan Cheng · 16 years ago
  49. 821b856 If a MI uses the same register more than once, only mark one of them as 'kill'. by Evan Cheng · 16 years ago
  50. c8bb37a Last commit accidentially deleted this code. by Evan Cheng · 16 years ago
  51. 04cf3e3 The last commit was overly conservative. It's ok to reuse value that's already marked livein. by Evan Cheng · 16 years ago
  52. 58207f1 If a use operand is marked isKill, don't forget to add kill to its live interval as well. by Evan Cheng · 16 years ago
  53. bf18939 A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes. by Evan Cheng · 16 years ago
  54. 8182347 Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. by Evan Cheng · 16 years ago
  55. f0e366a Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. by Evan Cheng · 16 years ago
  56. 8f0d99e Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. by Evan Cheng · 16 years ago
  57. 7f51fd3 Revert r63999. It was breaking self-hosting builds. by Bill Wendling · 16 years ago
  58. c963b63 Enable machine sinking pass in non-fast mode. by Evan Cheng · 16 years ago
  59. c5d1a4f Turn on machine LICM in non-fast mode. by Evan Cheng · 16 years ago
  60. bb46f52 Add the private linkage. by Rafael Espindola · 16 years ago
  61. c3ccc1a Clean up some ARM GV asm printing out; minor fixes to match what gcc does. by Evan Cheng · 16 years ago
  62. d37c13c - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. by Evan Cheng · 16 years ago
  63. 9c64bf3 Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later. by Evan Cheng · 16 years ago
  64. 3eb22e8 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls. by Evan Cheng · 16 years ago
  65. c7c7729 Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes. by Evan Cheng · 16 years ago
  66. 2c9c3e7 Implement function notes as function attributes. by Devang Patel · 16 years ago
  67. 870e4be Unallocatable registers do not have live intervals. by Evan Cheng · 16 years ago
  68. 5eb0cec Re-enable SelectionDAG CSE for calls. It matters in the case of by Dan Gohman · 16 years ago
  69. 25f34a3 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. by Evan Cheng · 16 years ago
  70. 4b88702 Legalizer was missing code that expand fpow to a libcall. by Evan Cheng · 16 years ago
  71. 711b6dc It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. by Evan Cheng · 16 years ago
  72. feac94b Print section flags ok on platforms, which use '@' as comment string. Fix test. by Anton Korobeynikov · 16 years ago
  73. 287b7b7 This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding. by Owen Anderson · 16 years ago
  74. 3888aa0 Remove the need for -disable-correct-folding from this test. by Owen Anderson · 16 years ago
  75. 2b85dc3 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. by Owen Anderson · 16 years ago
  76. d1b3da6 Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589. by Evan Cheng · 16 years ago
  77. c3e2672 Softfloat support for FDIV. Patch by Richard Pennington. by Duncan Sands · 16 years ago
  78. f6cadc4 sabre brings to my attention that the 'tr' suffix is also obsolete by Gabor Greif · 16 years ago
  79. 722243b Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. by Gabor Greif · 16 years ago
  80. 7a0f185 More local spiller complexity! by Evan Cheng · 16 years ago
  81. b0a6f62 Don't spill dead def. by Evan Cheng · 16 years ago
  82. f870fbc If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy. by Evan Cheng · 16 years ago
  83. b94d966 New test. by Evan Cheng · 16 years ago
  84. 1dc7869 1. IMPLICIT_DEF can *re-define* any register. by Evan Cheng · 16 years ago
  85. 9845eb5 More soft fp fixes. by Evan Cheng · 16 years ago
  86. 110cf48 Unbreak ARM / Thumb soft FP support. by Evan Cheng · 16 years ago
  87. d68f47c Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. by Evan Cheng · 17 years ago
  88. 433f6f6 Constant fold SIGN_EXTEND_INREG with ashr not lshr. by Evan Cheng · 17 years ago
  89. 65201f5 DCE'ed this testcase. by Bill Wendling · 17 years ago
  90. 97e3c01 If we reload a virtual register that's already been assigned, we want to mark by Bill Wendling · 17 years ago
  91. 6263f94 Remove llvm-upgrade. by Tanya Lattner · 17 years ago
  92. b745e88 It's PR1925, not PR1609. by Evan Cheng · 17 years ago
  93. 2fc628d Fix a number of local register allocator issues: PR1609. by Evan Cheng · 17 years ago
  94. 15c2351 Update this test. Due to dag combiner improvements, we now compile f7/f11 to: by Chris Lattner · 17 years ago
  95. e3c1cfb Remove xfail. This is fixed. by Evan Cheng · 17 years ago
  96. 33faddc Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta. by Evan Cheng · 17 years ago
  97. 5ef3a04 Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate. by Evan Cheng · 17 years ago
  98. 213ee90 Update tests. by Evan Cheng · 17 years ago
  99. 2adcf10 update this test after the fmrrd fix by Chris Lattner · 17 years ago
  100. 727842e Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines. by Tanya Lattner · 17 years ago