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gerrit-public.fairphone.software / platform / external / llvm / e13f441e002b95bb64d883d173f6aff9615556fd / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. 759e3fa Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 13 years ago
  2. d04a8d4 Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  3. 1c83093 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst by Kevin Enderby · 13 years ago
  4. 445ba85 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target by Kevin Enderby · 13 years ago
  5. 88d1266 Fix a bug where a 32-bit address with the high bit does not get symbolicated by Kevin Enderby · 13 years ago
  6. 93c7c44 Fix the handling of edge cases in ARM shifted operands. by Tim Northover · 13 years ago
  7. 24b9f25 Diagnose invalid alignments on duplicating VLDn instructions. by Tim Northover · 13 years ago
  8. eae1d34 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. by Tim Northover · 13 years ago
  9. 1144af3 Fix integer undefined behavior due to signed left shift overflow in LLVM. by Richard Smith · 13 years ago
  10. 960fb74 Remove unnecessary include of ARMGenInstrInfo.inc. by Craig Topper · 13 years ago
  11. fc1a161 Switch the fixed-length disassembler to be table-driven. by Jim Grosbach · 13 years ago
  12. fd652df Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. by Jiangning Liu · 13 years ago
  13. c1b7ca5 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. by Jiangning Liu · 13 years ago
  14. c8e41c5 Fix a typo (the the => the) by Sylvestre Ledru · 13 years ago
  15. fae96f1 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! by Richard Barton · 13 years ago
  16. 270e362 Revert r159938 (and r159945) to appease the buildbots. by Chad Rosier · 13 years ago
  17. 83cfff6 Oops - correct broken disassembly for VMOV by Richard Barton · 13 years ago
  18. 2e7e34b Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) by Richard Barton · 13 years ago
  19. c8f2fcc Correct decoder for T1 conditional B encoding by Richard Barton · 13 years ago
  20. dd051a0 ARMDisassembler.cpp: Fix utf8 char in comments. by NAKAMURA Takumi · 13 years ago
  21. 3610a15 Tweak to the fix in r156212, as with the change in removing the shift the by Kevin Enderby · 13 years ago
  22. ce734d5 Fix a bug in the ARM disassembler for wide branch conditional instructions by Kevin Enderby · 13 years ago
  23. 2d524b0 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits by Kevin Enderby · 13 years ago
  24. b422d0b Fixed disassembler for vstm/vldm ARM VFP instructions. by Silviu Baranga · 13 years ago
  25. bb32f1d ARM: Tweak tADDrSP definition for consistent operand order. by Jim Grosbach · 13 years ago
  26. 4d2f077 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. by Richard Barton · 13 years ago
  27. f4478f9 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector by Richard Barton · 13 years ago
  28. 35ee7d2 Added support for disassembling unpredictable swp/swpb ARM instructions. by Silviu Baranga · 13 years ago
  29. fa1ebc6 Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. by Silviu Baranga · 13 years ago
  30. c5a2a33 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) by Kevin Enderby · 13 years ago
  31. 2a7d3a9 Fix a few more places in the ARM disassembler so that branches get by Kevin Enderby · 13 years ago
  32. b318cc1 Fixed a case of ARM disassembly getting an assert on a bad encoding by Kevin Enderby · 13 years ago
  33. a69da35 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case by Kevin Enderby · 13 years ago
  34. 75e3b7f ARMDisassembler: drop bogus dependency on ARMCodeGen by Dylan Noblesmith · 13 years ago
  35. c89c744 Remove unnecessary llvm:: qualifications by Craig Topper · 13 years ago
  36. 6fe310e Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. by Silviu Baranga · 13 years ago
  37. b7c2ed6 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM by Silviu Baranga · 13 years ago
  38. f0586f0 Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test by Kevin Enderby · 13 years ago
  39. 5c062ad The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. by Silviu Baranga · 13 years ago
  40. b78ca42 Use uint16_t to store registers and opcode in static tables in the target specific backends. by Craig Topper · 13 years ago
  41. ff3164a Tidy up. Remove dead code that slipped into previous commit. by Jim Grosbach · 13 years ago
  42. 4d0983a ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 13 years ago
  43. c0fc450 ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 13 years ago
  44. 158c8a4 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. by Kevin Enderby · 13 years ago
  45. c3384c9 ARM Refactor VLD/VST spaced pair instructions. by Jim Grosbach · 13 years ago
  46. 28f08c9 ARM refactor away a bunch of VLD/VST pseudo instructions. by Jim Grosbach · 13 years ago
  47. adef06a Make MemoryObject accessor members const again by Derek Schuff · 13 years ago
  48. 0943303 Fix the symbolic operand added for the C disassmbler API for the ARM bl by Kevin Enderby · 13 years ago
  49. b80d571 Updated the llvm-mc disassembler C API to support for the X86 target. by Kevin Enderby · 14 years ago
  50. 31d157a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 14 years ago
  51. 88b6fc0 Make the EDis tables const. by Benjamin Kramer · 14 years ago
  52. bc21981 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  53. 2ea9387 Enable streaming of bitcode by Derek Schuff · 14 years ago
  54. 4d6ccb5 More dead code removal (using -Wunreachable-code) by David Blaikie · 14 years ago
  55. 60d99a5 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 14 years ago
  56. bb3a2e4 ARM NEON refactor VST2 w/ writeback instructions. by Jim Grosbach · 14 years ago
  57. e90ac9b ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 14 years ago
  58. a4e3c7f ARM assembly parsing and encoding for VLD2 with writeback. by Jim Grosbach · 14 years ago
  59. 7b8e121 Remove unused variable by Matt Beaumont-Gay · 14 years ago
  60. 096334e ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 14 years ago
  61. 4c7edb3 ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 14 years ago
  62. d5ca201 ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 14 years ago
  63. 22925d9 Fix a misplaced paren bug. by Owen Anderson · 14 years ago
  64. b589be9 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 14 years ago
  65. 742c4ba Re-apply 144430, this time with the associated isel and disassmbler bits. by Jim Grosbach · 14 years ago
  66. eea66f6 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. by Benjamin Kramer · 14 years ago
  67. 244006d The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 14 years ago
  68. e31b42a Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 14 years ago
  69. 60cb643 Fix disassembly of some VST1 instructions. by Owen Anderson · 14 years ago
  70. 4334e03 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 14 years ago
  71. fb6ab2b More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 14 years ago
  72. cb9fed6 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 14 years ago
  73. 04b12a4 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 14 years ago
  74. 399cdca ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 14 years ago
  75. 5921675 ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 14 years ago
  76. 10b90a9 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 14 years ago
  77. a7c98f5 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 14 years ago
  78. 1a2f988 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 14 years ago
  79. 224180e Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  80. 4661d4c Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  81. b631031 Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 14 years ago
  82. cdcfa28 Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 14 years ago
  83. 280dfad ARM VLD parsing and encoding. by Jim Grosbach · 14 years ago
  84. 01817c3 Tidy up. Trailing whitespace. by Jim Grosbach · 14 years ago
  85. c378015 Removed set, but unused variables. by Chad Rosier · 14 years ago
  86. 8223e45 Fix a non-firing assert. Change: by Richard Trieu · 14 years ago
  87. ecb830e Fix undefined shift. Patch by Ahmed Charles. by Eli Friedman · 14 years ago
  88. c18e940 SETEND is not allowed in an IT block. by Owen Anderson · 14 years ago
  89. 81b2928 ARM addrmode5 represents the 'U' bit of the encoding backwards. by Jim Grosbach · 14 years ago
  90. c66e7af Thumb2 assembly parsing and encoding for LDC/STC. by Jim Grosbach · 14 years ago
  91. b0786b3 addrmode2 is gone from these, so no need for the reg0 operand. by Jim Grosbach · 14 years ago
  92. 7011eee Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. by Owen Anderson · 14 years ago
  93. 9e5887b Adding back support for printing operands symbolically to ARM's new disassembler by Kevin Enderby · 14 years ago
  94. 4ebbf7b ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. by Jim Grosbach · 14 years ago
  95. 0afa009 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. by Owen Anderson · 14 years ago
  96. 31d485e Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. by Owen Anderson · 14 years ago
  97. df0caeb Revert r140412. This affects more instructions than intended. by Owen Anderson · 14 years ago
  98. d256056 Thumb2 register-shifted-register loads cannot target the PC or the SP. by Owen Anderson · 14 years ago
  99. d9346fb tMOVSr is not allowed in an IT block either. by Owen Anderson · 14 years ago
  100. 9f666b5 CPS instructions are UNPREDICTABLE inside IT blocks. by Owen Anderson · 14 years ago