| commit | 2badf0e85b3a54119b08c559dc18aed43a156295 | [log] [tgz] |
|---|---|---|
| author | Anuj Phogat <anuj.phogat@gmail.com> | Thu May 31 16:03:44 2018 -0700 |
| committer | Anuj Phogat <anuj.phogat@gmail.com> | Mon Jul 09 15:38:42 2018 -0700 |
| tree | 9226ec23b0f30aa7c067431678ee3ad914a4f881 | |
| parent | c1d8300117891ec87762caa30d14307622c65bcf [diff] |
i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>