| commit | 493bfa54a57e2feddd887ba0ec3d5ef139e82f3b | [log] [tgz] |
|---|---|---|
| author | Jason Ekstrand <jason.ekstrand@intel.com> | Thu Oct 02 16:04:57 2014 -0700 |
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | Thu Oct 02 16:38:25 2014 -0700 |
| tree | fd7c83b06ab7f98c8223965af272694889b7f9d2 | |
| parent | 50d0e2e118fb3e42dc83c83de34da3eac0a0d8a1 [diff] |
i965/fs: Use the correct base_mrf for spilling pairs in SIMD8 Before, we were hard-coding the base_mrf based on dispatch width not number of registers spilled at a time. This caused us to emit instructions with a base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16 register. This fixes the problem. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>