i965/vec4: Fix mapping attributes
This patch reverts 57bab6708f2bbc1ab8a3d202e9a467963596d462, which was
causing issues with ILK and earlier VS programs.
1. brw_nir.c: Revert "i965/vec4/nir: vec4 also needs to remap vs attributes"
Do not perform a remap in vec4 backend. Rather, do it later when
setup attributes
2. brw_vec4.cpp: This fixes mapping ATTRx to proper GRFn.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99391
[jordan.l.justen@intel.com: merge Juan's two patches from bugzilla]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index b39e2b1..3c1bc51 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -95,19 +95,9 @@
}
}
-struct remap_vs_attrs_params {
- shader_info *nir_info;
- bool is_scalar;
-};
-
static bool
-remap_vs_attrs(nir_block *block, void *closure)
+remap_vs_attrs(nir_block *block, shader_info *nir_info)
{
- struct remap_vs_attrs_params *params =
- (struct remap_vs_attrs_params *) closure;
- shader_info *nir_info = params->nir_info;
- bool is_scalar = params->is_scalar;
-
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
@@ -123,7 +113,7 @@
int attr = intrin->const_index[0];
int slot = _mesa_bitcount_64(nir_info->inputs_read &
BITFIELD64_MASK(attr));
- intrin->const_index[0] = is_scalar ? 4 * slot : slot;
+ intrin->const_index[0] = 4 * slot;
}
}
return true;
@@ -267,11 +257,6 @@
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags)
{
- struct remap_vs_attrs_params params = {
- .nir_info = nir->info,
- .is_scalar = is_scalar
- };
-
/* Start with the location of the variable's base. */
foreach_list_typed(nir_variable, var, node, &nir->inputs) {
var->data.driver_location = var->data.location;
@@ -291,11 +276,14 @@
brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
vs_attrib_wa_flags);
- /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
- nir_foreach_function(function, nir) {
- if (function->impl) {
- nir_foreach_block(block, function->impl) {
- remap_vs_attrs(block, ¶ms);
+ if (is_scalar) {
+ /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
+
+ nir_foreach_function(function, nir) {
+ if (function->impl) {
+ nir_foreach_block(block, function->impl) {
+ remap_vs_attrs(block, nir->info);
+ }
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 748a068..5e60eb6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1739,7 +1739,7 @@
int needed_slots =
(vs_prog_data->double_inputs_read & BITFIELD64_BIT(first)) ? 2 : 1;
for (int c = 0; c < needed_slots; c++) {
- attribute_map[nr_attributes] = payload_reg + nr_attributes;
+ attribute_map[first + c] = payload_reg + nr_attributes;
nr_attributes++;
vs_inputs &= ~BITFIELD64_BIT(first + c);
}