ci: Disable SMP on the a5xx boards.
CPU0 comes up at some plausible freq, but the rest are at 19Mhz waiting
for cpufreq to come up, which has not been upstreamed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 3364909..3f00f95 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -874,7 +874,9 @@
variables:
BM_KERNEL: /lava-files/db820c-kernel
BM_DTB: /lava-files/db820c.dtb
- BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8"
+ # Disable SMP because only CPU 0 is at a freq higher than 19mhz on
+ # current upstream kernel.
+ BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 nosmp"
DEQP_EXPECTED_FAILS: deqp-freedreno-a530-fails.txt
DEQP_SKIPS: deqp-freedreno-a530-skips.txt
DEQP_EXPECTED_RENDERER: FD530