commit 75d402b2118c55b0131025016a859a35733746b5
author Chia-I Wu <olvaffe@gmail.com> Wed Apr 10 21:32:13 2013 +0800
committer Eric Anholt <eric@anholt.net> Wed Apr 24 12:56:17 2013 -0700
tree d9b420ad6fd4255e3e5b7ed798e82780d73b76bd
parent bc98950a2a667fbf415e4caf820b4b5e50839b49

i965/gen7: fix 3DSTATE_LINE_STIPPLE_PATTERN

The inverse repeat count should taks up bits 31:15 and is in U1.16.  Fixes
the "Restarting lines within a single Begin/End block" subtest of piglit
linestipple, and gets the other failing subtests much closer to passing.

v2: Rewrite commit message with more detailed piglit info (by anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>

src/mesa/drivers/dri/i965/brw_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 953f6cd..6b61929 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -947,9 +947,20 @@
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
    OUT_BATCH(ctx->Line.StipplePattern);
-   tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
-   tmpi = tmp * (1<<13);
-   OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
+
+   if (intel->gen >= 7) {
+      /* in U1.16 */
+      tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
+      tmpi = tmp * (1<<16);
+      OUT_BATCH(tmpi << 15 | ctx->Line.StippleFactor);
+   }
+   else {
+      /* in U1.13 */
+      tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
+      tmpi = tmp * (1<<13);
+      OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
+   }
+
    CACHED_BATCH();
 }