commit 76bb695f096667383597af78efd29dc466858dc6
author Jason Ekstrand <jason.ekstrand@intel.com> Fri Oct 24 11:37:55 2014 -0700
committer Jason Ekstrand <jason.ekstrand@intel.com> Mon Oct 27 13:35:57 2014 -0700
tree 6fd7c8012bb6666937adddb3c24f95d09ff18549
parent 3a5df8b61272fe78badb195c267c04a9e78d920f

i965/fs: Don't [un]spill multiple registers at a time in SIMD8 mode

I thought this would be a clever way to make spilling less expensive.
However, it appears that the oword read/write messages we are using for
spilling ignore the execution size and assume SIMD16 whenever working with
more than one register.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 7ae6c75..ee5e123 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -688,8 +688,10 @@
                          uint32_t spill_offset, int count)
 {
    int reg_size = 1;
-   if (count % 2 == 0)
+   if (dispatch_width == 16 && count % 2 == 0) {
       reg_size = 2;
+      dst.width = 16;
+   }
 
    for (int i = 0; i < count / reg_size; i++) {
       /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
@@ -722,7 +724,7 @@
 {
    int reg_size = 1;
    int spill_base_mrf = 14;
-   if (count % 2 == 0) {
+   if (dispatch_width == 16 && count % 2 == 0) {
       spill_base_mrf = 13;
       reg_size = 2;
    }