commit 8621961d4334bbfd51cb9e1934c6dcbc741699a9
author Topi Pohjolainen <topi.pohjolainen@intel.com> Tue Jan 17 11:48:49 2017 +0200
committer Emil Velikov <emil.l.velikov@gmail.com> Tue Jan 24 17:17:53 2017 +0000
tree c2511a8ffde0ae644de4d07e09bfdd5027335f65
parent 7d5a98f106b0695aca305bac8eb8833324bb8fe3

i965/gen6: Issue direct depth stall and flush after depth clear

instead of calling unconditionally brw_emit_mi_flush() which
does:

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                PIPE_CONTROL_RENDER_TARGET_FLUSH |
                                PIPE_CONTROL_CS_STALL);

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
                                PIPE_CONTROL_CONST_CACHE_INVALIDATE);

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 46b346899d98e29943f8cd74c25bcb8d2f868a49)