radeonsi: optimize access pattern for compute blits with linear textures
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
diff --git a/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c b/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
index d1a97c2..c1a150d 100644
--- a/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
+++ b/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
@@ -503,18 +503,16 @@
{
static const char text[] =
"COMP\n"
- "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
- "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
- "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
"DCL SV[0], THREAD_ID\n"
"DCL SV[1], BLOCK_ID\n"
+ "DCL SV[2], BLOCK_SIZE\n"
"DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
"DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
"DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
"DCL TEMP[0..4], LOCAL\n"
- "IMM[0] UINT32 {8, 1, 0, 0}\n"
+
"MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
- "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
+ "UMAD TEMP[1].xyz, SV[1].xyzz, SV[2].xyzz, SV[0].xyzz\n"
"UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
"LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
"MOV TEMP[4].xyz, CONST[0][1].xyzw\n"