| commit | c1d8300117891ec87762caa30d14307622c65bcf | [log] [tgz] |
|---|---|---|
| author | Anuj Phogat <anuj.phogat@gmail.com> | Thu May 31 15:41:53 2018 -0700 |
| committer | Anuj Phogat <anuj.phogat@gmail.com> | Mon Jul 09 15:38:42 2018 -0700 |
| tree | f3ee9eee84887d1c1dd17125f549b36df509679e | |
| parent | 227dabc2664b886e621de03d9ba82073e2fd16aa [diff] |
anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>