radeonsi: prepare depth export registers at compile time
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 3ed4ad2..5f4f1bf 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1413,6 +1413,7 @@
out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
mask |= 0x1;
+ si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
}
if (stencil_index >= 0) {
@@ -1422,8 +1423,15 @@
* breaks some stencil piglit tests
*/
mask |= 0x3;
+ si_shader_ctx->shader->db_shader_control |=
+ S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
}
+ if (stencil_index >= 0)
+ si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
+ else
+ si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
+
/* Specify which components to enable */
args[0] = lp_build_const_int32(base->gallivm, mask);