i965/vec4: do not trim dead channels on gen6 for math

Do not set a writemask on Gen6 for math instructions, those are
executed using align1 mode that does not support a destination mask.

v2: cleanups, better comment (Matt)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76883

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
1 file changed