Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2016 Red Hat. |
| 3 | * Copyright © 2016 Bas Nieuwenhuizen |
| 4 | * |
| 5 | * based in part on anv driver which is: |
| 6 | * Copyright © 2015 Intel Corporation |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the "Software"), |
| 10 | * to deal in the Software without restriction, including without limitation |
| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| 13 | * Software is furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the next |
| 16 | * paragraph) shall be included in all copies or substantial portions of the |
| 17 | * Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 24 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 25 | * IN THE SOFTWARE. |
| 26 | */ |
| 27 | |
| 28 | #include "util/mesa-sha1.h" |
| 29 | #include "radv_private.h" |
| 30 | #include "nir/nir.h" |
| 31 | #include "nir/nir_builder.h" |
| 32 | #include "spirv/nir_spirv.h" |
| 33 | |
| 34 | #include <llvm-c/Core.h> |
| 35 | #include <llvm-c/TargetMachine.h> |
| 36 | |
| 37 | #include "sid.h" |
| 38 | #include "r600d_common.h" |
| 39 | #include "ac_binary.h" |
| 40 | #include "ac_llvm_util.h" |
| 41 | #include "ac_nir_to_llvm.h" |
| 42 | #include "vk_format.h" |
| 43 | #include "util/debug.h" |
| 44 | void radv_shader_variant_destroy(struct radv_device *device, |
| 45 | struct radv_shader_variant *variant); |
| 46 | |
| 47 | static const struct nir_shader_compiler_options nir_options = { |
| 48 | .vertex_id_zero_based = true, |
| 49 | .lower_scmp = true, |
| 50 | .lower_flrp32 = true, |
| 51 | .lower_fsat = true, |
| 52 | .lower_pack_snorm_2x16 = true, |
| 53 | .lower_pack_snorm_4x8 = true, |
| 54 | .lower_pack_unorm_2x16 = true, |
| 55 | .lower_pack_unorm_4x8 = true, |
| 56 | .lower_unpack_snorm_2x16 = true, |
| 57 | .lower_unpack_snorm_4x8 = true, |
| 58 | .lower_unpack_unorm_2x16 = true, |
| 59 | .lower_unpack_unorm_4x8 = true, |
| 60 | .lower_extract_byte = true, |
| 61 | .lower_extract_word = true, |
| 62 | }; |
| 63 | |
| 64 | VkResult radv_CreateShaderModule( |
| 65 | VkDevice _device, |
| 66 | const VkShaderModuleCreateInfo* pCreateInfo, |
| 67 | const VkAllocationCallbacks* pAllocator, |
| 68 | VkShaderModule* pShaderModule) |
| 69 | { |
| 70 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 71 | struct radv_shader_module *module; |
| 72 | |
| 73 | assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO); |
| 74 | assert(pCreateInfo->flags == 0); |
| 75 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 76 | module = vk_alloc2(&device->alloc, pAllocator, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 77 | sizeof(*module) + pCreateInfo->codeSize, 8, |
| 78 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 79 | if (module == NULL) |
| 80 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 81 | |
| 82 | module->nir = NULL; |
| 83 | module->size = pCreateInfo->codeSize; |
| 84 | memcpy(module->data, pCreateInfo->pCode, module->size); |
| 85 | |
| 86 | _mesa_sha1_compute(module->data, module->size, module->sha1); |
| 87 | |
| 88 | *pShaderModule = radv_shader_module_to_handle(module); |
| 89 | |
| 90 | return VK_SUCCESS; |
| 91 | } |
| 92 | |
| 93 | void radv_DestroyShaderModule( |
| 94 | VkDevice _device, |
| 95 | VkShaderModule _module, |
| 96 | const VkAllocationCallbacks* pAllocator) |
| 97 | { |
| 98 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 99 | RADV_FROM_HANDLE(radv_shader_module, module, _module); |
| 100 | |
| 101 | if (!module) |
| 102 | return; |
| 103 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 104 | vk_free2(&device->alloc, pAllocator, module); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | void radv_DestroyPipeline( |
| 108 | VkDevice _device, |
| 109 | VkPipeline _pipeline, |
| 110 | const VkAllocationCallbacks* pAllocator) |
| 111 | { |
| 112 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 113 | RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); |
| 114 | |
| 115 | if (!_pipeline) |
| 116 | return; |
| 117 | |
| 118 | for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) |
| 119 | if (pipeline->shaders[i]) |
| 120 | radv_shader_variant_destroy(device, pipeline->shaders[i]); |
| 121 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 122 | vk_free2(&device->alloc, pAllocator, pipeline); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | |
| 126 | static void |
| 127 | radv_optimize_nir(struct nir_shader *shader) |
| 128 | { |
| 129 | bool progress; |
| 130 | |
| 131 | do { |
| 132 | progress = false; |
| 133 | |
| 134 | NIR_PASS_V(shader, nir_lower_vars_to_ssa); |
| 135 | NIR_PASS_V(shader, nir_lower_alu_to_scalar); |
| 136 | NIR_PASS_V(shader, nir_lower_phis_to_scalar); |
| 137 | |
| 138 | NIR_PASS(progress, shader, nir_copy_prop); |
| 139 | NIR_PASS(progress, shader, nir_opt_remove_phis); |
| 140 | NIR_PASS(progress, shader, nir_opt_dce); |
| 141 | NIR_PASS(progress, shader, nir_opt_dead_cf); |
| 142 | NIR_PASS(progress, shader, nir_opt_cse); |
| 143 | NIR_PASS(progress, shader, nir_opt_peephole_select, 8); |
| 144 | NIR_PASS(progress, shader, nir_opt_algebraic); |
| 145 | NIR_PASS(progress, shader, nir_opt_constant_folding); |
| 146 | NIR_PASS(progress, shader, nir_opt_undef); |
| 147 | } while (progress); |
| 148 | } |
| 149 | |
| 150 | static nir_shader * |
| 151 | radv_shader_compile_to_nir(struct radv_device *device, |
| 152 | struct radv_shader_module *module, |
| 153 | const char *entrypoint_name, |
| 154 | gl_shader_stage stage, |
| 155 | const VkSpecializationInfo *spec_info, |
| 156 | bool dump) |
| 157 | { |
| 158 | if (strcmp(entrypoint_name, "main") != 0) { |
| 159 | radv_finishme("Multiple shaders per module not really supported"); |
| 160 | } |
| 161 | |
| 162 | nir_shader *nir; |
| 163 | nir_function *entry_point; |
| 164 | if (module->nir) { |
| 165 | /* Some things such as our meta clear/blit code will give us a NIR |
| 166 | * shader directly. In that case, we just ignore the SPIR-V entirely |
| 167 | * and just use the NIR shader */ |
| 168 | nir = module->nir; |
| 169 | nir->options = &nir_options; |
| 170 | nir_validate_shader(nir); |
| 171 | |
| 172 | assert(exec_list_length(&nir->functions) == 1); |
| 173 | struct exec_node *node = exec_list_get_head(&nir->functions); |
| 174 | entry_point = exec_node_data(nir_function, node, node); |
| 175 | } else { |
| 176 | uint32_t *spirv = (uint32_t *) module->data; |
| 177 | assert(module->size % 4 == 0); |
| 178 | |
| 179 | uint32_t num_spec_entries = 0; |
| 180 | struct nir_spirv_specialization *spec_entries = NULL; |
| 181 | if (spec_info && spec_info->mapEntryCount > 0) { |
| 182 | num_spec_entries = spec_info->mapEntryCount; |
| 183 | spec_entries = malloc(num_spec_entries * sizeof(*spec_entries)); |
| 184 | for (uint32_t i = 0; i < num_spec_entries; i++) { |
| 185 | VkSpecializationMapEntry entry = spec_info->pMapEntries[i]; |
| 186 | const void *data = spec_info->pData + entry.offset; |
| 187 | assert(data + entry.size <= spec_info->pData + spec_info->dataSize); |
| 188 | |
| 189 | spec_entries[i].id = spec_info->pMapEntries[i].constantID; |
| 190 | spec_entries[i].data = *(const uint32_t *)data; |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | entry_point = spirv_to_nir(spirv, module->size / 4, |
| 195 | spec_entries, num_spec_entries, |
| 196 | stage, entrypoint_name, &nir_options); |
| 197 | nir = entry_point->shader; |
| 198 | assert(nir->stage == stage); |
| 199 | nir_validate_shader(nir); |
| 200 | |
| 201 | free(spec_entries); |
| 202 | |
| 203 | nir_lower_returns(nir); |
| 204 | nir_validate_shader(nir); |
| 205 | |
| 206 | nir_inline_functions(nir); |
| 207 | nir_validate_shader(nir); |
| 208 | |
| 209 | /* Pick off the single entrypoint that we want */ |
| 210 | foreach_list_typed_safe(nir_function, func, node, &nir->functions) { |
| 211 | if (func != entry_point) |
| 212 | exec_node_remove(&func->node); |
| 213 | } |
| 214 | assert(exec_list_length(&nir->functions) == 1); |
| 215 | entry_point->name = ralloc_strdup(entry_point, "main"); |
| 216 | |
| 217 | nir_remove_dead_variables(nir, nir_var_shader_in); |
| 218 | nir_remove_dead_variables(nir, nir_var_shader_out); |
| 219 | nir_remove_dead_variables(nir, nir_var_system_value); |
| 220 | nir_validate_shader(nir); |
| 221 | |
| 222 | nir_lower_system_values(nir); |
| 223 | nir_validate_shader(nir); |
| 224 | } |
| 225 | |
| 226 | /* Vulkan uses the separate-shader linking model */ |
| 227 | nir->info.separate_shader = true; |
| 228 | |
| 229 | // nir = brw_preprocess_nir(compiler, nir); |
| 230 | |
| 231 | nir_shader_gather_info(nir, entry_point->impl); |
| 232 | |
| 233 | nir_variable_mode indirect_mask = 0; |
| 234 | // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput) |
| 235 | indirect_mask |= nir_var_shader_in; |
| 236 | // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp) |
| 237 | indirect_mask |= nir_var_local; |
| 238 | |
| 239 | nir_lower_indirect_derefs(nir, indirect_mask); |
| 240 | |
| 241 | static const nir_lower_tex_options tex_options = { |
| 242 | .lower_txp = ~0, |
| 243 | }; |
| 244 | |
| 245 | nir_lower_tex(nir, &tex_options); |
| 246 | |
| 247 | nir_lower_vars_to_ssa(nir); |
| 248 | nir_lower_var_copies(nir); |
| 249 | nir_lower_global_vars_to_local(nir); |
| 250 | nir_remove_dead_variables(nir, nir_var_local); |
| 251 | radv_optimize_nir(nir); |
| 252 | |
| 253 | if (dump) |
| 254 | nir_print_shader(nir, stderr); |
| 255 | |
| 256 | return nir; |
| 257 | } |
| 258 | |
| 259 | void radv_shader_variant_destroy(struct radv_device *device, |
| 260 | struct radv_shader_variant *variant) |
| 261 | { |
| 262 | if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1) |
| 263 | return; |
| 264 | |
| 265 | device->ws->buffer_destroy(variant->bo); |
| 266 | free(variant); |
| 267 | } |
| 268 | |
| 269 | static |
| 270 | struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device, |
| 271 | struct nir_shader *shader, |
| 272 | struct radv_pipeline_layout *layout, |
| 273 | const union ac_shader_variant_key *key, |
| 274 | void** code_out, |
| 275 | unsigned *code_size_out, |
| 276 | bool dump) |
| 277 | { |
| 278 | struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant)); |
| 279 | enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family; |
| 280 | LLVMTargetMachineRef tm; |
| 281 | if (!variant) |
| 282 | return NULL; |
| 283 | |
| 284 | struct ac_nir_compiler_options options = {0}; |
| 285 | options.layout = layout; |
| 286 | if (key) |
| 287 | options.key = *key; |
| 288 | |
| 289 | struct ac_shader_binary binary; |
| 290 | |
| 291 | options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false); |
| 292 | options.family = chip_family; |
| 293 | options.chip_class = device->instance->physicalDevice.rad_info.chip_class; |
| 294 | tm = ac_create_target_machine(chip_family); |
| 295 | ac_compile_nir_shader(tm, &binary, &variant->config, |
| 296 | &variant->info, shader, &options, dump); |
| 297 | LLVMDisposeTargetMachine(tm); |
| 298 | |
| 299 | bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; |
| 300 | unsigned vgpr_comp_cnt = 0; |
| 301 | |
| 302 | if (scratch_enabled) |
| 303 | radv_finishme("shader scratch space"); |
| 304 | switch (shader->stage) { |
| 305 | case MESA_SHADER_VERTEX: |
| 306 | variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | |
| 307 | S_00B12C_SCRATCH_EN(scratch_enabled); |
| 308 | vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; |
| 309 | break; |
| 310 | case MESA_SHADER_FRAGMENT: |
| 311 | variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | |
| 312 | S_00B12C_SCRATCH_EN(scratch_enabled); |
| 313 | break; |
| 314 | case MESA_SHADER_COMPUTE: |
| 315 | variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) | |
| 316 | S_00B84C_SCRATCH_EN(scratch_enabled) | |
| 317 | S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) | |
| 318 | S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) | |
| 319 | S_00B84C_TG_SIZE_EN(1) | |
| 320 | S_00B84C_LDS_SIZE(variant->config.lds_size); |
| 321 | break; |
| 322 | default: |
| 323 | unreachable("unsupported shader type"); |
| 324 | break; |
| 325 | } |
| 326 | |
| 327 | variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | |
| 328 | S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | |
| 329 | S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | |
| 330 | S_00B848_DX10_CLAMP(1) | |
| 331 | S_00B848_FLOAT_MODE(variant->config.float_mode); |
| 332 | |
| 333 | variant->bo = device->ws->buffer_create(device->ws, binary.code_size, 256, |
| 334 | RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS); |
| 335 | |
| 336 | void *ptr = device->ws->buffer_map(variant->bo); |
| 337 | memcpy(ptr, binary.code, binary.code_size); |
| 338 | device->ws->buffer_unmap(variant->bo); |
| 339 | |
| 340 | if (code_out) { |
| 341 | *code_out = binary.code; |
| 342 | *code_size_out = binary.code_size; |
| 343 | } else |
| 344 | free(binary.code); |
| 345 | free(binary.config); |
| 346 | free(binary.rodata); |
| 347 | free(binary.global_symbol_offsets); |
| 348 | free(binary.relocs); |
| 349 | free(binary.disasm_string); |
| 350 | variant->ref_count = 1; |
| 351 | return variant; |
| 352 | } |
| 353 | |
| 354 | |
| 355 | static struct radv_shader_variant * |
| 356 | radv_pipeline_compile(struct radv_pipeline *pipeline, |
| 357 | struct radv_pipeline_cache *cache, |
| 358 | struct radv_shader_module *module, |
| 359 | const char *entrypoint, |
| 360 | gl_shader_stage stage, |
| 361 | const VkSpecializationInfo *spec_info, |
| 362 | struct radv_pipeline_layout *layout, |
| 363 | const union ac_shader_variant_key *key, |
| 364 | bool dump) |
| 365 | { |
| 366 | unsigned char sha1[20]; |
| 367 | struct radv_shader_variant *variant; |
| 368 | nir_shader *nir; |
| 369 | void *code = NULL; |
Grigori Goronzy | 0b539ab | 2016-10-12 00:47:19 +0200 | [diff] [blame] | 370 | unsigned code_size = 0; |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 371 | |
| 372 | if (module->nir) |
| 373 | _mesa_sha1_compute(module->nir->info.name, |
| 374 | strlen(module->nir->info.name), |
| 375 | module->sha1); |
| 376 | |
| 377 | radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key); |
| 378 | |
| 379 | if (cache) { |
| 380 | variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device, |
| 381 | cache, |
| 382 | sha1); |
| 383 | if (variant) |
| 384 | return variant; |
| 385 | } |
| 386 | |
| 387 | nir = radv_shader_compile_to_nir(pipeline->device, |
| 388 | module, entrypoint, stage, |
| 389 | spec_info, dump); |
| 390 | if (nir == NULL) |
| 391 | return NULL; |
| 392 | |
| 393 | variant = radv_shader_variant_create(pipeline->device, nir, layout, key, |
| 394 | &code, &code_size, dump); |
| 395 | if (!module->nir) |
| 396 | ralloc_free(nir); |
| 397 | |
| 398 | if (variant && cache) |
| 399 | variant = radv_pipeline_cache_insert_shader(cache, sha1, variant, |
| 400 | code, code_size); |
| 401 | |
| 402 | if (code) |
| 403 | free(code); |
| 404 | return variant; |
| 405 | } |
| 406 | |
| 407 | static uint32_t si_translate_blend_function(VkBlendOp op) |
| 408 | { |
| 409 | switch (op) { |
| 410 | case VK_BLEND_OP_ADD: |
| 411 | return V_028780_COMB_DST_PLUS_SRC; |
| 412 | case VK_BLEND_OP_SUBTRACT: |
| 413 | return V_028780_COMB_SRC_MINUS_DST; |
| 414 | case VK_BLEND_OP_REVERSE_SUBTRACT: |
| 415 | return V_028780_COMB_DST_MINUS_SRC; |
| 416 | case VK_BLEND_OP_MIN: |
| 417 | return V_028780_COMB_MIN_DST_SRC; |
| 418 | case VK_BLEND_OP_MAX: |
| 419 | return V_028780_COMB_MAX_DST_SRC; |
| 420 | default: |
| 421 | return 0; |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | static uint32_t si_translate_blend_factor(VkBlendFactor factor) |
| 426 | { |
| 427 | switch (factor) { |
| 428 | case VK_BLEND_FACTOR_ZERO: |
| 429 | return V_028780_BLEND_ZERO; |
| 430 | case VK_BLEND_FACTOR_ONE: |
| 431 | return V_028780_BLEND_ONE; |
| 432 | case VK_BLEND_FACTOR_SRC_COLOR: |
| 433 | return V_028780_BLEND_SRC_COLOR; |
| 434 | case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR: |
| 435 | return V_028780_BLEND_ONE_MINUS_SRC_COLOR; |
| 436 | case VK_BLEND_FACTOR_DST_COLOR: |
| 437 | return V_028780_BLEND_DST_COLOR; |
| 438 | case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR: |
| 439 | return V_028780_BLEND_ONE_MINUS_DST_COLOR; |
| 440 | case VK_BLEND_FACTOR_SRC_ALPHA: |
| 441 | return V_028780_BLEND_SRC_ALPHA; |
| 442 | case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA: |
| 443 | return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; |
| 444 | case VK_BLEND_FACTOR_DST_ALPHA: |
| 445 | return V_028780_BLEND_DST_ALPHA; |
| 446 | case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA: |
| 447 | return V_028780_BLEND_ONE_MINUS_DST_ALPHA; |
| 448 | case VK_BLEND_FACTOR_CONSTANT_COLOR: |
| 449 | return V_028780_BLEND_CONSTANT_COLOR; |
| 450 | case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR: |
| 451 | return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; |
| 452 | case VK_BLEND_FACTOR_CONSTANT_ALPHA: |
| 453 | return V_028780_BLEND_CONSTANT_ALPHA; |
| 454 | case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA: |
| 455 | return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; |
| 456 | case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE: |
| 457 | return V_028780_BLEND_SRC_ALPHA_SATURATE; |
| 458 | case VK_BLEND_FACTOR_SRC1_COLOR: |
| 459 | return V_028780_BLEND_SRC1_COLOR; |
| 460 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: |
| 461 | return V_028780_BLEND_INV_SRC1_COLOR; |
| 462 | case VK_BLEND_FACTOR_SRC1_ALPHA: |
| 463 | return V_028780_BLEND_SRC1_ALPHA; |
| 464 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: |
| 465 | return V_028780_BLEND_INV_SRC1_ALPHA; |
| 466 | default: |
| 467 | return 0; |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | static bool is_dual_src(VkBlendFactor factor) |
| 472 | { |
| 473 | switch (factor) { |
| 474 | case VK_BLEND_FACTOR_SRC1_COLOR: |
| 475 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: |
| 476 | case VK_BLEND_FACTOR_SRC1_ALPHA: |
| 477 | case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: |
| 478 | return true; |
| 479 | default: |
| 480 | return false; |
| 481 | } |
| 482 | } |
| 483 | |
| 484 | static unsigned si_choose_spi_color_format(VkFormat vk_format, |
| 485 | bool blend_enable, |
| 486 | bool blend_need_alpha) |
| 487 | { |
| 488 | const struct vk_format_description *desc = vk_format_description(vk_format); |
| 489 | unsigned format, ntype, swap; |
| 490 | |
| 491 | /* Alpha is needed for alpha-to-coverage. |
| 492 | * Blending may be with or without alpha. |
| 493 | */ |
| 494 | unsigned normal = 0; /* most optimal, may not support blending or export alpha */ |
| 495 | unsigned alpha = 0; /* exports alpha, but may not support blending */ |
| 496 | unsigned blend = 0; /* supports blending, but may not export alpha */ |
| 497 | unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ |
| 498 | |
| 499 | format = radv_translate_colorformat(vk_format); |
| 500 | ntype = radv_translate_color_numformat(vk_format, desc, |
| 501 | vk_format_get_first_non_void_channel(vk_format)); |
| 502 | swap = radv_translate_colorswap(vk_format, false); |
| 503 | |
| 504 | /* Choose the SPI color formats. These are required values for Stoney/RB+. |
| 505 | * Other chips have multiple choices, though they are not necessarily better. |
| 506 | */ |
| 507 | switch (format) { |
| 508 | case V_028C70_COLOR_5_6_5: |
| 509 | case V_028C70_COLOR_1_5_5_5: |
| 510 | case V_028C70_COLOR_5_5_5_1: |
| 511 | case V_028C70_COLOR_4_4_4_4: |
| 512 | case V_028C70_COLOR_10_11_11: |
| 513 | case V_028C70_COLOR_11_11_10: |
| 514 | case V_028C70_COLOR_8: |
| 515 | case V_028C70_COLOR_8_8: |
| 516 | case V_028C70_COLOR_8_8_8_8: |
| 517 | case V_028C70_COLOR_10_10_10_2: |
| 518 | case V_028C70_COLOR_2_10_10_10: |
| 519 | if (ntype == V_028C70_NUMBER_UINT) |
| 520 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; |
| 521 | else if (ntype == V_028C70_NUMBER_SINT) |
| 522 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; |
| 523 | else |
| 524 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; |
| 525 | break; |
| 526 | |
| 527 | case V_028C70_COLOR_16: |
| 528 | case V_028C70_COLOR_16_16: |
| 529 | case V_028C70_COLOR_16_16_16_16: |
| 530 | if (ntype == V_028C70_NUMBER_UNORM || |
| 531 | ntype == V_028C70_NUMBER_SNORM) { |
| 532 | /* UNORM16 and SNORM16 don't support blending */ |
| 533 | if (ntype == V_028C70_NUMBER_UNORM) |
| 534 | normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; |
| 535 | else |
| 536 | normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; |
| 537 | |
| 538 | /* Use 32 bits per channel for blending. */ |
| 539 | if (format == V_028C70_COLOR_16) { |
| 540 | if (swap == V_028C70_SWAP_STD) { /* R */ |
| 541 | blend = V_028714_SPI_SHADER_32_R; |
| 542 | blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 543 | } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ |
| 544 | blend = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 545 | else |
| 546 | assert(0); |
| 547 | } else if (format == V_028C70_COLOR_16_16) { |
| 548 | if (swap == V_028C70_SWAP_STD) { /* RG */ |
| 549 | blend = V_028714_SPI_SHADER_32_GR; |
| 550 | blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 551 | } else if (swap == V_028C70_SWAP_ALT) /* RA */ |
| 552 | blend = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 553 | else |
| 554 | assert(0); |
| 555 | } else /* 16_16_16_16 */ |
| 556 | blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 557 | } else if (ntype == V_028C70_NUMBER_UINT) |
| 558 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; |
| 559 | else if (ntype == V_028C70_NUMBER_SINT) |
| 560 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; |
| 561 | else if (ntype == V_028C70_NUMBER_FLOAT) |
| 562 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; |
| 563 | else |
| 564 | assert(0); |
| 565 | break; |
| 566 | |
| 567 | case V_028C70_COLOR_32: |
| 568 | if (swap == V_028C70_SWAP_STD) { /* R */ |
| 569 | blend = normal = V_028714_SPI_SHADER_32_R; |
| 570 | alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; |
| 571 | } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ |
| 572 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; |
| 573 | else |
| 574 | assert(0); |
| 575 | break; |
| 576 | |
| 577 | case V_028C70_COLOR_32_32: |
| 578 | if (swap == V_028C70_SWAP_STD) { /* RG */ |
| 579 | blend = normal = V_028714_SPI_SHADER_32_GR; |
| 580 | alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; |
| 581 | } else if (swap == V_028C70_SWAP_ALT) /* RA */ |
| 582 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; |
| 583 | else |
| 584 | assert(0); |
| 585 | break; |
| 586 | |
| 587 | case V_028C70_COLOR_32_32_32_32: |
| 588 | case V_028C70_COLOR_8_24: |
| 589 | case V_028C70_COLOR_24_8: |
| 590 | case V_028C70_COLOR_X24_8_32_FLOAT: |
| 591 | alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; |
| 592 | break; |
| 593 | |
| 594 | default: |
| 595 | unreachable("unhandled blend format"); |
| 596 | } |
| 597 | |
| 598 | if (blend_enable && blend_need_alpha) |
| 599 | return blend_alpha; |
| 600 | else if(blend_need_alpha) |
| 601 | return alpha; |
| 602 | else if(blend_enable) |
| 603 | return blend; |
| 604 | else |
| 605 | return normal; |
| 606 | } |
| 607 | |
| 608 | static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format) |
| 609 | { |
| 610 | unsigned i, cb_shader_mask = 0; |
| 611 | |
| 612 | for (i = 0; i < 8; i++) { |
| 613 | switch ((spi_shader_col_format >> (i * 4)) & 0xf) { |
| 614 | case V_028714_SPI_SHADER_ZERO: |
| 615 | break; |
| 616 | case V_028714_SPI_SHADER_32_R: |
| 617 | cb_shader_mask |= 0x1 << (i * 4); |
| 618 | break; |
| 619 | case V_028714_SPI_SHADER_32_GR: |
| 620 | cb_shader_mask |= 0x3 << (i * 4); |
| 621 | break; |
| 622 | case V_028714_SPI_SHADER_32_AR: |
| 623 | cb_shader_mask |= 0x9 << (i * 4); |
| 624 | break; |
| 625 | case V_028714_SPI_SHADER_FP16_ABGR: |
| 626 | case V_028714_SPI_SHADER_UNORM16_ABGR: |
| 627 | case V_028714_SPI_SHADER_SNORM16_ABGR: |
| 628 | case V_028714_SPI_SHADER_UINT16_ABGR: |
| 629 | case V_028714_SPI_SHADER_SINT16_ABGR: |
| 630 | case V_028714_SPI_SHADER_32_ABGR: |
| 631 | cb_shader_mask |= 0xf << (i * 4); |
| 632 | break; |
| 633 | default: |
| 634 | assert(0); |
| 635 | } |
| 636 | } |
| 637 | return cb_shader_mask; |
| 638 | } |
| 639 | |
| 640 | static void |
| 641 | radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, |
| 642 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 643 | uint32_t blend_enable, |
| 644 | uint32_t blend_need_alpha, |
| 645 | bool single_cb_enable) |
| 646 | { |
| 647 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 648 | struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; |
| 649 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 650 | unsigned col_format = 0; |
| 651 | |
| 652 | for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) { |
| 653 | struct radv_render_pass_attachment *attachment; |
| 654 | unsigned cf; |
| 655 | |
| 656 | attachment = pass->attachments + subpass->color_attachments[i].attachment; |
| 657 | |
| 658 | cf = si_choose_spi_color_format(attachment->format, |
| 659 | blend_enable & (1 << i), |
| 660 | blend_need_alpha & (1 << i)); |
| 661 | |
| 662 | col_format |= cf << (4 * i); |
| 663 | } |
| 664 | |
| 665 | blend->cb_shader_mask = si_get_cb_shader_mask(col_format); |
| 666 | |
| 667 | if (!col_format) |
| 668 | col_format |= V_028714_SPI_SHADER_32_R; |
| 669 | blend->spi_shader_col_format = col_format; |
| 670 | } |
| 671 | |
| 672 | static bool |
| 673 | format_is_int8(VkFormat format) |
| 674 | { |
| 675 | const struct vk_format_description *desc = vk_format_description(format); |
| 676 | int channel = vk_format_get_first_non_void_channel(format); |
| 677 | |
| 678 | return channel >= 0 && desc->channel[channel].pure_integer && |
| 679 | desc->channel[channel].size == 8; |
| 680 | } |
| 681 | |
| 682 | unsigned radv_format_meta_fs_key(VkFormat format) |
| 683 | { |
| 684 | unsigned col_format = si_choose_spi_color_format(format, false, false) - 1; |
| 685 | bool is_int8 = format_is_int8(format); |
| 686 | |
| 687 | return col_format + (is_int8 ? 3 : 0); |
| 688 | } |
| 689 | |
| 690 | static unsigned |
| 691 | radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 692 | { |
| 693 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 694 | struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; |
| 695 | unsigned is_int8 = 0; |
| 696 | |
| 697 | for (unsigned i = 0; i < subpass->color_count; ++i) { |
| 698 | struct radv_render_pass_attachment *attachment; |
| 699 | |
| 700 | attachment = pass->attachments + subpass->color_attachments[i].attachment; |
| 701 | |
| 702 | if (format_is_int8(attachment->format)) |
| 703 | is_int8 |= 1 << i; |
| 704 | } |
| 705 | |
| 706 | return is_int8; |
| 707 | } |
| 708 | |
| 709 | static void |
| 710 | radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, |
| 711 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 712 | const struct radv_graphics_pipeline_create_info *extra) |
| 713 | { |
| 714 | const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; |
| 715 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 716 | unsigned mode = V_028808_CB_NORMAL; |
| 717 | uint32_t blend_enable = 0, blend_need_alpha = 0; |
| 718 | int i; |
| 719 | bool single_cb_enable = false; |
| 720 | if (extra && extra->custom_blend_mode) { |
| 721 | single_cb_enable = true; |
| 722 | mode = extra->custom_blend_mode; |
| 723 | } |
| 724 | blend->cb_color_control = 0; |
| 725 | if (vkblend->logicOpEnable) |
| 726 | blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4)); |
| 727 | else |
| 728 | blend->cb_color_control |= S_028808_ROP3(0xcc); |
| 729 | |
| 730 | blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | |
| 731 | S_028B70_ALPHA_TO_MASK_OFFSET1(2) | |
| 732 | S_028B70_ALPHA_TO_MASK_OFFSET2(2) | |
| 733 | S_028B70_ALPHA_TO_MASK_OFFSET3(2); |
| 734 | |
| 735 | blend->cb_target_mask = 0; |
| 736 | for (i = 0; i < vkblend->attachmentCount; i++) { |
| 737 | const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i]; |
| 738 | unsigned blend_cntl = 0; |
| 739 | VkBlendOp eqRGB = att->colorBlendOp; |
| 740 | VkBlendFactor srcRGB = att->srcColorBlendFactor; |
| 741 | VkBlendFactor dstRGB = att->dstColorBlendFactor; |
| 742 | VkBlendOp eqA = att->alphaBlendOp; |
| 743 | VkBlendFactor srcA = att->srcAlphaBlendFactor; |
| 744 | VkBlendFactor dstA = att->dstAlphaBlendFactor; |
| 745 | |
| 746 | blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); |
| 747 | |
| 748 | if (!att->colorWriteMask) |
| 749 | continue; |
| 750 | |
| 751 | blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); |
| 752 | if (!att->blendEnable) { |
| 753 | blend->cb_blend_control[i] = blend_cntl; |
| 754 | continue; |
| 755 | } |
| 756 | |
| 757 | if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA)) |
| 758 | radv_finishme("dual source blending"); |
| 759 | if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) { |
| 760 | srcRGB = VK_BLEND_FACTOR_ONE; |
| 761 | dstRGB = VK_BLEND_FACTOR_ONE; |
| 762 | } |
| 763 | if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) { |
| 764 | srcA = VK_BLEND_FACTOR_ONE; |
| 765 | dstA = VK_BLEND_FACTOR_ONE; |
| 766 | } |
| 767 | |
| 768 | blend_cntl |= S_028780_ENABLE(1); |
| 769 | |
| 770 | blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); |
| 771 | blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); |
| 772 | blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); |
| 773 | if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { |
| 774 | blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); |
| 775 | blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); |
| 776 | blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); |
| 777 | blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); |
| 778 | } |
| 779 | blend->cb_blend_control[i] = blend_cntl; |
| 780 | |
| 781 | blend_enable |= 1 << i; |
| 782 | |
| 783 | if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA || |
| 784 | dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || |
| 785 | srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || |
| 786 | dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || |
| 787 | srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA || |
| 788 | dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
| 789 | blend_need_alpha |= 1 << i; |
| 790 | } |
| 791 | for (i = vkblend->attachmentCount; i < 8; i++) |
| 792 | blend->cb_blend_control[i] = 0; |
| 793 | |
| 794 | if (blend->cb_target_mask) |
| 795 | blend->cb_color_control |= S_028808_MODE(mode); |
| 796 | else |
| 797 | blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE); |
| 798 | |
| 799 | radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, |
| 800 | blend_enable, blend_need_alpha, single_cb_enable); |
| 801 | } |
| 802 | |
| 803 | static uint32_t si_translate_stencil_op(enum VkStencilOp op) |
| 804 | { |
| 805 | switch (op) { |
| 806 | case VK_STENCIL_OP_KEEP: |
| 807 | return V_02842C_STENCIL_KEEP; |
| 808 | case VK_STENCIL_OP_ZERO: |
| 809 | return V_02842C_STENCIL_ZERO; |
| 810 | case VK_STENCIL_OP_REPLACE: |
| 811 | return V_02842C_STENCIL_REPLACE_TEST; |
| 812 | case VK_STENCIL_OP_INCREMENT_AND_CLAMP: |
| 813 | return V_02842C_STENCIL_ADD_CLAMP; |
| 814 | case VK_STENCIL_OP_DECREMENT_AND_CLAMP: |
| 815 | return V_02842C_STENCIL_SUB_CLAMP; |
| 816 | case VK_STENCIL_OP_INVERT: |
| 817 | return V_02842C_STENCIL_INVERT; |
| 818 | case VK_STENCIL_OP_INCREMENT_AND_WRAP: |
| 819 | return V_02842C_STENCIL_ADD_WRAP; |
| 820 | case VK_STENCIL_OP_DECREMENT_AND_WRAP: |
| 821 | return V_02842C_STENCIL_SUB_WRAP; |
| 822 | default: |
| 823 | return 0; |
| 824 | } |
| 825 | } |
| 826 | static void |
| 827 | radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline, |
| 828 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 829 | const struct radv_graphics_pipeline_create_info *extra) |
| 830 | { |
| 831 | const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState; |
| 832 | struct radv_depth_stencil_state *ds = &pipeline->graphics.ds; |
| 833 | |
| 834 | memset(ds, 0, sizeof(*ds)); |
| 835 | if (!vkds) |
| 836 | return; |
| 837 | ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) | |
| 838 | S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) | |
| 839 | S_028800_ZFUNC(vkds->depthCompareOp) | |
| 840 | S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0); |
| 841 | |
| 842 | if (vkds->stencilTestEnable) { |
| 843 | ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1); |
| 844 | ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp); |
| 845 | ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp)); |
| 846 | ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp)); |
| 847 | ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp)); |
| 848 | |
| 849 | ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp); |
| 850 | ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp)); |
| 851 | ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp)); |
| 852 | ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp)); |
| 853 | } |
| 854 | |
| 855 | if (extra) { |
| 856 | |
| 857 | ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); |
| 858 | ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); |
| 859 | |
| 860 | ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize); |
| 861 | ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace); |
| 862 | ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace); |
| 863 | ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear); |
| 864 | ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear); |
| 865 | } |
| 866 | } |
| 867 | |
| 868 | static uint32_t si_translate_fill(VkPolygonMode func) |
| 869 | { |
| 870 | switch(func) { |
| 871 | case VK_POLYGON_MODE_FILL: |
| 872 | return V_028814_X_DRAW_TRIANGLES; |
| 873 | case VK_POLYGON_MODE_LINE: |
| 874 | return V_028814_X_DRAW_LINES; |
| 875 | case VK_POLYGON_MODE_POINT: |
| 876 | return V_028814_X_DRAW_POINTS; |
| 877 | default: |
| 878 | assert(0); |
| 879 | return V_028814_X_DRAW_POINTS; |
| 880 | } |
| 881 | } |
| 882 | static void |
| 883 | radv_pipeline_init_raster_state(struct radv_pipeline *pipeline, |
| 884 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 885 | { |
| 886 | const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; |
| 887 | struct radv_raster_state *raster = &pipeline->graphics.raster; |
| 888 | |
| 889 | memset(raster, 0, sizeof(*raster)); |
| 890 | |
| 891 | raster->spi_interp_control = |
| 892 | S_0286D4_FLAT_SHADE_ENA(1) | |
| 893 | S_0286D4_PNT_SPRITE_ENA(1) | |
| 894 | S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | |
| 895 | S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | |
| 896 | S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | |
| 897 | S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | |
| 898 | S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom |
| 899 | |
| 900 | raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1); |
| 901 | raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) | |
| 902 | S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions. |
| 903 | S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | |
| 904 | S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | |
| 905 | S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) | |
| 906 | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); |
| 907 | |
| 908 | raster->pa_su_vtx_cntl = |
| 909 | S_028BE4_PIX_CENTER(1) | // TODO verify |
| 910 | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) | |
| 911 | S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH); |
| 912 | |
| 913 | raster->pa_su_sc_mode_cntl = |
| 914 | S_028814_FACE(vkraster->frontFace) | |
| 915 | S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) | |
| 916 | S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) | |
| 917 | S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) | |
| 918 | S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) | |
| 919 | S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) | |
| 920 | S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | |
| 921 | S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | |
| 922 | S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0); |
| 923 | |
| 924 | } |
| 925 | |
| 926 | static void |
| 927 | radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, |
| 928 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 929 | { |
| 930 | const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; |
| 931 | struct radv_blend_state *blend = &pipeline->graphics.blend; |
| 932 | struct radv_multisample_state *ms = &pipeline->graphics.ms; |
| 933 | unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes; |
| 934 | int ps_iter_samples = 1; |
| 935 | uint32_t mask = 0xffff; |
| 936 | |
| 937 | ms->num_samples = vkms->rasterizationSamples; |
| 938 | ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1); |
| 939 | ms->pa_sc_aa_config = 0; |
| 940 | ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | |
| 941 | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); |
| 942 | ms->pa_sc_mode_cntl_1 = |
| 943 | S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes |
| 944 | S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | |
| 945 | /* always 1: */ |
| 946 | S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | |
| 947 | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | |
| 948 | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | |
| 949 | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | |
| 950 | EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | |
| 951 | EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1); |
| 952 | |
| 953 | if (vkms->rasterizationSamples > 1) { |
| 954 | unsigned log_samples = util_logbase2(vkms->rasterizationSamples); |
| 955 | unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples)); |
| 956 | ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1); |
| 957 | ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */ |
| 958 | ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) | |
| 959 | S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | |
| 960 | S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | |
| 961 | S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); |
| 962 | ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | |
| 963 | S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | |
| 964 | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ |
| 965 | ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); |
| 966 | } |
| 967 | |
| 968 | if (vkms->alphaToCoverageEnable) |
| 969 | blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1); |
| 970 | |
| 971 | if (vkms->pSampleMask) { |
| 972 | mask = vkms->pSampleMask[0] & 0xffff; |
| 973 | } |
| 974 | |
| 975 | ms->pa_sc_aa_mask[0] = mask | (mask << 16); |
| 976 | ms->pa_sc_aa_mask[1] = mask | (mask << 16); |
| 977 | } |
| 978 | |
| 979 | static uint32_t |
| 980 | si_translate_prim(enum VkPrimitiveTopology topology) |
| 981 | { |
| 982 | switch (topology) { |
| 983 | case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: |
| 984 | return V_008958_DI_PT_POINTLIST; |
| 985 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: |
| 986 | return V_008958_DI_PT_LINELIST; |
| 987 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: |
| 988 | return V_008958_DI_PT_LINESTRIP; |
| 989 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: |
| 990 | return V_008958_DI_PT_TRILIST; |
| 991 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: |
| 992 | return V_008958_DI_PT_TRISTRIP; |
| 993 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: |
| 994 | return V_008958_DI_PT_TRIFAN; |
| 995 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: |
| 996 | return V_008958_DI_PT_LINELIST_ADJ; |
| 997 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: |
| 998 | return V_008958_DI_PT_LINESTRIP_ADJ; |
| 999 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: |
| 1000 | return V_008958_DI_PT_TRILIST_ADJ; |
| 1001 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: |
| 1002 | return V_008958_DI_PT_TRISTRIP_ADJ; |
| 1003 | case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: |
| 1004 | return V_008958_DI_PT_PATCH; |
| 1005 | default: |
| 1006 | assert(0); |
| 1007 | return 0; |
| 1008 | } |
| 1009 | } |
| 1010 | |
| 1011 | static uint32_t |
| 1012 | si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology) |
| 1013 | { |
| 1014 | switch (topology) { |
| 1015 | case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: |
| 1016 | case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: |
| 1017 | return V_028A6C_OUTPRIM_TYPE_POINTLIST; |
| 1018 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: |
| 1019 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: |
| 1020 | case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: |
| 1021 | case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: |
| 1022 | return V_028A6C_OUTPRIM_TYPE_LINESTRIP; |
| 1023 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: |
| 1024 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: |
| 1025 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: |
| 1026 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: |
| 1027 | case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: |
| 1028 | return V_028A6C_OUTPRIM_TYPE_TRISTRIP; |
| 1029 | default: |
| 1030 | assert(0); |
| 1031 | return 0; |
| 1032 | } |
| 1033 | } |
| 1034 | |
| 1035 | static unsigned si_map_swizzle(unsigned swizzle) |
| 1036 | { |
| 1037 | switch (swizzle) { |
| 1038 | case VK_SWIZZLE_Y: |
| 1039 | return V_008F0C_SQ_SEL_Y; |
| 1040 | case VK_SWIZZLE_Z: |
| 1041 | return V_008F0C_SQ_SEL_Z; |
| 1042 | case VK_SWIZZLE_W: |
| 1043 | return V_008F0C_SQ_SEL_W; |
| 1044 | case VK_SWIZZLE_0: |
| 1045 | return V_008F0C_SQ_SEL_0; |
| 1046 | case VK_SWIZZLE_1: |
| 1047 | return V_008F0C_SQ_SEL_1; |
| 1048 | default: /* VK_SWIZZLE_X */ |
| 1049 | return V_008F0C_SQ_SEL_X; |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | static void |
| 1054 | radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, |
| 1055 | const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 1056 | { |
| 1057 | radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL; |
| 1058 | RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); |
| 1059 | struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; |
| 1060 | |
| 1061 | pipeline->dynamic_state = default_dynamic_state; |
| 1062 | |
| 1063 | if (pCreateInfo->pDynamicState) { |
| 1064 | /* Remove all of the states that are marked as dynamic */ |
| 1065 | uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount; |
| 1066 | for (uint32_t s = 0; s < count; s++) |
| 1067 | states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]); |
| 1068 | } |
| 1069 | |
| 1070 | struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; |
| 1071 | |
| 1072 | dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount; |
| 1073 | if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) { |
| 1074 | typed_memcpy(dynamic->viewport.viewports, |
| 1075 | pCreateInfo->pViewportState->pViewports, |
| 1076 | pCreateInfo->pViewportState->viewportCount); |
| 1077 | } |
| 1078 | |
| 1079 | dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount; |
| 1080 | if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) { |
| 1081 | typed_memcpy(dynamic->scissor.scissors, |
| 1082 | pCreateInfo->pViewportState->pScissors, |
| 1083 | pCreateInfo->pViewportState->scissorCount); |
| 1084 | } |
| 1085 | |
| 1086 | if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) { |
| 1087 | assert(pCreateInfo->pRasterizationState); |
| 1088 | dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth; |
| 1089 | } |
| 1090 | |
| 1091 | if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) { |
| 1092 | assert(pCreateInfo->pRasterizationState); |
| 1093 | dynamic->depth_bias.bias = |
| 1094 | pCreateInfo->pRasterizationState->depthBiasConstantFactor; |
| 1095 | dynamic->depth_bias.clamp = |
| 1096 | pCreateInfo->pRasterizationState->depthBiasClamp; |
| 1097 | dynamic->depth_bias.slope = |
| 1098 | pCreateInfo->pRasterizationState->depthBiasSlopeFactor; |
| 1099 | } |
| 1100 | |
| 1101 | if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) { |
| 1102 | assert(pCreateInfo->pColorBlendState); |
| 1103 | typed_memcpy(dynamic->blend_constants, |
| 1104 | pCreateInfo->pColorBlendState->blendConstants, 4); |
| 1105 | } |
| 1106 | |
| 1107 | /* If there is no depthstencil attachment, then don't read |
| 1108 | * pDepthStencilState. The Vulkan spec states that pDepthStencilState may |
| 1109 | * be NULL in this case. Even if pDepthStencilState is non-NULL, there is |
| 1110 | * no need to override the depthstencil defaults in |
| 1111 | * radv_pipeline::dynamic_state when there is no depthstencil attachment. |
| 1112 | * |
| 1113 | * From the Vulkan spec (20 Oct 2015, git-aa308cb): |
| 1114 | * |
| 1115 | * pDepthStencilState [...] may only be NULL if renderPass and subpass |
| 1116 | * specify a subpass that has no depth/stencil attachment. |
| 1117 | */ |
| 1118 | if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { |
| 1119 | if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) { |
| 1120 | assert(pCreateInfo->pDepthStencilState); |
| 1121 | dynamic->depth_bounds.min = |
| 1122 | pCreateInfo->pDepthStencilState->minDepthBounds; |
| 1123 | dynamic->depth_bounds.max = |
| 1124 | pCreateInfo->pDepthStencilState->maxDepthBounds; |
| 1125 | } |
| 1126 | |
| 1127 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) { |
| 1128 | assert(pCreateInfo->pDepthStencilState); |
| 1129 | dynamic->stencil_compare_mask.front = |
| 1130 | pCreateInfo->pDepthStencilState->front.compareMask; |
| 1131 | dynamic->stencil_compare_mask.back = |
| 1132 | pCreateInfo->pDepthStencilState->back.compareMask; |
| 1133 | } |
| 1134 | |
| 1135 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) { |
| 1136 | assert(pCreateInfo->pDepthStencilState); |
| 1137 | dynamic->stencil_write_mask.front = |
| 1138 | pCreateInfo->pDepthStencilState->front.writeMask; |
| 1139 | dynamic->stencil_write_mask.back = |
| 1140 | pCreateInfo->pDepthStencilState->back.writeMask; |
| 1141 | } |
| 1142 | |
| 1143 | if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) { |
| 1144 | assert(pCreateInfo->pDepthStencilState); |
| 1145 | dynamic->stencil_reference.front = |
| 1146 | pCreateInfo->pDepthStencilState->front.reference; |
| 1147 | dynamic->stencil_reference.back = |
| 1148 | pCreateInfo->pDepthStencilState->back.reference; |
| 1149 | } |
| 1150 | } |
| 1151 | |
| 1152 | pipeline->dynamic_state_mask = states; |
| 1153 | } |
| 1154 | |
| 1155 | static union ac_shader_variant_key |
| 1156 | radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo) |
| 1157 | { |
| 1158 | union ac_shader_variant_key key; |
| 1159 | const VkPipelineVertexInputStateCreateInfo *input_state = |
| 1160 | pCreateInfo->pVertexInputState; |
| 1161 | |
| 1162 | memset(&key, 0, sizeof(key)); |
| 1163 | key.vs.instance_rate_inputs = 0; |
| 1164 | |
| 1165 | for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) { |
| 1166 | unsigned binding; |
| 1167 | binding = input_state->pVertexAttributeDescriptions[i].binding; |
| 1168 | if (input_state->pVertexBindingDescriptions[binding].inputRate) |
| 1169 | key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location; |
| 1170 | } |
| 1171 | return key; |
| 1172 | } |
| 1173 | |
| 1174 | VkResult |
| 1175 | radv_pipeline_init(struct radv_pipeline *pipeline, |
| 1176 | struct radv_device *device, |
| 1177 | struct radv_pipeline_cache *cache, |
| 1178 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 1179 | const struct radv_graphics_pipeline_create_info *extra, |
| 1180 | const VkAllocationCallbacks *alloc) |
| 1181 | { |
| 1182 | struct radv_shader_module fs_m = {0}; |
| 1183 | |
| 1184 | bool dump = getenv("RADV_DUMP_SHADERS"); |
| 1185 | if (alloc == NULL) |
| 1186 | alloc = &device->alloc; |
| 1187 | |
| 1188 | pipeline->device = device; |
| 1189 | pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); |
| 1190 | |
| 1191 | radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); |
| 1192 | const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; |
| 1193 | struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, }; |
| 1194 | for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { |
| 1195 | gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1; |
| 1196 | pStages[stage] = &pCreateInfo->pStages[i]; |
| 1197 | modules[stage] = radv_shader_module_from_handle(pStages[stage]->module); |
| 1198 | } |
| 1199 | |
| 1200 | radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); |
| 1201 | |
| 1202 | /* */ |
| 1203 | if (modules[MESA_SHADER_VERTEX]) { |
| 1204 | union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo); |
| 1205 | |
| 1206 | pipeline->shaders[MESA_SHADER_VERTEX] = |
| 1207 | radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX], |
| 1208 | pStages[MESA_SHADER_VERTEX]->pName, |
| 1209 | MESA_SHADER_VERTEX, |
| 1210 | pStages[MESA_SHADER_VERTEX]->pSpecializationInfo, |
| 1211 | pipeline->layout, &key, dump); |
| 1212 | |
| 1213 | pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX); |
| 1214 | } |
| 1215 | |
| 1216 | if (!modules[MESA_SHADER_FRAGMENT]) { |
| 1217 | nir_builder fs_b; |
| 1218 | nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL); |
| 1219 | fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs"); |
| 1220 | fs_m.nir = fs_b.shader; |
| 1221 | modules[MESA_SHADER_FRAGMENT] = &fs_m; |
| 1222 | } |
| 1223 | |
| 1224 | if (modules[MESA_SHADER_FRAGMENT]) { |
| 1225 | union ac_shader_variant_key key; |
| 1226 | key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format; |
| 1227 | key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo); |
| 1228 | |
| 1229 | const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT]; |
| 1230 | |
| 1231 | pipeline->shaders[MESA_SHADER_FRAGMENT] = |
| 1232 | radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT], |
| 1233 | stage ? stage->pName : "main", |
| 1234 | MESA_SHADER_FRAGMENT, |
| 1235 | stage ? stage->pSpecializationInfo : NULL, |
| 1236 | pipeline->layout, &key, dump); |
| 1237 | pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT); |
| 1238 | } |
| 1239 | |
| 1240 | if (fs_m.nir) |
| 1241 | ralloc_free(fs_m.nir); |
| 1242 | |
| 1243 | radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra); |
| 1244 | radv_pipeline_init_raster_state(pipeline, pCreateInfo); |
| 1245 | radv_pipeline_init_multisample_state(pipeline, pCreateInfo); |
| 1246 | pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology); |
| 1247 | pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); |
| 1248 | if (extra && extra->use_rectlist) { |
| 1249 | pipeline->graphics.prim = V_008958_DI_PT_RECTLIST; |
| 1250 | pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; |
| 1251 | } |
| 1252 | pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable; |
| 1253 | |
| 1254 | const VkPipelineVertexInputStateCreateInfo *vi_info = |
| 1255 | pCreateInfo->pVertexInputState; |
| 1256 | for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) { |
| 1257 | const VkVertexInputAttributeDescription *desc = |
| 1258 | &vi_info->pVertexAttributeDescriptions[i]; |
| 1259 | unsigned loc = desc->location; |
| 1260 | const struct vk_format_description *format_desc; |
| 1261 | int first_non_void; |
| 1262 | uint32_t num_format, data_format; |
| 1263 | format_desc = vk_format_description(desc->format); |
| 1264 | first_non_void = vk_format_get_first_non_void_channel(desc->format); |
| 1265 | |
| 1266 | num_format = radv_translate_buffer_numformat(format_desc, first_non_void); |
| 1267 | data_format = radv_translate_buffer_dataformat(format_desc, first_non_void); |
| 1268 | |
| 1269 | pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) | |
| 1270 | S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) | |
| 1271 | S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) | |
| 1272 | S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) | |
| 1273 | S_008F0C_NUM_FORMAT(num_format) | |
| 1274 | S_008F0C_DATA_FORMAT(data_format); |
| 1275 | pipeline->va_format_size[loc] = format_desc->block.bits / 8; |
| 1276 | pipeline->va_offset[loc] = desc->offset; |
| 1277 | pipeline->va_binding[loc] = desc->binding; |
| 1278 | pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1); |
| 1279 | } |
| 1280 | |
| 1281 | for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) { |
| 1282 | const VkVertexInputBindingDescription *desc = |
| 1283 | &vi_info->pVertexBindingDescriptions[i]; |
| 1284 | |
| 1285 | pipeline->binding_stride[desc->binding] = desc->stride; |
| 1286 | } |
| 1287 | |
| 1288 | return VK_SUCCESS; |
| 1289 | } |
| 1290 | |
| 1291 | VkResult |
| 1292 | radv_graphics_pipeline_create( |
| 1293 | VkDevice _device, |
| 1294 | VkPipelineCache _cache, |
| 1295 | const VkGraphicsPipelineCreateInfo *pCreateInfo, |
| 1296 | const struct radv_graphics_pipeline_create_info *extra, |
| 1297 | const VkAllocationCallbacks *pAllocator, |
| 1298 | VkPipeline *pPipeline) |
| 1299 | { |
| 1300 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 1301 | RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); |
| 1302 | struct radv_pipeline *pipeline; |
| 1303 | VkResult result; |
| 1304 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 1305 | pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1306 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 1307 | if (pipeline == NULL) |
| 1308 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 1309 | |
| 1310 | memset(pipeline, 0, sizeof(*pipeline)); |
| 1311 | result = radv_pipeline_init(pipeline, device, cache, |
| 1312 | pCreateInfo, extra, pAllocator); |
| 1313 | if (result != VK_SUCCESS) { |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 1314 | vk_free2(&device->alloc, pAllocator, pipeline); |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1315 | return result; |
| 1316 | } |
| 1317 | |
| 1318 | *pPipeline = radv_pipeline_to_handle(pipeline); |
| 1319 | |
| 1320 | return VK_SUCCESS; |
| 1321 | } |
| 1322 | |
| 1323 | VkResult radv_CreateGraphicsPipelines( |
| 1324 | VkDevice _device, |
| 1325 | VkPipelineCache pipelineCache, |
| 1326 | uint32_t count, |
| 1327 | const VkGraphicsPipelineCreateInfo* pCreateInfos, |
| 1328 | const VkAllocationCallbacks* pAllocator, |
| 1329 | VkPipeline* pPipelines) |
| 1330 | { |
| 1331 | VkResult result = VK_SUCCESS; |
| 1332 | unsigned i = 0; |
| 1333 | |
| 1334 | for (; i < count; i++) { |
| 1335 | result = radv_graphics_pipeline_create(_device, |
| 1336 | pipelineCache, |
| 1337 | &pCreateInfos[i], |
| 1338 | NULL, pAllocator, &pPipelines[i]); |
| 1339 | if (result != VK_SUCCESS) { |
| 1340 | for (unsigned j = 0; j < i; j++) { |
| 1341 | radv_DestroyPipeline(_device, pPipelines[j], pAllocator); |
| 1342 | } |
| 1343 | |
| 1344 | return result; |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | return VK_SUCCESS; |
| 1349 | } |
| 1350 | |
| 1351 | static VkResult radv_compute_pipeline_create( |
| 1352 | VkDevice _device, |
| 1353 | VkPipelineCache _cache, |
| 1354 | const VkComputePipelineCreateInfo* pCreateInfo, |
| 1355 | const VkAllocationCallbacks* pAllocator, |
| 1356 | VkPipeline* pPipeline) |
| 1357 | { |
| 1358 | RADV_FROM_HANDLE(radv_device, device, _device); |
| 1359 | RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); |
| 1360 | RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module); |
| 1361 | struct radv_pipeline *pipeline; |
| 1362 | bool dump = getenv("RADV_DUMP_SHADERS"); |
| 1363 | |
Dave Airlie | 4450f40 | 2016-10-14 13:36:45 +1000 | [diff] [blame^] | 1364 | pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, |
Dave Airlie | f4e499e | 2016-10-07 09:16:09 +1000 | [diff] [blame] | 1365 | VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); |
| 1366 | if (pipeline == NULL) |
| 1367 | return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); |
| 1368 | |
| 1369 | memset(pipeline, 0, sizeof(*pipeline)); |
| 1370 | pipeline->device = device; |
| 1371 | pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); |
| 1372 | |
| 1373 | pipeline->shaders[MESA_SHADER_COMPUTE] = |
| 1374 | radv_pipeline_compile(pipeline, cache, module, |
| 1375 | pCreateInfo->stage.pName, |
| 1376 | MESA_SHADER_COMPUTE, |
| 1377 | pCreateInfo->stage.pSpecializationInfo, |
| 1378 | pipeline->layout, NULL, dump); |
| 1379 | |
| 1380 | *pPipeline = radv_pipeline_to_handle(pipeline); |
| 1381 | return VK_SUCCESS; |
| 1382 | } |
| 1383 | VkResult radv_CreateComputePipelines( |
| 1384 | VkDevice _device, |
| 1385 | VkPipelineCache pipelineCache, |
| 1386 | uint32_t count, |
| 1387 | const VkComputePipelineCreateInfo* pCreateInfos, |
| 1388 | const VkAllocationCallbacks* pAllocator, |
| 1389 | VkPipeline* pPipelines) |
| 1390 | { |
| 1391 | VkResult result = VK_SUCCESS; |
| 1392 | |
| 1393 | unsigned i = 0; |
| 1394 | for (; i < count; i++) { |
| 1395 | result = radv_compute_pipeline_create(_device, pipelineCache, |
| 1396 | &pCreateInfos[i], |
| 1397 | pAllocator, &pPipelines[i]); |
| 1398 | if (result != VK_SUCCESS) { |
| 1399 | for (unsigned j = 0; j < i; j++) { |
| 1400 | radv_DestroyPipeline(_device, pPipelines[j], pAllocator); |
| 1401 | } |
| 1402 | |
| 1403 | return result; |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | return VK_SUCCESS; |
| 1408 | } |