Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2020 Collabora Ltd. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors (Collabora): |
| 24 | * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> |
| 25 | */ |
| 26 | |
| 27 | #ifndef __BIFROST_COMPILER_H |
| 28 | #define __BIFROST_COMPILER_H |
| 29 | |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame^] | 30 | #include "compiler/nir/nir.h" |
| 31 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 32 | /* Bifrost opcodes are tricky -- the same op may exist on both FMA and |
| 33 | * ADD with two completely different opcodes, and opcodes can be varying |
| 34 | * length in some cases. Then we have different opcodes for int vs float |
| 35 | * and then sometimes even for different typesizes. Further, virtually |
| 36 | * every op has a number of flags which depend on the op. In constrast |
| 37 | * to Midgard where you have a strict ALU/LDST/TEX division and within |
| 38 | * ALU you have strict int/float and that's it... here it's a *lot* more |
| 39 | * involved. As such, we use something much higher level for our IR, |
| 40 | * encoding "classes" of operations, letting the opcode details get |
| 41 | * sorted out at emit time. |
| 42 | * |
| 43 | * Please keep this list alphabetized. Please use a dictionary if you |
| 44 | * don't know how to do that. |
| 45 | */ |
| 46 | |
| 47 | enum bi_class { |
| 48 | BI_ADD, |
| 49 | BI_ATEST, |
| 50 | BI_BRANCH, |
| 51 | BI_CMP, |
| 52 | BI_BLEND, |
| 53 | BI_BITWISE, |
| 54 | BI_CONVERT, |
| 55 | BI_CSEL, |
| 56 | BI_DISCARD, |
| 57 | BI_FMA, |
| 58 | BI_FREXP, |
| 59 | BI_LOAD, |
| 60 | BI_LOAD_ATTR, |
| 61 | BI_LOAD_VAR, |
| 62 | BI_LOAD_VAR_ADDRESS, |
| 63 | BI_MINMAX, |
| 64 | BI_MOV, |
| 65 | BI_SHIFT, |
| 66 | BI_STORE, |
| 67 | BI_STORE_VAR, |
| 68 | BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */ |
| 69 | BI_TEX, |
| 70 | BI_ROUND, |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame^] | 71 | BI_NUM_CLASSES |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 72 | }; |
| 73 | |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame^] | 74 | /* Properties of a class... */ |
| 75 | extern unsigned bi_class_props[BI_NUM_CLASSES]; |
| 76 | |
| 77 | /* abs/neg/outmod valid for a float op */ |
| 78 | #define BI_MODS (1 << 0) |
| 79 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 80 | /* It can't get any worse than csel4... can it? */ |
| 81 | #define BIR_SRC_COUNT 4 |
| 82 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 83 | typedef struct { |
| 84 | struct list_head link; /* Must be first */ |
| 85 | enum bi_class type; |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 86 | |
| 87 | /* Indices, see bir_ssa_index etc. Note zero is special cased |
| 88 | * to "no argument" */ |
| 89 | unsigned dest; |
| 90 | unsigned src[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 91 | } bi_instruction; |
| 92 | |
| 93 | typedef struct { |
| 94 | struct list_head link; /* must be first */ |
| 95 | struct list_head instructions; /* list of bi_instructions */ |
| 96 | } bi_block; |
| 97 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 98 | typedef struct { |
| 99 | nir_shader *nir; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 100 | struct list_head blocks; /* list of bi_block */ |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 101 | } bi_context; |
| 102 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 103 | /* So we can distinguish between SSA/reg/sentinel quickly */ |
| 104 | #define BIR_NO_ARG (0) |
| 105 | #define BIR_IS_REG (1) |
| 106 | |
| 107 | static inline unsigned |
| 108 | bir_ssa_index(nir_ssa_def *ssa) |
| 109 | { |
| 110 | /* Off-by-one ensures BIR_NO_ARG is skipped */ |
| 111 | return ((ssa->index + 1) << 1) | 0; |
| 112 | } |
| 113 | |
| 114 | static inline unsigned |
| 115 | bir_src_index(nir_src *src) |
| 116 | { |
| 117 | if (src->is_ssa) |
| 118 | return bir_ssa_index(src->ssa); |
| 119 | else { |
| 120 | assert(!src->reg.indirect); |
| 121 | return (src->reg.reg->index << 1) | BIR_IS_REG; |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | static inline unsigned |
| 126 | bir_dest_index(nir_dest *dst) |
| 127 | { |
| 128 | if (dst->is_ssa) |
| 129 | return bir_ssa_index(&dst->ssa); |
| 130 | else { |
| 131 | assert(!dst->reg.indirect); |
| 132 | return (dst->reg.reg->index << 1) | BIR_IS_REG; |
| 133 | } |
| 134 | } |
| 135 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 136 | #endif |