Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Copyright (C) 2015 Intel Corporation. All Rights Reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | ***************************************************************************/ |
| 23 | |
George Kyriazis | 974d280 | 2016-11-11 11:44:05 -0600 | [diff] [blame] | 24 | #include "swr_context.h" |
| 25 | #include "swr_public.h" |
| 26 | #include "swr_screen.h" |
| 27 | #include "swr_resource.h" |
| 28 | #include "swr_fence.h" |
| 29 | #include "gen_knobs.h" |
| 30 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 31 | #include "pipe/p_screen.h" |
| 32 | #include "pipe/p_defines.h" |
| 33 | #include "util/u_memory.h" |
| 34 | #include "util/u_format.h" |
| 35 | #include "util/u_inlines.h" |
| 36 | #include "util/u_cpu_detect.h" |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 37 | #include "util/u_format_s3tc.h" |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 38 | |
| 39 | #include "state_tracker/sw_winsys.h" |
| 40 | |
| 41 | extern "C" { |
| 42 | #include "gallivm/lp_bld_limits.h" |
| 43 | } |
| 44 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 45 | #include "jit_api.h" |
| 46 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 47 | #include "memory/TilingFunctions.h" |
| 48 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 49 | #include <stdio.h> |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 50 | #include <map> |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 51 | |
| 52 | /* MSVC case instensitive compare */ |
| 53 | #if defined(PIPE_CC_MSVC) |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 54 | #define strcasecmp lstrcmpiA |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 55 | #endif |
| 56 | |
| 57 | /* |
| 58 | * Max texture sizes |
| 59 | * XXX Check max texture size values against core and sampler. |
| 60 | */ |
Tim Rowley | 7514e32 | 2016-08-17 10:12:04 -0500 | [diff] [blame] | 61 | #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 62 | #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */ |
| 63 | #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */ |
| 64 | #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */ |
| 65 | #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */ |
| 66 | |
| 67 | static const char * |
| 68 | swr_get_name(struct pipe_screen *screen) |
| 69 | { |
| 70 | return "SWR"; |
| 71 | } |
| 72 | |
| 73 | static const char * |
| 74 | swr_get_vendor(struct pipe_screen *screen) |
| 75 | { |
| 76 | return "Intel Corporation"; |
| 77 | } |
| 78 | |
| 79 | static boolean |
| 80 | swr_is_format_supported(struct pipe_screen *screen, |
| 81 | enum pipe_format format, |
| 82 | enum pipe_texture_target target, |
| 83 | unsigned sample_count, |
| 84 | unsigned bind) |
| 85 | { |
| 86 | struct sw_winsys *winsys = swr_screen(screen)->winsys; |
| 87 | const struct util_format_description *format_desc; |
| 88 | |
| 89 | assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D |
| 90 | || target == PIPE_TEXTURE_1D_ARRAY |
| 91 | || target == PIPE_TEXTURE_2D |
| 92 | || target == PIPE_TEXTURE_2D_ARRAY |
| 93 | || target == PIPE_TEXTURE_RECT |
| 94 | || target == PIPE_TEXTURE_3D |
| 95 | || target == PIPE_TEXTURE_CUBE |
| 96 | || target == PIPE_TEXTURE_CUBE_ARRAY); |
| 97 | |
| 98 | format_desc = util_format_description(format); |
| 99 | if (!format_desc) |
| 100 | return FALSE; |
| 101 | |
| 102 | if (sample_count > 1) |
| 103 | return FALSE; |
| 104 | |
| 105 | if (bind |
| 106 | & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) { |
| 107 | if (!winsys->is_displaytarget_format_supported(winsys, bind, format)) |
| 108 | return FALSE; |
| 109 | } |
| 110 | |
| 111 | if (bind & PIPE_BIND_RENDER_TARGET) { |
| 112 | if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) |
| 113 | return FALSE; |
| 114 | |
| 115 | if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) |
| 116 | return FALSE; |
| 117 | |
| 118 | /* |
| 119 | * Although possible, it is unnatural to render into compressed or YUV |
| 120 | * surfaces. So disable these here to avoid going into weird paths |
| 121 | * inside the state trackers. |
| 122 | */ |
| 123 | if (format_desc->block.width != 1 || format_desc->block.height != 1) |
| 124 | return FALSE; |
| 125 | } |
| 126 | |
| 127 | if (bind & PIPE_BIND_DEPTH_STENCIL) { |
| 128 | if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) |
| 129 | return FALSE; |
| 130 | |
| 131 | if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) |
| 132 | return FALSE; |
| 133 | } |
| 134 | |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 135 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC || |
| 136 | format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) { |
| 137 | return FALSE; |
| 138 | } |
| 139 | |
| 140 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC && |
| 141 | format != PIPE_FORMAT_ETC1_RGB8) { |
| 142 | return FALSE; |
| 143 | } |
| 144 | |
| 145 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { |
| 146 | return util_format_s3tc_enabled; |
| 147 | } |
| 148 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 149 | return TRUE; |
| 150 | } |
| 151 | |
| 152 | static int |
| 153 | swr_get_param(struct pipe_screen *screen, enum pipe_cap param) |
| 154 | { |
| 155 | switch (param) { |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 156 | /* limits */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 157 | case PIPE_CAP_MAX_RENDER_TARGETS: |
| 158 | return PIPE_MAX_COLOR_BUFS; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 159 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: |
| 160 | return SWR_MAX_TEXTURE_2D_LEVELS; |
| 161 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: |
| 162 | return SWR_MAX_TEXTURE_3D_LEVELS; |
| 163 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: |
| 164 | return SWR_MAX_TEXTURE_CUBE_LEVELS; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 165 | case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: |
| 166 | return MAX_SO_STREAMS; |
| 167 | case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: |
| 168 | case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: |
| 169 | return MAX_ATTRIBUTES; |
| 170 | case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: |
| 171 | case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: |
| 172 | return 1024; |
| 173 | case PIPE_CAP_MAX_VERTEX_STREAMS: |
| 174 | return 1; |
| 175 | case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: |
| 176 | return 2048; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 177 | case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: |
| 178 | return SWR_MAX_TEXTURE_ARRAY_LAYERS; |
| 179 | case PIPE_CAP_MIN_TEXEL_OFFSET: |
| 180 | return -8; |
| 181 | case PIPE_CAP_MAX_TEXEL_OFFSET: |
| 182 | return 7; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 183 | case PIPE_CAP_GLSL_FEATURE_LEVEL: |
| 184 | return 330; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 185 | case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: |
| 186 | return 16; |
| 187 | case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: |
| 188 | return 64; |
| 189 | case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: |
| 190 | return 65536; |
| 191 | case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 192 | return 0; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 193 | case PIPE_CAP_MAX_VIEWPORTS: |
| 194 | return 1; |
| 195 | case PIPE_CAP_ENDIANNESS: |
| 196 | return PIPE_ENDIAN_NATIVE; |
| 197 | case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: |
| 198 | case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: |
| 199 | return 0; |
| 200 | |
| 201 | /* supported features */ |
| 202 | case PIPE_CAP_NPOT_TEXTURES: |
| 203 | case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: |
| 204 | case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: |
| 205 | case PIPE_CAP_TWO_SIDED_STENCIL: |
| 206 | case PIPE_CAP_SM3: |
| 207 | case PIPE_CAP_POINT_SPRITE: |
| 208 | case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: |
| 209 | case PIPE_CAP_OCCLUSION_QUERY: |
| 210 | case PIPE_CAP_QUERY_TIME_ELAPSED: |
| 211 | case PIPE_CAP_QUERY_PIPELINE_STATISTICS: |
| 212 | case PIPE_CAP_TEXTURE_MIRROR_CLAMP: |
| 213 | case PIPE_CAP_TEXTURE_SHADOW_MAP: |
| 214 | case PIPE_CAP_TEXTURE_SWIZZLE: |
| 215 | case PIPE_CAP_BLEND_EQUATION_SEPARATE: |
| 216 | case PIPE_CAP_INDEP_BLEND_ENABLE: |
| 217 | case PIPE_CAP_INDEP_BLEND_FUNC: |
| 218 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: |
| 219 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: |
| 220 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: |
| 221 | case PIPE_CAP_DEPTH_CLIP_DISABLE: |
| 222 | case PIPE_CAP_PRIMITIVE_RESTART: |
| 223 | case PIPE_CAP_TGSI_INSTANCEID: |
| 224 | case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: |
| 225 | case PIPE_CAP_START_INSTANCE: |
| 226 | case PIPE_CAP_SEAMLESS_CUBE_MAP: |
| 227 | case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: |
| 228 | case PIPE_CAP_CONDITIONAL_RENDER: |
| 229 | case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: |
| 230 | case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: |
| 231 | case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 232 | case PIPE_CAP_USER_VERTEX_BUFFERS: |
| 233 | case PIPE_CAP_USER_INDEX_BUFFERS: |
| 234 | case PIPE_CAP_USER_CONSTANT_BUFFERS: |
| 235 | case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: |
Ilia Mirkin | 3fdeb7c | 2016-10-14 00:03:12 -0400 | [diff] [blame] | 236 | case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 237 | case PIPE_CAP_QUERY_TIMESTAMP: |
| 238 | case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: |
| 239 | case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: |
| 240 | case PIPE_CAP_FAKE_SW_MSAA: |
| 241 | case PIPE_CAP_DRAW_INDIRECT: |
| 242 | case PIPE_CAP_UMA: |
| 243 | case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: |
| 244 | case PIPE_CAP_CLIP_HALFZ: |
| 245 | case PIPE_CAP_POLYGON_OFFSET_CLAMP: |
| 246 | case PIPE_CAP_DEPTH_BOUNDS_TEST: |
| 247 | case PIPE_CAP_TEXTURE_FLOAT_LINEAR: |
| 248 | case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: |
| 249 | case PIPE_CAP_CULL_DISTANCE: |
Ilia Mirkin | 86f7932 | 2016-11-20 13:33:04 -0500 | [diff] [blame^] | 250 | case PIPE_CAP_CUBE_MAP_ARRAY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 251 | return 1; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 252 | |
| 253 | /* unsupported features */ |
| 254 | case PIPE_CAP_ANISOTROPIC_FILTER: |
| 255 | case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: |
| 256 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: |
| 257 | case PIPE_CAP_SHADER_STENCIL_EXPORT: |
| 258 | case PIPE_CAP_TEXTURE_BARRIER: |
| 259 | case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: |
| 260 | case PIPE_CAP_VERTEX_COLOR_CLAMPED: |
| 261 | case PIPE_CAP_COMPUTE: |
Ilia Mirkin | c3dd5b2 | 2016-11-20 13:13:12 -0500 | [diff] [blame] | 262 | case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 263 | case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: |
| 264 | case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: |
| 265 | case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: |
| 266 | case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: |
| 267 | case PIPE_CAP_TEXTURE_MULTISAMPLE: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 268 | case PIPE_CAP_TGSI_TEXCOORD: |
| 269 | case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 270 | case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: |
| 271 | case PIPE_CAP_TEXTURE_GATHER_SM5: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 272 | case PIPE_CAP_TEXTURE_QUERY_LOD: |
| 273 | case PIPE_CAP_SAMPLE_SHADING: |
| 274 | case PIPE_CAP_TEXTURE_GATHER_OFFSETS: |
| 275 | case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: |
| 276 | case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: |
| 277 | case PIPE_CAP_SAMPLER_VIEW_TARGET: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 278 | case PIPE_CAP_VERTEXID_NOBASE: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 279 | case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 280 | case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 281 | case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 282 | case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 283 | case PIPE_CAP_TGSI_TXQS: |
| 284 | case PIPE_CAP_FORCE_PERSAMPLE_INTERP: |
| 285 | case PIPE_CAP_SHAREABLE_SHADERS: |
| 286 | case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: |
| 287 | case PIPE_CAP_CLEAR_TEXTURE: |
| 288 | case PIPE_CAP_DRAW_PARAMETERS: |
| 289 | case PIPE_CAP_TGSI_PACK_HALF_FLOAT: |
| 290 | case PIPE_CAP_MULTI_DRAW_INDIRECT: |
| 291 | case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: |
| 292 | case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: |
| 293 | case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: |
| 294 | case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: |
| 295 | case PIPE_CAP_INVALIDATE_BUFFER: |
| 296 | case PIPE_CAP_GENERATE_MIPMAP: |
| 297 | case PIPE_CAP_STRING_MARKER: |
| 298 | case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: |
| 299 | case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: |
| 300 | case PIPE_CAP_QUERY_BUFFER_OBJECT: |
| 301 | case PIPE_CAP_QUERY_MEMORY_INFO: |
Bas Nieuwenhuizen | 70dcd84 | 2016-04-12 15:00:31 +0200 | [diff] [blame] | 302 | case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: |
Tim Rowley | b9294bc | 2016-04-01 19:58:29 -0500 | [diff] [blame] | 303 | case PIPE_CAP_PCI_GROUP: |
| 304 | case PIPE_CAP_PCI_BUS: |
| 305 | case PIPE_CAP_PCI_DEVICE: |
| 306 | case PIPE_CAP_PCI_FUNCTION: |
Tim Rowley | 81c1c48 | 2016-04-21 11:10:29 -0500 | [diff] [blame] | 307 | case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: |
Kenneth Graunke | 70048eb | 2016-05-20 21:05:34 -0700 | [diff] [blame] | 308 | case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: |
Ilia Mirkin | edfa7a4 | 2016-05-29 11:39:52 -0400 | [diff] [blame] | 309 | case PIPE_CAP_TGSI_VOTE: |
Ilia Mirkin | 07fcb06 | 2016-06-11 15:26:45 -0400 | [diff] [blame] | 310 | case PIPE_CAP_MAX_WINDOW_RECTANGLES: |
Axel Davy | 59a6929 | 2016-06-13 22:28:32 +0200 | [diff] [blame] | 311 | case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: |
Józef Kucia | 3cd28fe | 2016-07-19 13:07:24 +0200 | [diff] [blame] | 312 | case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: |
Nicolai Hähnle | 700a571 | 2016-10-07 09:42:55 +0200 | [diff] [blame] | 313 | case PIPE_CAP_TGSI_ARRAY_COMPONENTS: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 314 | return 0; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 315 | |
| 316 | case PIPE_CAP_VENDOR_ID: |
| 317 | return 0xFFFFFFFF; |
| 318 | case PIPE_CAP_DEVICE_ID: |
| 319 | return 0xFFFFFFFF; |
| 320 | case PIPE_CAP_ACCELERATED: |
| 321 | return 0; |
| 322 | case PIPE_CAP_VIDEO_MEMORY: { |
| 323 | /* XXX: Do we want to return the full amount of system memory ? */ |
| 324 | uint64_t system_memory; |
| 325 | |
| 326 | if (!os_get_total_physical_memory(&system_memory)) |
| 327 | return 0; |
| 328 | |
| 329 | return (int)(system_memory >> 20); |
| 330 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | /* should only get here on unhandled cases */ |
| 334 | debug_printf("Unexpected PIPE_CAP %d query\n", param); |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | static int |
| 339 | swr_get_shader_param(struct pipe_screen *screen, |
| 340 | unsigned shader, |
| 341 | enum pipe_shader_cap param) |
| 342 | { |
| 343 | if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_FRAGMENT) |
| 344 | return gallivm_get_shader_param(param); |
| 345 | |
| 346 | // Todo: geometry, tesselation, compute |
| 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | |
| 351 | static float |
| 352 | swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param) |
| 353 | { |
| 354 | switch (param) { |
| 355 | case PIPE_CAPF_MAX_LINE_WIDTH: |
| 356 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: |
| 357 | case PIPE_CAPF_MAX_POINT_WIDTH: |
| 358 | return 255.0; /* arbitrary */ |
| 359 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: |
| 360 | return 0.0; |
| 361 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: |
| 362 | return 0.0; |
| 363 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: |
Ilia Mirkin | 2234a43 | 2016-11-19 10:10:47 -0500 | [diff] [blame] | 364 | return 16.0; /* arbitrary */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 365 | case PIPE_CAPF_GUARD_BAND_LEFT: |
| 366 | case PIPE_CAPF_GUARD_BAND_TOP: |
| 367 | case PIPE_CAPF_GUARD_BAND_RIGHT: |
| 368 | case PIPE_CAPF_GUARD_BAND_BOTTOM: |
| 369 | return 0.0; |
| 370 | } |
| 371 | /* should only get here on unhandled cases */ |
| 372 | debug_printf("Unexpected PIPE_CAPF %d query\n", param); |
| 373 | return 0.0; |
| 374 | } |
| 375 | |
| 376 | SWR_FORMAT |
| 377 | mesa_to_swr_format(enum pipe_format format) |
| 378 | { |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 379 | static const std::map<pipe_format,SWR_FORMAT> mesa2swr = { |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 380 | {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM}, |
| 381 | {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 382 | {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM}, |
| 383 | {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM}, |
| 384 | {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM}, |
| 385 | {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 386 | {PIPE_FORMAT_A8_UNORM, A8_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 387 | {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 388 | {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z |
| 389 | {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 390 | {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 391 | {PIPE_FORMAT_R32_FLOAT, R32_FLOAT}, |
| 392 | {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT}, |
| 393 | {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT}, |
| 394 | {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 395 | {PIPE_FORMAT_R32_USCALED, R32_USCALED}, |
| 396 | {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED}, |
| 397 | {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED}, |
| 398 | {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 399 | {PIPE_FORMAT_R32_SSCALED, R32_SSCALED}, |
| 400 | {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED}, |
| 401 | {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED}, |
| 402 | {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED}, |
| 403 | {PIPE_FORMAT_R16_UNORM, R16_UNORM}, |
| 404 | {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM}, |
| 405 | {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM}, |
| 406 | {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM}, |
| 407 | {PIPE_FORMAT_R16_USCALED, R16_USCALED}, |
| 408 | {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED}, |
| 409 | {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED}, |
| 410 | {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED}, |
| 411 | {PIPE_FORMAT_R16_SNORM, R16_SNORM}, |
| 412 | {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM}, |
| 413 | {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM}, |
| 414 | {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM}, |
| 415 | {PIPE_FORMAT_R16_SSCALED, R16_SSCALED}, |
| 416 | {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED}, |
| 417 | {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED}, |
| 418 | {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED}, |
| 419 | {PIPE_FORMAT_R8_UNORM, R8_UNORM}, |
| 420 | {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM}, |
| 421 | {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM}, |
| 422 | {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 423 | {PIPE_FORMAT_R8_USCALED, R8_USCALED}, |
| 424 | {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED}, |
| 425 | {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED}, |
| 426 | {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED}, |
| 427 | {PIPE_FORMAT_R8_SNORM, R8_SNORM}, |
| 428 | {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM}, |
| 429 | {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM}, |
| 430 | {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM}, |
| 431 | {PIPE_FORMAT_R8_SSCALED, R8_SSCALED}, |
| 432 | {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED}, |
| 433 | {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED}, |
| 434 | {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 435 | {PIPE_FORMAT_R16_FLOAT, R16_FLOAT}, |
| 436 | {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT}, |
| 437 | {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT}, |
| 438 | {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT}, |
| 439 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 440 | {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 441 | {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB}, |
| 442 | {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 443 | {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB}, |
| 444 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 445 | {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM}, |
| 446 | {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED}, |
| 447 | {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 448 | {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 449 | {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 450 | {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 451 | {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 452 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 453 | {PIPE_FORMAT_A16_UNORM, A16_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 454 | {PIPE_FORMAT_A16_FLOAT, A16_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 455 | {PIPE_FORMAT_A32_FLOAT, A32_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 456 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 457 | {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED}, |
| 458 | {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM}, |
| 459 | |
| 460 | {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED}, |
| 461 | {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED}, |
| 462 | {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM}, |
| 463 | |
| 464 | {PIPE_FORMAT_R8_UINT, R8_UINT}, |
| 465 | {PIPE_FORMAT_R8G8_UINT, R8G8_UINT}, |
| 466 | {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT}, |
| 467 | {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT}, |
| 468 | |
| 469 | {PIPE_FORMAT_R8_SINT, R8_SINT}, |
| 470 | {PIPE_FORMAT_R8G8_SINT, R8G8_SINT}, |
| 471 | {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT}, |
| 472 | {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT}, |
| 473 | |
| 474 | {PIPE_FORMAT_R16_UINT, R16_UINT}, |
| 475 | {PIPE_FORMAT_R16G16_UINT, R16G16_UINT}, |
| 476 | {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT}, |
| 477 | {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT}, |
| 478 | |
| 479 | {PIPE_FORMAT_R16_SINT, R16_SINT}, |
| 480 | {PIPE_FORMAT_R16G16_SINT, R16G16_SINT}, |
| 481 | {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT}, |
| 482 | {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT}, |
| 483 | |
| 484 | {PIPE_FORMAT_R32_UINT, R32_UINT}, |
| 485 | {PIPE_FORMAT_R32G32_UINT, R32G32_UINT}, |
| 486 | {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT}, |
| 487 | {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT}, |
| 488 | |
| 489 | {PIPE_FORMAT_R32_SINT, R32_SINT}, |
| 490 | {PIPE_FORMAT_R32G32_SINT, R32G32_SINT}, |
| 491 | {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT}, |
| 492 | {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT}, |
| 493 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 494 | {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT}, |
| 495 | |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 496 | {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM}, |
| 497 | {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 498 | {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 499 | {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 500 | {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT}, |
| 501 | |
Ilia Mirkin | 946a7ab | 2016-11-12 13:09:21 -0500 | [diff] [blame] | 502 | {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB}, |
| 503 | |
| 504 | /* These formats have entries in SWR but don't have Load/StoreTile |
| 505 | * implementations. That means these aren't renderable, and thus having |
| 506 | * a mapping entry here is detrimental. |
| 507 | */ |
| 508 | /* |
| 509 | |
| 510 | {PIPE_FORMAT_L8_UNORM, L8_UNORM}, |
| 511 | {PIPE_FORMAT_I8_UNORM, I8_UNORM}, |
| 512 | {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM}, |
| 513 | {PIPE_FORMAT_L16_UNORM, L16_UNORM}, |
| 514 | {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY}, |
| 515 | |
| 516 | {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB}, |
| 517 | {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB}, |
| 518 | |
| 519 | {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM}, |
| 520 | {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM}, |
| 521 | {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM}, |
| 522 | |
| 523 | {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB}, |
| 524 | {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB}, |
| 525 | {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB}, |
| 526 | |
| 527 | {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM}, |
| 528 | {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM}, |
| 529 | {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM}, |
| 530 | {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM}, |
| 531 | |
| 532 | {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM}, |
| 533 | {PIPE_FORMAT_I16_UNORM, I16_UNORM}, |
| 534 | {PIPE_FORMAT_L16_FLOAT, L16_FLOAT}, |
| 535 | {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT}, |
| 536 | {PIPE_FORMAT_I16_FLOAT, I16_FLOAT}, |
| 537 | {PIPE_FORMAT_L32_FLOAT, L32_FLOAT}, |
| 538 | {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT}, |
| 539 | {PIPE_FORMAT_I32_FLOAT, I32_FLOAT}, |
| 540 | |
| 541 | {PIPE_FORMAT_I8_UINT, I8_UINT}, |
| 542 | {PIPE_FORMAT_L8_UINT, L8_UINT}, |
| 543 | {PIPE_FORMAT_L8A8_UINT, L8A8_UINT}, |
| 544 | |
| 545 | {PIPE_FORMAT_I8_SINT, I8_SINT}, |
| 546 | {PIPE_FORMAT_L8_SINT, L8_SINT}, |
| 547 | {PIPE_FORMAT_L8A8_SINT, L8A8_SINT}, |
| 548 | |
| 549 | */ |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 550 | }; |
| 551 | |
Ilia Mirkin | 2b7bdff | 2016-11-12 22:18:48 -0500 | [diff] [blame] | 552 | auto it = mesa2swr.find(format); |
| 553 | if (it == mesa2swr.end()) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 554 | return (SWR_FORMAT)-1; |
Ilia Mirkin | 2b7bdff | 2016-11-12 22:18:48 -0500 | [diff] [blame] | 555 | else |
| 556 | return it->second; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | static boolean |
| 560 | swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res) |
| 561 | { |
| 562 | struct sw_winsys *winsys = screen->winsys; |
| 563 | struct sw_displaytarget *dt; |
| 564 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 565 | const unsigned width = align(res->swr.width, res->swr.halign); |
| 566 | const unsigned height = align(res->swr.height, res->swr.valign); |
| 567 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 568 | UINT stride; |
| 569 | dt = winsys->displaytarget_create(winsys, |
| 570 | res->base.bind, |
| 571 | res->base.format, |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 572 | width, height, |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 573 | 64, NULL, |
| 574 | &stride); |
| 575 | |
| 576 | if (dt == NULL) |
| 577 | return FALSE; |
| 578 | |
| 579 | void *map = winsys->displaytarget_map(winsys, dt, 0); |
| 580 | |
| 581 | res->display_target = dt; |
| 582 | res->swr.pBaseAddress = (uint8_t*) map; |
| 583 | |
| 584 | /* Clear the display target surface */ |
| 585 | if (map) |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 586 | memset(map, 0, height * stride); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 587 | |
| 588 | winsys->displaytarget_unmap(winsys, dt); |
| 589 | |
| 590 | return TRUE; |
| 591 | } |
| 592 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 593 | static bool |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 594 | swr_texture_layout(struct swr_screen *screen, |
| 595 | struct swr_resource *res, |
| 596 | boolean allocate) |
| 597 | { |
| 598 | struct pipe_resource *pt = &res->base; |
| 599 | |
| 600 | pipe_format fmt = pt->format; |
| 601 | const struct util_format_description *desc = util_format_description(fmt); |
| 602 | |
| 603 | res->has_depth = util_format_has_depth(desc); |
| 604 | res->has_stencil = util_format_has_stencil(desc); |
| 605 | |
| 606 | if (res->has_stencil && !res->has_depth) |
| 607 | fmt = PIPE_FORMAT_R8_UINT; |
| 608 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 609 | /* We always use the SWR layout. For 2D and 3D textures this looks like: |
| 610 | * |
| 611 | * |<------- pitch ------->| |
| 612 | * +=======================+------- |
| 613 | * |Array 0 | ^ |
| 614 | * | | | |
| 615 | * | Level 0 | | |
| 616 | * | | | |
| 617 | * | | qpitch |
| 618 | * +-----------+-----------+ | |
| 619 | * | | L2L2L2L2 | | |
| 620 | * | Level 1 | L3L3 | | |
| 621 | * | | L4 | v |
| 622 | * +===========+===========+------- |
| 623 | * |Array 1 | |
| 624 | * | | |
| 625 | * | Level 0 | |
| 626 | * | | |
| 627 | * | | |
| 628 | * +-----------+-----------+ |
| 629 | * | | L2L2L2L2 | |
| 630 | * | Level 1 | L3L3 | |
| 631 | * | | L4 | |
| 632 | * +===========+===========+ |
| 633 | * |
| 634 | * The overall width in bytes is known as the pitch, while the overall |
| 635 | * height in rows is the qpitch. Array slices are laid out logically below |
| 636 | * one another, qpitch rows apart. For 3D surfaces, the "level" values are |
| 637 | * just invalid for the higher array numbers (since depth is also |
| 638 | * minified). 1D and 1D array surfaces are stored effectively the same way, |
| 639 | * except that pitch never plays into it. All the levels are logically |
| 640 | * adjacent to each other on the X axis. The qpitch becomes the number of |
| 641 | * elements between array slices, while the pitch is unused. |
| 642 | * |
| 643 | * Each level's sizes are subject to the valign and halign settings of the |
| 644 | * surface. For compressed formats that swr is unaware of, we will use an |
| 645 | * appropriately-sized uncompressed format, and scale the widths/heights. |
| 646 | * |
| 647 | * This surface is stored inside res->swr. For depth/stencil textures, |
| 648 | * res->secondary will have an identically-laid-out but R8_UINT-formatted |
| 649 | * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp |
| 650 | * texels, to simplify map/unmap logic which copies the stencil values |
| 651 | * in/out. |
| 652 | */ |
| 653 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 654 | res->swr.width = pt->width0; |
| 655 | res->swr.height = pt->height0; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 656 | res->swr.type = swr_convert_target_type(pt->target); |
| 657 | res->swr.tileMode = SWR_TILE_NONE; |
| 658 | res->swr.format = mesa_to_swr_format(fmt); |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 659 | res->swr.numSamples = std::max(1u, pt->nr_samples); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 660 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 661 | if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) { |
| 662 | res->swr.halign = KNOB_MACROTILE_X_DIM; |
| 663 | res->swr.valign = KNOB_MACROTILE_Y_DIM; |
| 664 | } else { |
| 665 | res->swr.halign = 1; |
| 666 | res->swr.valign = 1; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 667 | } |
| 668 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 669 | unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt); |
| 670 | unsigned width = align(pt->width0, halign); |
| 671 | if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) { |
| 672 | for (int level = 1; level <= pt->last_level; level++) |
| 673 | width += align(u_minify(pt->width0, level), halign); |
| 674 | res->swr.pitch = util_format_get_blocksize(fmt); |
| 675 | res->swr.qpitch = util_format_get_nblocksx(fmt, width); |
| 676 | } else { |
| 677 | // The pitch is the overall width of the texture in bytes. Most of the |
| 678 | // time this is the pitch of level 0 since all the other levels fit |
| 679 | // underneath it. However in some degenerate situations, the width of |
| 680 | // level1 + level2 may be larger. In that case, we use those |
| 681 | // widths. This can happen if, e.g. halign is 32, and the width of level |
| 682 | // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also |
| 683 | // be 32 each, adding up to 64. |
| 684 | unsigned valign = res->swr.valign * util_format_get_blockheight(fmt); |
| 685 | if (pt->last_level > 1) { |
| 686 | width = std::max<uint32_t>( |
| 687 | width, |
| 688 | align(u_minify(pt->width0, 1), halign) + |
| 689 | align(u_minify(pt->width0, 2), halign)); |
| 690 | } |
| 691 | res->swr.pitch = util_format_get_stride(fmt, width); |
| 692 | |
| 693 | // The qpitch is controlled by either the height of the second LOD, or |
| 694 | // the combination of all the later LODs. |
| 695 | unsigned height = align(pt->height0, valign); |
| 696 | if (pt->last_level == 1) { |
| 697 | height += align(u_minify(pt->height0, 1), valign); |
| 698 | } else if (pt->last_level > 1) { |
| 699 | unsigned level1 = align(u_minify(pt->height0, 1), valign); |
| 700 | unsigned level2 = 0; |
| 701 | for (int level = 2; level <= pt->last_level; level++) { |
| 702 | level2 += align(u_minify(pt->height0, level), valign); |
| 703 | } |
| 704 | height += std::max(level1, level2); |
| 705 | } |
| 706 | res->swr.qpitch = util_format_get_nblocksy(fmt, height); |
| 707 | } |
| 708 | |
| 709 | if (pt->target == PIPE_TEXTURE_3D) |
| 710 | res->swr.depth = pt->depth0; |
| 711 | else |
| 712 | res->swr.depth = pt->array_size; |
| 713 | |
| 714 | // Fix up swr format if necessary so that LOD offset computation works |
| 715 | if (res->swr.format == (SWR_FORMAT)-1) { |
| 716 | switch (util_format_get_blocksize(fmt)) { |
| 717 | default: |
| 718 | unreachable("Unexpected format block size"); |
| 719 | case 1: res->swr.format = R8_UINT; break; |
| 720 | case 2: res->swr.format = R16_UINT; break; |
| 721 | case 4: res->swr.format = R32_UINT; break; |
| 722 | case 8: |
| 723 | if (util_format_is_compressed(fmt)) |
| 724 | res->swr.format = BC4_UNORM; |
| 725 | else |
| 726 | res->swr.format = R32G32_UINT; |
| 727 | break; |
| 728 | case 16: |
| 729 | if (util_format_is_compressed(fmt)) |
| 730 | res->swr.format = BC5_UNORM; |
| 731 | else |
| 732 | res->swr.format = R32G32B32A32_UINT; |
| 733 | break; |
| 734 | } |
| 735 | } |
| 736 | |
| 737 | for (int level = 0; level <= pt->last_level; level++) { |
| 738 | res->mip_offsets[level] = |
| 739 | ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr); |
| 740 | } |
| 741 | |
| 742 | size_t total_size = |
| 743 | (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch; |
| 744 | if (total_size > SWR_MAX_TEXTURE_SIZE) |
| 745 | return false; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 746 | |
| 747 | if (allocate) { |
Tim Rowley | 4997169 | 2016-05-06 12:49:23 -0600 | [diff] [blame] | 748 | res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 749 | |
| 750 | if (res->has_depth && res->has_stencil) { |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 751 | res->secondary = res->swr; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 752 | res->secondary.format = R8_UINT; |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 753 | res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt); |
| 754 | |
| 755 | for (int level = 0; level <= pt->last_level; level++) { |
| 756 | res->secondary_mip_offsets[level] = |
| 757 | ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary); |
| 758 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 759 | |
Tim Rowley | 4997169 | 2016-05-06 12:49:23 -0600 | [diff] [blame] | 760 | res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc( |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 761 | res->secondary.depth * res->secondary.qpitch * |
| 762 | res->secondary.pitch, 64); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 763 | } |
| 764 | } |
| 765 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 766 | return true; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | static boolean |
| 770 | swr_can_create_resource(struct pipe_screen *screen, |
| 771 | const struct pipe_resource *templat) |
| 772 | { |
| 773 | struct swr_resource res; |
| 774 | memset(&res, 0, sizeof(res)); |
| 775 | res.base = *templat; |
| 776 | return swr_texture_layout(swr_screen(screen), &res, false); |
| 777 | } |
| 778 | |
| 779 | static struct pipe_resource * |
| 780 | swr_resource_create(struct pipe_screen *_screen, |
| 781 | const struct pipe_resource *templat) |
| 782 | { |
| 783 | struct swr_screen *screen = swr_screen(_screen); |
| 784 | struct swr_resource *res = CALLOC_STRUCT(swr_resource); |
| 785 | if (!res) |
| 786 | return NULL; |
| 787 | |
| 788 | res->base = *templat; |
| 789 | pipe_reference_init(&res->base.reference, 1); |
| 790 | res->base.screen = &screen->base; |
| 791 | |
| 792 | if (swr_resource_is_texture(&res->base)) { |
| 793 | if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
| 794 | | PIPE_BIND_SHARED)) { |
| 795 | /* displayable surface |
| 796 | * first call swr_texture_layout without allocating to finish |
| 797 | * filling out the SWR_SURFAE_STATE in res */ |
| 798 | swr_texture_layout(screen, res, false); |
| 799 | if (!swr_displaytarget_layout(screen, res)) |
| 800 | goto fail; |
| 801 | } else { |
| 802 | /* texture map */ |
| 803 | if (!swr_texture_layout(screen, res, true)) |
| 804 | goto fail; |
| 805 | } |
| 806 | } else { |
| 807 | /* other data (vertex buffer, const buffer, etc) */ |
| 808 | assert(util_format_get_blocksize(templat->format) == 1); |
| 809 | assert(templat->height0 == 1); |
| 810 | assert(templat->depth0 == 1); |
| 811 | assert(templat->last_level == 0); |
| 812 | |
| 813 | /* Easiest to just call swr_texture_layout, as it sets up |
| 814 | * SWR_SURFAE_STATE in res */ |
| 815 | if (!swr_texture_layout(screen, res, true)) |
| 816 | goto fail; |
| 817 | } |
| 818 | |
| 819 | return &res->base; |
| 820 | |
| 821 | fail: |
| 822 | FREE(res); |
| 823 | return NULL; |
| 824 | } |
| 825 | |
| 826 | static void |
| 827 | swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt) |
| 828 | { |
| 829 | struct swr_screen *screen = swr_screen(p_screen); |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 830 | struct swr_resource *spr = swr_resource(pt); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 831 | struct pipe_context *pipe = screen->pipe; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 832 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 833 | /* Only wait on fence if the resource is being used */ |
| 834 | if (pipe && spr->status) { |
| 835 | /* But, if there's no fence pending, submit one. |
| 836 | * XXX: Remove once draw timestamps are implmented. */ |
| 837 | if (!swr_is_fence_pending(screen->flush_fence)) |
| 838 | swr_fence_submit(swr_context(pipe), screen->flush_fence); |
| 839 | |
Marek Olšák | 54272e1 | 2016-08-06 16:41:42 +0200 | [diff] [blame] | 840 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 841 | swr_resource_unused(pt); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 842 | } |
| 843 | |
| 844 | /* |
| 845 | * Free resource primary surface. If resource is display target, winsys |
| 846 | * manages the buffer and will free it on displaytarget_destroy. |
| 847 | */ |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 848 | if (spr->display_target) { |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 849 | /* display target */ |
| 850 | struct sw_winsys *winsys = screen->winsys; |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 851 | winsys->displaytarget_destroy(winsys, spr->display_target); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 852 | } else |
Tim Rowley | 4997169 | 2016-05-06 12:49:23 -0600 | [diff] [blame] | 853 | AlignedFree(spr->swr.pBaseAddress); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 854 | |
Tim Rowley | 4997169 | 2016-05-06 12:49:23 -0600 | [diff] [blame] | 855 | AlignedFree(spr->secondary.pBaseAddress); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 856 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 857 | FREE(spr); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 858 | } |
| 859 | |
| 860 | |
| 861 | static void |
| 862 | swr_flush_frontbuffer(struct pipe_screen *p_screen, |
| 863 | struct pipe_resource *resource, |
| 864 | unsigned level, |
| 865 | unsigned layer, |
| 866 | void *context_private, |
| 867 | struct pipe_box *sub_box) |
| 868 | { |
| 869 | struct swr_screen *screen = swr_screen(p_screen); |
| 870 | struct sw_winsys *winsys = screen->winsys; |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 871 | struct swr_resource *spr = swr_resource(resource); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 872 | struct pipe_context *pipe = screen->pipe; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 873 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 874 | if (pipe) { |
Marek Olšák | 54272e1 | 2016-08-06 16:41:42 +0200 | [diff] [blame] | 875 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 876 | swr_resource_unused(resource); |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 877 | SwrEndFrame(swr_context(pipe)->swrContext); |
| 878 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 879 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 880 | debug_assert(spr->display_target); |
| 881 | if (spr->display_target) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 882 | winsys->displaytarget_display( |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 883 | winsys, spr->display_target, context_private, sub_box); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | |
| 887 | static void |
| 888 | swr_destroy_screen(struct pipe_screen *p_screen) |
| 889 | { |
| 890 | struct swr_screen *screen = swr_screen(p_screen); |
| 891 | struct sw_winsys *winsys = screen->winsys; |
| 892 | |
| 893 | fprintf(stderr, "SWR destroy screen!\n"); |
| 894 | |
Marek Olšák | 54272e1 | 2016-08-06 16:41:42 +0200 | [diff] [blame] | 895 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 896 | swr_fence_reference(p_screen, &screen->flush_fence, NULL); |
| 897 | |
| 898 | JitDestroyContext(screen->hJitMgr); |
| 899 | |
| 900 | if (winsys->destroy) |
| 901 | winsys->destroy(winsys); |
| 902 | |
| 903 | FREE(screen); |
| 904 | } |
| 905 | |
| 906 | PUBLIC |
| 907 | struct pipe_screen * |
George Kyriazis | 87bd282 | 2016-11-17 16:21:12 -0600 | [diff] [blame] | 908 | swr_create_screen_internal(struct sw_winsys *winsys) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 909 | { |
| 910 | struct swr_screen *screen = CALLOC_STRUCT(swr_screen); |
| 911 | |
| 912 | if (!screen) |
| 913 | return NULL; |
| 914 | |
| 915 | if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) { |
| 916 | g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152); |
| 917 | } |
| 918 | |
| 919 | screen->winsys = winsys; |
| 920 | screen->base.get_name = swr_get_name; |
| 921 | screen->base.get_vendor = swr_get_vendor; |
| 922 | screen->base.is_format_supported = swr_is_format_supported; |
| 923 | screen->base.context_create = swr_create_context; |
| 924 | screen->base.can_create_resource = swr_can_create_resource; |
| 925 | |
| 926 | screen->base.destroy = swr_destroy_screen; |
| 927 | screen->base.get_param = swr_get_param; |
| 928 | screen->base.get_shader_param = swr_get_shader_param; |
| 929 | screen->base.get_paramf = swr_get_paramf; |
| 930 | |
| 931 | screen->base.resource_create = swr_resource_create; |
| 932 | screen->base.resource_destroy = swr_resource_destroy; |
| 933 | |
| 934 | screen->base.flush_frontbuffer = swr_flush_frontbuffer; |
| 935 | |
Tim Rowley | 9aa75e5 | 2016-08-09 15:29:06 -0600 | [diff] [blame] | 936 | screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr"); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 937 | |
| 938 | swr_fence_init(&screen->base); |
| 939 | |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 940 | util_format_s3tc_init(); |
| 941 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 942 | return &screen->base; |
| 943 | } |
| 944 | |